/* UART test using ACV */
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/* UART test using ACV */
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#include "spr_defs.h"
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#include "spr_defs.h"
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#include "support.h"
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#include "support.h"
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#define UART_ADDR (0x9c000000)
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#define UART_ADDR (0x9c000000)
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#define UART_RBR (UART_ADDR + 0)
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#define UART_RBR (UART_ADDR + 0)
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#define UART_THR (UART_ADDR + 0)
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#define UART_THR (UART_ADDR + 0)
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#define UART_IER (UART_ADDR + 1)
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#define UART_IER (UART_ADDR + 1)
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#define UART_IIR (UART_ADDR + 2)
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#define UART_IIR (UART_ADDR + 2)
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#define UART_FCR (UART_ADDR + 2)
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#define UART_FCR (UART_ADDR + 2)
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#define UART_LCR (UART_ADDR + 3)
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#define UART_LCR (UART_ADDR + 3)
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#define UART_MCR (UART_ADDR + 4)
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#define UART_MCR (UART_ADDR + 4)
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#define UART_LSR (UART_ADDR + 5)
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#define UART_LSR (UART_ADDR + 5)
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#define UART_MSR (UART_ADDR + 6)
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#define UART_MSR (UART_ADDR + 6)
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#define UART_DLL (UART_ADDR + 0)
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#define UART_DLL (UART_ADDR + 0)
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#define UART_DLH (UART_ADDR + 1)
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#define UART_DLH (UART_ADDR + 1)
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#define LCR_DIVL (0x80)
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#define LCR_DIVL (0x80)
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#define LCR_BREAK (0x40)
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#define LCR_BREAK (0x40)
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#define LCR_STICK (0x20)
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#define LCR_STICK (0x20)
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#define LCR_EVENP (0x10)
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#define LCR_EVENP (0x10)
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#define LCR_PAREN (0x08)
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#define LCR_PAREN (0x08)
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#define LCR_NSTOP (0x04)
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#define LCR_NSTOP (0x04)
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#define LCR_NBITS (0x03)
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#define LCR_NBITS (0x03)
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#define LSR_DR (0x01)
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#define LSR_DR (0x01)
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#define LSR_OE (0x02)
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#define LSR_OE (0x02)
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#define LSR_PE (0x04)
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#define LSR_PE (0x04)
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#define LSR_FE (0x08)
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#define LSR_FE (0x08)
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#define LSR_BREAK (0x10)
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#define LSR_BREAK (0x10)
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#define LSR_TXFE (0x20)
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#define LSR_TXFE (0x20)
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#define LSR_TXE (0x40)
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#define LSR_TXE (0x40)
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#define LSR_ERR (0x80)
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#define LSR_ERR (0x80)
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/* fails if x is false */
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/* fails if x is false */
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#define ASSERT(x) ((x)?1: fail (__FUNCTION__, __LINE__))
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#define ASSERT(x) ((x)?1: fail (__FUNCTION__, __LINE__))
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/* Waits a few cycles that uart can prepare its data */
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/* Waits a few cycles that uart can prepare its data */
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#define WAIT() {asm ("l.nop");asm ("l.nop");asm ("l.nop");asm ("l.nop");}
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#define WAIT() {asm ("l.nop");asm ("l.nop");asm ("l.nop");asm ("l.nop");}
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/* fails if there is an error */
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/* fails if there is an error */
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#define NO_ERROR() { unsigned x = getreg (UART_LSR); if ((x & (LSR_BREAK|LSR_FE|LSR_PE|LSR_OE)) && !(x & LSR_ERR)) \
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#define NO_ERROR() { unsigned x = getreg (UART_LSR); if ((x & (LSR_BREAK|LSR_FE|LSR_PE|LSR_OE)) && !(x & LSR_ERR)) \
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printf ("LSR7 ERR\n"); ASSERT(!(x & LSR_ERR));}
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printf ("LSR7 ERR\n"); ASSERT(!(x & LSR_ERR));}
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#ifndef __LINE__
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#ifndef __LINE__
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#define __LINE__ 0
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#define __LINE__ 0
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#endif
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#endif
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void fail (char *func, int line)
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void fail (char *func, int line)
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{
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{
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#ifndef __FUNCTION__
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#ifndef __FUNCTION__
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#define __FUNCTION__ "?"
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#define __FUNCTION__ "?"
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#endif
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#endif
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printf ("Test failed in %s:%i\n", func, line);
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printf ("Test failed in %s:%i\n", func, line);
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exit (1);
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exit (1);
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}
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}
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inline void setreg (unsigned long addr, unsigned char value)
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inline void setreg (unsigned long addr, unsigned char value)
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{
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{
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*((volatile unsigned char *)addr) = value;
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*((volatile unsigned char *)addr) = value;
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}
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}
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inline unsigned long getreg (unsigned long addr)
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inline unsigned long getreg (unsigned long addr)
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{
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{
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return *((volatile unsigned char *)addr);
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return *((volatile unsigned char *)addr);
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}
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}
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void interrupt_handler ()
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void interrupt_handler ()
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{
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{
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printf ("Int\n");
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printf ("Int\n");
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}
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}
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/* Test reset values and r/w properties of some registers */
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/* Test reset values and r/w properties of some registers */
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void register_test ()
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void register_test ()
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{
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{
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printf ("register test\n");
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printf ("register test\n");
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{ /* test reset values */
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{ /* test reset values */
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ASSERT(getreg (UART_RBR) == 0x00); //0
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ASSERT(getreg (UART_RBR) == 0x00); //0
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ASSERT(getreg (UART_IER) == 0x00); //1
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ASSERT(getreg (UART_IER) == 0x00); //1
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ASSERT(getreg (UART_IIR) == 0xc1); //2
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ASSERT(getreg (UART_IIR) == 0xc1); //2
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ASSERT(getreg (UART_LCR) == 0x03); //3
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ASSERT(getreg (UART_LCR) == 0x03); //3
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ASSERT(getreg (UART_MCR) == 0x00); //4
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ASSERT(getreg (UART_MCR) == 0x00); //4
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ASSERT(getreg (UART_LSR) == 0x60); //5
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ASSERT(getreg (UART_LSR) == 0x60); //5
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ASSERT(getreg (UART_MSR) == 0x00); //6
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// ASSERT(getreg (UART_MSR) == 0xff); //6
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// ASSERT(getreg (UART_MSR) == 0x00); //6
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setreg(UART_LCR, LCR_DIVL); //enable latches
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setreg(UART_LCR, LCR_DIVL); //enable latches
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ASSERT(getreg (UART_DLL) == 0x00); //0
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ASSERT(getreg (UART_DLL) == 0x00); //0
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ASSERT(getreg (UART_DLH) == 0x00); //1
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ASSERT(getreg (UART_DLH) == 0x00); //1
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setreg(UART_LCR, 0x00); //disable latches
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setreg(UART_LCR, 0x00); //disable latches
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}
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}
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{ /* test if status registers are read only */
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{ /* test if status registers are read only */
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unsigned long tmp;
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unsigned long tmp;
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int i;
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int i;
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tmp = getreg (UART_LSR);
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tmp = getreg (UART_LSR);
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setreg (UART_LSR, ~tmp);
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setreg (UART_LSR, ~tmp);
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ASSERT(getreg (UART_LSR) == tmp);
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ASSERT(getreg (UART_LSR) == tmp);
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for (i = 0; i < 9; i++) {
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for (i = 0; i < 9; i++) {
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setreg (UART_LSR, 1 < i);
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setreg (UART_LSR, 1 << i);
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ASSERT(getreg (UART_LSR) == tmp);
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ASSERT(getreg (UART_LSR) == tmp);
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}
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}
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tmp = getreg (UART_MSR);
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/*tmp = getreg (UART_MSR);
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setreg (UART_MSR, ~tmp);
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setreg (UART_MSR, ~tmp);
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ASSERT(getreg (UART_MSR) == tmp);
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ASSERT(getreg (UART_MSR) == tmp);
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for (i = 0; i < 9; i++) {
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for (i = 0; i < 9; i++) {
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setreg (UART_MSR, 1 < i);
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setreg (UART_MSR, 1 << i);
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ASSERT(getreg (UART_MSR) == tmp);
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ASSERT(getreg (UART_MSR) == tmp);
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}
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}*/
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}
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}
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ASSERT (!(getreg (UART_LSR) & 0x1f));
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ASSERT (!(getreg (UART_LSR) & 0x1f));
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{ /* test whether MCR is write only, be careful not to set the loopback bit */
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{ /* test whether MCR is write only, be careful not to set the loopback bit */
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ASSERT(getreg (UART_MCR) == 0x00);
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/*ASSERT(getreg (UART_MCR) == 0x00);
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setreg (UART_MCR, 0x45);
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setreg (UART_MCR, 0x45);
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ASSERT(getreg (UART_MCR) == 0x00);
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ASSERT(getreg (UART_MCR) == 0x00);
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setreg (UART_MCR, 0xaa);
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setreg (UART_MCR, 0xaa);
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ASSERT(getreg (UART_MCR) == 0x00);
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ASSERT(getreg (UART_MCR) == 0x00);*/
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}
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}
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ASSERT (!(getreg (UART_LSR) & 0x1f));
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ASSERT (!(getreg (UART_LSR) & 0x1f));
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{ /* Test if Divisor latch byte holds the data */
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{ /* Test if Divisor latch byte holds the data */
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int i;
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int i;
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setreg(UART_LCR, LCR_DIVL); //enable latches
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setreg(UART_LCR, LCR_DIVL); //enable latches
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ASSERT(getreg (UART_LCR) == LCR_DIVL);
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ASSERT(getreg (UART_LCR) == LCR_DIVL);
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for (i = 0; i < 16; i++) {
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for (i = 0; i < 16; i++) {
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unsigned short tmp = 0xdead << i;
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unsigned short tmp = 0xdead << i;
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setreg (UART_DLH, tmp >> 8);
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setreg (UART_DLH, tmp >> 8);
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setreg (UART_DLL, tmp & 0xff);
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setreg (UART_DLL, tmp & 0xff);
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ASSERT(getreg (UART_DLL) == (tmp & 0xff)); //0
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ASSERT(getreg (UART_DLL) == (tmp & 0xff)); //0
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ASSERT(getreg (UART_DLH) == (tmp >> 8)); //1
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ASSERT(getreg (UART_DLH) == (tmp >> 8)); //1
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}
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}
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ASSERT (!(getreg (UART_LSR) & 0x1f));
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ASSERT (!(getreg (UART_LSR) & 0x1f));
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for (i = 0; i < 16; i++) {
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for (i = 0; i < 16; i++) {
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unsigned short tmp = 0xdead << i;
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unsigned short tmp = 0xdead << i;
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setreg (UART_DLL, tmp >> 8);
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setreg (UART_DLL, tmp >> 8);
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setreg (UART_DLH, tmp & 0xff);
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setreg (UART_DLH, tmp & 0xff);
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ASSERT(getreg (UART_DLL) == (tmp >> 8)); //1
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ASSERT(getreg (UART_DLL) == (tmp >> 8)); //1
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ASSERT(getreg (UART_DLH) == (tmp & 0xff)); //0
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ASSERT(getreg (UART_DLH) == (tmp & 0xff)); //0
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}
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}
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setreg(UART_LCR, 0x00); //disable latches
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setreg(UART_LCR, 0x00); //disable latches
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ASSERT(getreg (UART_LCR) == 0x00);
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ASSERT(getreg (UART_LCR) == 0x00);
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ASSERT (!(getreg (UART_LSR) & 0x1f));
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ASSERT (!(getreg (UART_LSR) & 0x1f));
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}
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}
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{ /* Test LCR, if it holds our data */
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{ /* Test LCR, if it holds our data */
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int i;
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int i;
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for (i = 0; i < 6; i++) {
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for (i = 0; i < 6; i++) {
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unsigned short tmp = (0xde << i) & 0x3f;
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unsigned short tmp = (0xde << i) & 0x3f;
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setreg (UART_LCR, tmp);
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setreg (UART_LCR, tmp);
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ASSERT(getreg (UART_LCR) == tmp);
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ASSERT(getreg (UART_LCR) == tmp);
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}
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}
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ASSERT (!(getreg (UART_LSR) & 0x1f));
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ASSERT (!(getreg (UART_LSR) & 0x1f));
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}
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}
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/* Other registers will be tested later, if they function correctly,
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/* Other registers will be tested later, if they function correctly,
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since we cannot test them now, without destroying anything. */
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since we cannot test them now, without destroying anything. */
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}
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}
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/* Initializes uart and sends a few bytes to VAPI. It is then activated and send something back. */
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/* Initializes uart and sends a few bytes to VAPI. It is then activated and send something back. */
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void send_recv_test ()
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void send_recv_test ()
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{
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{
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char *s;
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char *s;
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printf ("send_recv_test: ");
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printf ("send_recv_test: ");
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/* Init */
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/* Init */
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setreg (UART_IER, 0x00); /* disable interrupts */
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setreg (UART_IER, 0x00); /* disable interrupts */
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WAIT();
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WAIT();
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ASSERT(getreg (UART_IIR) == 0xc1); /* nothing should be happening */
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ASSERT(getreg (UART_IIR) == 0xc1); /* nothing should be happening */
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setreg (UART_FCR, 0x06); /* clear RX and TX FIFOs */
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setreg (UART_FCR, 0x06); /* clear RX and TX FIFOs */
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setreg (UART_LCR, LCR_DIVL);
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setreg (UART_LCR, LCR_DIVL);
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setreg (UART_DLH, 10 >> 8);
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setreg (UART_DLH, 10 >> 8);
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setreg (UART_DLL, 10 & 0xff);
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setreg (UART_DLL, 10 & 0xff);
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setreg (UART_LCR, 0x03); /* 8N1 @ 10 => 160 instructions for one cycle */
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setreg (UART_LCR, 0x03); /* 8N1 @ 10 => 160 instructions for one cycle */
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ASSERT(getreg (UART_LCR) == 0x03);
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ASSERT(getreg (UART_LCR) == 0x03);
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//printf ("basic\n");
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//printf ("basic\n");
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ASSERT (!(getreg (UART_LSR) & LSR_DR));
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ASSERT (!(getreg (UART_LSR) & LSR_DR));
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/* Send a string */
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/* Send a string */
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s = "send_";
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s = "send_";
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while (*s) {
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while (*s) {
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/* Wait for tx fifo to be empty */
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/* Wait for tx fifo to be empty */
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while (!(getreg (UART_LSR) & LSR_TXFE));
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while (!(getreg (UART_LSR) & LSR_TXFE));
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NO_ERROR();
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NO_ERROR();
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setreg (UART_THR, *s); /* send character */
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setreg (UART_THR, *s); /* send character */
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NO_ERROR();
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NO_ERROR();
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report((unsigned long)*s);
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s++;
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s++;
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}
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}
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ASSERT (!(getreg (UART_LSR) & LSR_DR));
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ASSERT (!(getreg (UART_LSR) & LSR_DR));
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s = "test_";
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s = "test_";
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while (*s) {
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while (*s) {
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/* Wait for tx fifo and tx to be empty */
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/* Wait for tx fifo and tx to be empty */
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while (!(getreg (UART_LSR) & LSR_TXE));
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while (!(getreg (UART_LSR) & LSR_TXE));
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NO_ERROR();
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NO_ERROR();
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setreg (UART_THR, *s); /* send character */
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setreg (UART_THR, *s); /* send character */
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NO_ERROR();
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NO_ERROR();
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s++;
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s++;
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}
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}
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ASSERT (!(getreg (UART_LSR) & LSR_DR));
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ASSERT (!(getreg (UART_LSR) & LSR_DR));
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/* Send characters with delay inbetween */
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/* Send characters with delay inbetween */
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s = "is_running";
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s = "is_running";
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while (*s) {
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while (*s) {
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int i;
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int i;
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/* Wait for tx fifo and tx to be empty */
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/* Wait for tx fifo and tx to be empty */
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while (!(getreg (UART_LSR) & LSR_TXE));
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while (!(getreg (UART_LSR) & LSR_TXE));
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NO_ERROR();
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NO_ERROR();
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setreg (UART_THR, *s); /* send character */
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setreg (UART_THR, *s); /* send character */
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NO_ERROR();
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NO_ERROR();
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for (i = 0; i < 1600; i++) /* wait at least ten chars before sending next one */
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// igor for (i = 0; i < 1600; i++) /* wait at least ten chars before sending next one */
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for (i = 0; i < 16; i++) /* wait at least ten chars before sending next one */
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asm volatile ("l.nop");
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asm volatile ("l.nop");
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s++;
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s++;
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}
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}
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while (!(getreg (UART_LSR) & LSR_TXE));
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while (!(getreg (UART_LSR) & LSR_TXE));
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NO_ERROR();
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NO_ERROR();
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setreg (UART_THR, 0); /* send terminate character */
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setreg (UART_THR, 0); /* send terminate character */
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NO_ERROR();
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NO_ERROR();
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/* Receives and compares the string */
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/* Receives and compares the string */
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s = "recv_test";
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s = "recv_test";
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while (*s) {
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while (*s) {
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/* Wait for rx fifo to be */
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/* Wait for rx fifo to be */
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while (!(getreg (UART_LSR) & LSR_DR));
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while (!(getreg (UART_LSR) & LSR_DR));
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NO_ERROR();
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NO_ERROR();
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ASSERT (getreg (UART_RBR) == *s); /* compare character */
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ASSERT (getreg (UART_RBR) == *s); /* compare character */
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NO_ERROR();
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NO_ERROR();
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s++;
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s++;
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}
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}
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printf ("OK\n");
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printf ("OK\n");
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}
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}
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/* sends break in both directions */
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/* sends break in both directions */
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void break_test ()
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void break_test ()
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{
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{
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char *s;
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char *s;
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printf ("break_test: ");
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printf ("break_test: ");
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/* Send and receive break */
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/* Send and receive break */
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NO_ERROR();
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NO_ERROR();
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setreg (UART_LCR, LCR_BREAK);
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setreg (UART_LCR, LCR_BREAK);
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while (!(getreg (UART_LSR) & LSR_BREAK));
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while (!(getreg (UART_LSR) & LSR_BREAK));
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setreg (UART_THR, '*');
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setreg (UART_THR, '*');
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while (getreg (UART_LSR) & LSR_BREAK);
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while (getreg (UART_LSR) & LSR_BREAK);
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NO_ERROR(); /* BREAK bit should be cleared */
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NO_ERROR(); /* BREAK bit should be cleared */
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/* Break while sending characters */
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/* Break while sending characters */
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s = "no_star";
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s = "no_star";
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while (*s) {
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while (*s) {
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/* Wait for tx fifo to be empty */
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/* Wait for tx fifo to be empty */
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while (!(getreg (UART_LSR) & LSR_TXFE));
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while (!(getreg (UART_LSR) & LSR_TXFE));
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NO_ERROR();
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NO_ERROR();
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setreg (UART_THR, *s); /* send character */
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setreg (UART_THR, *s); /* send character */
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NO_ERROR();
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NO_ERROR();
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s++;
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s++;
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}
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}
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ASSERT (!(getreg (UART_LSR) & LSR_DR));
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ASSERT (!(getreg (UART_LSR) & LSR_DR));
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/* this should break the * char, so it should not be received */
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/* this should break the * char, so it should not be received */
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setreg (UART_LCR, LCR_BREAK);
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setreg (UART_LCR, LCR_BREAK);
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setreg (UART_THR, '*');
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setreg (UART_THR, '*');
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/* uart should hold line long enough even if we drop it immediately */
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/* uart should hold line long enough even if we drop it immediately */
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setreg (UART_LCR, 0);
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setreg (UART_LCR, 0);
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NO_ERROR();
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NO_ERROR();
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/* Receives and compares the string */
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/* Receives and compares the string */
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s = "no_star";
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s = "no_star";
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while (*s) {
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while (*s) {
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/* Wait for rx fifo to be nonempty */
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/* Wait for rx fifo to be nonempty */
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while (!(getreg (UART_LSR) & LSR_DR));
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while (!(getreg (UART_LSR) & LSR_DR));
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NO_ERROR();
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NO_ERROR();
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ASSERT (getreg (UART_RBR) == *s); /* compare character */
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ASSERT (getreg (UART_RBR) == *s); /* compare character */
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s++;
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s++;
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}
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}
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/* right now we should receive break */
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/* right now we should receive break */
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while (!(getreg (UART_LSR) & LSR_BREAK));
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while (!(getreg (UART_LSR) & LSR_BREAK));
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setreg (UART_THR, '*');
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setreg (UART_THR, '*');
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while (getreg (UART_LSR) & LSR_BREAK);
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while (getreg (UART_LSR) & LSR_BREAK);
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NO_ERROR(); /* BREAK bit should be cleared */
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NO_ERROR(); /* BREAK bit should be cleared */
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/* we should not receive incoming characters */
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/* we should not receive incoming characters */
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ASSERT (!(getreg (UART_LSR) & LSR_DR));
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ASSERT (!(getreg (UART_LSR) & LSR_DR));
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printf ("OK\n");
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printf ("OK\n");
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}
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}
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void loopback_test ()
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void loopback_test ()
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{
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{
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printf ("loopback test\n");
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printf ("loopback test\n");
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setreg (UART_MCR, 0);
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setreg (UART_MCR, 0);
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}
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}
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int main ()
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int main ()
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{
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{
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/* Use our low priority interrupt handler */
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/* Use our low priority interrupt handler */
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excpt_lpint = (unsigned long)interrupt_handler;
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excpt_lpint = (unsigned long)interrupt_handler;
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/* Enable interrupts */
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/* Enable interrupts */
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mtspr (SPR_SR, mfspr(SPR_SR) | SPR_SR_EXR);
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mtspr (SPR_SR, mfspr(SPR_SR) | SPR_SR_EXR);
|
|
|
register_test ();
|
register_test ();
|
send_recv_test ();
|
send_recv_test ();
|
break_test ();
|
break_test ();
|
/*different_modes_test ();
|
/*different_modes_test ();
|
loopback_send_rcv_test ();
|
loopback_send_rcv_test ();
|
interrupt_test ();
|
interrupt_test ();
|
fifo_test ();
|
fifo_test ();
|
loopback_test ();
|
loopback_test ();
|
modem_test ();
|
modem_test ();
|
line_error_test ();
|
line_error_test ();
|
speed_error_test ();
|
speed_error_test ();
|
frame_error_test ();
|
frame_error_test ();
|
modem_error_test ();*/
|
modem_error_test ();*/
|
printf ("ALL TESTS PASSED\n");
|
printf ("ALL TESTS PASSED\n");
|
return 0;
|
return 0;
|
}
|
}
|
|
|