/* dcache_model.c -- data cache simulation
|
/* dcache_model.c -- data cache simulation
|
Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
|
Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
|
|
|
This file is part of OpenRISC 1000 Architectural Simulator.
|
This file is part of OpenRISC 1000 Architectural Simulator.
|
|
|
This program is free software; you can redistribute it and/or modify
|
This program is free software; you can redistribute it and/or modify
|
it under the terms of the GNU General Public License as published by
|
it under the terms of the GNU General Public License as published by
|
the Free Software Foundation; either version 2 of the License, or
|
the Free Software Foundation; either version 2 of the License, or
|
(at your option) any later version.
|
(at your option) any later version.
|
|
|
This program is distributed in the hope that it will be useful,
|
This program is distributed in the hope that it will be useful,
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
GNU General Public License for more details.
|
GNU General Public License for more details.
|
|
|
You should have received a copy of the GNU General Public License
|
You should have received a copy of the GNU General Public License
|
along with this program; if not, write to the Free Software
|
along with this program; if not, write to the Free Software
|
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
|
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
|
|
|
/* Cache functions.
|
/* Cache functions.
|
At the moment this functions only simulate functionality of data
|
At the moment this functions only simulate functionality of data
|
caches and do not influence on fetche/decode/execute stages and timings.
|
caches and do not influence on fetche/decode/execute stages and timings.
|
They are here only to verify performance of various cache configurations.
|
They are here only to verify performance of various cache configurations.
|
*/
|
*/
|
|
|
#include <stdio.h>
|
#include <stdio.h>
|
#include <string.h>
|
#include <string.h>
|
#include <errno.h>
|
#include <errno.h>
|
#include <stdarg.h>
|
#include <stdarg.h>
|
|
|
#include "dcache_model.h"
|
#include "dcache_model.h"
|
#include "abstract.h"
|
#include "abstract.h"
|
#include "stats.h"
|
#include "stats.h"
|
|
|
/* Data cache */
|
/* Data cache */
|
|
|
/* Number of DC sets (power of 2) */
|
/* Number of DC sets (power of 2) */
|
#define DC_SETS 128
|
#define DC_SETS 512
|
|
|
/* Block size in bytes (1, 2, 4, 8, 16, 32 etc.) */
|
/* Block size in bytes (1, 2, 4, 8, 16, 32 etc.) */
|
#define DC_BLOCK_SIZE 16
|
#define DC_BLOCK_SIZE 16
|
|
|
/* Number of DC ways (1, 2, 3 etc.). */
|
/* Number of DC ways (1, 2, 3 etc.). */
|
#define DC_WAYS 1
|
#define DC_WAYS 1
|
|
|
/* Number of usage states (2, 3, 4 etc.). */
|
/* Number of usage states (2, 3, 4 etc.). */
|
#define DC_USTATES 2
|
#define DC_USTATES 2
|
|
|
struct dc_set {
|
struct dc_set {
|
struct {
|
struct {
|
unsigned long tagaddr; /* tag address */
|
unsigned long tagaddr; /* tag address */
|
int lru; /* least recently used */
|
int lru; /* least recently used */
|
} way[DC_WAYS];
|
} way[DC_WAYS];
|
} dc[DC_SETS];
|
} dc[DC_SETS];
|
|
|
void dc_info()
|
void dc_info()
|
{
|
{
|
printf("Data cache %dKB: ", DC_SETS * DC_BLOCK_SIZE * DC_WAYS / 1024);
|
printf("Data cache %dKB: ", DC_SETS * DC_BLOCK_SIZE * DC_WAYS / 1024);
|
printf("%d ways, %d sets, block size %d bytes\n", DC_WAYS, DC_SETS, DC_BLOCK_SIZE);
|
printf("%d ways, %d sets, block size %d bytes\n", DC_WAYS, DC_SETS, DC_BLOCK_SIZE);
|
}
|
}
|
|
|
/* First check if data is already in the cache and if it is:
|
/* First check if data is already in the cache and if it is:
|
- increment DC read hit stats,
|
- increment DC read hit stats,
|
- set 'lru' at this way to DC_USTATES - 1 and
|
- set 'lru' at this way to DC_USTATES - 1 and
|
decrement 'lru' of other ways unless they have reached 0,
|
decrement 'lru' of other ways unless they have reached 0,
|
and if not:
|
and if not:
|
- increment DC read miss stats
|
- increment DC read miss stats
|
- find lru way and entry and replace old tag with tag of the 'dataaddr'
|
- find lru way and entry and replace old tag with tag of the 'dataaddr'
|
- set 'lru' with DC_USTATES - 1 and decrement 'lru' of other
|
- set 'lru' with DC_USTATES - 1 and decrement 'lru' of other
|
ways unless they have reached 0
|
ways unless they have reached 0
|
*/
|
*/
|
|
|
void dc_simulate_read(unsigned long dataaddr)
|
void dc_simulate_read(unsigned long dataaddr)
|
{
|
{
|
int set, way = -1;
|
int set, way = -1;
|
int i;
|
int i;
|
unsigned long tagaddr;
|
unsigned long tagaddr;
|
|
|
/* Which set to check out? */
|
/* Which set to check out? */
|
set = (dataaddr / DC_BLOCK_SIZE) % DC_SETS;
|
set = (dataaddr / DC_BLOCK_SIZE) % DC_SETS;
|
tagaddr = (dataaddr / DC_BLOCK_SIZE) / DC_SETS;
|
tagaddr = (dataaddr / DC_BLOCK_SIZE) / DC_SETS;
|
|
|
/* Scan all ways and try to find a matching way. */
|
/* Scan all ways and try to find a matching way. */
|
for (i = 0; i < DC_WAYS; i++)
|
for (i = 0; i < DC_WAYS; i++)
|
if (dc[set].way[i].tagaddr == tagaddr)
|
if (dc[set].way[i].tagaddr == tagaddr)
|
way = i;
|
way = i;
|
|
|
/* Did we find our cached data? */
|
/* Did we find our cached data? */
|
if (way >= 0) { /* Yes, we did. */
|
if (way >= 0) { /* Yes, we did. */
|
dc_stats.readhit++;
|
dc_stats.readhit++;
|
|
|
for (i = 0; i < DC_WAYS; i++)
|
for (i = 0; i < DC_WAYS; i++)
|
if (dc[set].way[i].lru)
|
if (dc[set].way[i].lru)
|
dc[set].way[i].lru--;
|
dc[set].way[i].lru--;
|
dc[set].way[way].lru = DC_USTATES - 1;
|
dc[set].way[way].lru = DC_USTATES - 1;
|
}
|
}
|
else { /* No, we didn't. */
|
else { /* No, we didn't. */
|
int minlru = DC_USTATES - 1;
|
int minlru = DC_USTATES - 1;
|
int minway = 0;
|
int minway = 0;
|
|
|
dc_stats.readmiss++;
|
dc_stats.readmiss++;
|
|
|
for (i = 0; i < DC_WAYS; i++)
|
for (i = 0; i < DC_WAYS; i++)
|
if (dc[set].way[i].lru < minlru)
|
if (dc[set].way[i].lru < minlru)
|
minway = i;
|
minway = i;
|
|
|
dc[set].way[minway].tagaddr = tagaddr;
|
dc[set].way[minway].tagaddr = tagaddr;
|
for (i = 0; i < DC_WAYS; i++)
|
for (i = 0; i < DC_WAYS; i++)
|
if (dc[set].way[i].lru)
|
if (dc[set].way[i].lru)
|
dc[set].way[i].lru--;
|
dc[set].way[i].lru--;
|
dc[set].way[minway].lru = DC_USTATES - 1;
|
dc[set].way[minway].lru = DC_USTATES - 1;
|
}
|
}
|
}
|
}
|
|
|
/* First check if data is already in the cache and if it is:
|
/* First check if data is already in the cache and if it is:
|
- increment DC write hit stats,
|
- increment DC write hit stats,
|
- set 'lru' at this way to DC_USTATES - 1 and
|
- set 'lru' at this way to DC_USTATES - 1 and
|
decrement 'lru' of other ways unless they have reached 0,
|
decrement 'lru' of other ways unless they have reached 0,
|
and if not:
|
and if not:
|
- increment DC write miss stats
|
- increment DC write miss stats
|
- find lru way and entry and replace old tag with tag of the 'dataaddr'
|
- find lru way and entry and replace old tag with tag of the 'dataaddr'
|
- set 'lru' with DC_USTATES - 1 and decrement 'lru' of other
|
- set 'lru' with DC_USTATES - 1 and decrement 'lru' of other
|
ways unless they have reached 0
|
ways unless they have reached 0
|
*/
|
*/
|
|
|
void dc_simulate_write(unsigned long dataaddr)
|
void dc_simulate_write(unsigned long dataaddr)
|
{
|
{
|
int set, way = -1;
|
int set, way = -1;
|
int i;
|
int i;
|
unsigned long tagaddr;
|
unsigned long tagaddr;
|
|
|
/* Which set to check out? */
|
/* Which set to check out? */
|
set = (dataaddr / DC_BLOCK_SIZE) % DC_SETS;
|
set = (dataaddr / DC_BLOCK_SIZE) % DC_SETS;
|
tagaddr = (dataaddr / DC_BLOCK_SIZE) / DC_SETS;
|
tagaddr = (dataaddr / DC_BLOCK_SIZE) / DC_SETS;
|
|
|
/* Scan all ways and try to find a matching way. */
|
/* Scan all ways and try to find a matching way. */
|
for (i = 0; i < DC_WAYS; i++)
|
for (i = 0; i < DC_WAYS; i++)
|
if (dc[set].way[i].tagaddr == tagaddr)
|
if (dc[set].way[i].tagaddr == tagaddr)
|
way = i;
|
way = i;
|
|
|
/* Did we find our cached data? */
|
/* Did we find our cached data? */
|
if (way >= 0) { /* Yes, we did. */
|
if (way >= 0) { /* Yes, we did. */
|
dc_stats.writehit++;
|
dc_stats.writehit++;
|
|
|
for (i = 0; i < DC_WAYS; i++)
|
for (i = 0; i < DC_WAYS; i++)
|
if (dc[set].way[i].lru)
|
if (dc[set].way[i].lru)
|
dc[set].way[i].lru--;
|
dc[set].way[i].lru--;
|
dc[set].way[way].lru = DC_USTATES - 1;
|
dc[set].way[way].lru = DC_USTATES - 1;
|
}
|
}
|
else { /* No, we didn't. */
|
else { /* No, we didn't. */
|
int minlru = DC_USTATES - 1;
|
int minlru = DC_USTATES - 1;
|
int minway = 0;
|
int minway = 0;
|
|
|
dc_stats.writemiss++;
|
dc_stats.writemiss++;
|
|
|
for (i = 0; i < DC_WAYS; i++)
|
for (i = 0; i < DC_WAYS; i++)
|
if (dc[set].way[i].lru < minlru)
|
if (dc[set].way[i].lru < minlru)
|
minway = i;
|
minway = i;
|
|
|
dc[set].way[minway].tagaddr = tagaddr;
|
dc[set].way[minway].tagaddr = tagaddr;
|
for (i = 0; i < DC_WAYS; i++)
|
for (i = 0; i < DC_WAYS; i++)
|
if (dc[set].way[i].lru)
|
if (dc[set].way[i].lru)
|
dc[set].way[i].lru--;
|
dc[set].way[i].lru--;
|
dc[set].way[minway].lru = DC_USTATES - 1;
|
dc[set].way[minway].lru = DC_USTATES - 1;
|
}
|
}
|
}
|
}
|
|
|
