/* dmmu.c -- Data MMU simulation
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/* dmmu.c -- Data MMU simulation
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* DMMU model (not functional yet, currently just copy of data cache). */
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/* DMMU model (not functional yet, currently just copy of data cache). */
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#include "config.h"
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#include "config.h"
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#ifdef HAVE_INTTYPES_H
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#ifdef HAVE_INTTYPES_H
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#include <inttypes.h>
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#include <inttypes.h>
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#endif
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#endif
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#include "port.h"
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#include "port.h"
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#include "arch.h"
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#include "arch.h"
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#include "dmmu.h"
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#include "dmmu.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "opcode/or32.h"
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#include "opcode/or32.h"
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#include "stats.h"
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#include "stats.h"
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#include "sprs.h"
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#include "sprs.h"
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#include "except.h"
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#include "except.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "debug.h"
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#include "debug.h"
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DEFAULT_DEBUG_CHANNEL(dmmu);
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extern int cont_run;
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extern int cont_run;
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/* Data MMU */
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/* Data MMU */
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inline oraddr_t dmmu_simulate_tlb(oraddr_t virtaddr, int write_access)
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inline oraddr_t dmmu_simulate_tlb(oraddr_t virtaddr, int write_access)
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{
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{
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int set, way = -1;
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int set, way = -1;
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int i;
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int i;
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oraddr_t tagaddr;
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oraddr_t tagaddr;
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oraddr_t vpn, ppn;
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oraddr_t vpn, ppn;
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if (!(mfspr(SPR_SR) & SPR_SR_DME) || !testsprbits(SPR_UPR, SPR_UPR_DMP)) {
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if (!(mfspr(SPR_SR) & SPR_SR_DME) || !testsprbits(SPR_UPR, SPR_UPR_DMP)) {
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data_ci = (virtaddr >= 0x80000000);
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data_ci = (virtaddr >= 0x80000000);
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return virtaddr;
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return virtaddr;
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}
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}
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/* Which set to check out? */
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/* Which set to check out? */
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set = (virtaddr / config.dmmu.pagesize) % config.dmmu.nsets;
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set = (virtaddr / config.dmmu.pagesize) % config.dmmu.nsets;
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tagaddr = (virtaddr / config.dmmu.pagesize) / config.dmmu.nsets;
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tagaddr = (virtaddr / config.dmmu.pagesize) / config.dmmu.nsets;
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vpn = virtaddr / (config.dmmu.pagesize * config.dmmu.nsets);
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vpn = virtaddr / (config.dmmu.pagesize * config.dmmu.nsets);
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/* Scan all ways and try to find a matching way. */
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/* Scan all ways and try to find a matching way. */
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for (i = 0; i < config.dmmu.nways; i++)
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for (i = 0; i < config.dmmu.nways; i++)
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if (((mfspr(SPR_DTLBMR_BASE(i) + set) / (config.dmmu.pagesize * config.dmmu.nsets)) == vpn) &&
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if (((mfspr(SPR_DTLBMR_BASE(i) + set) / (config.dmmu.pagesize * config.dmmu.nsets)) == vpn) &&
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testsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_V))
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testsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_V))
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way = i;
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way = i;
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/* Did we find our tlb entry? */
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/* Did we find our tlb entry? */
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if (way >= 0) { /* Yes, we did. */
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if (way >= 0) { /* Yes, we did. */
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dmmu_stats.loads_tlbhit++;
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dmmu_stats.loads_tlbhit++;
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debug(5, "DTLB hit (virtaddr=%"PRIxADDR").\n", virtaddr);
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TRACE("DTLB hit (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,
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runtime.sim.cycles);
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/* Test for page fault */
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/* Test for page fault */
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if (mfspr (SPR_SR) & SPR_SR_SM) {
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if (mfspr (SPR_SR) & SPR_SR_SM) {
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if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SWE)
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if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SWE)
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|| !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SRE))
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|| !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SRE))
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except_handle(EXCEPT_DPF, virtaddr);
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except_handle(EXCEPT_DPF, virtaddr);
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} else {
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} else {
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if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_UWE)
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if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_UWE)
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|| !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_URE))
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|| !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_URE))
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except_handle(EXCEPT_DPF, virtaddr);
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except_handle(EXCEPT_DPF, virtaddr);
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}
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}
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/* Set LRUs */
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/* Set LRUs */
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for (i = 0; i < config.dmmu.nways; i++)
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for (i = 0; i < config.dmmu.nways; i++)
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if (testsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU))
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if (testsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU))
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setsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU, getsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU) - 1);
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setsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU, getsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU) - 1);
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setsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBMR_LRU, config.dmmu.nsets - 1);
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setsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBMR_LRU, config.dmmu.nsets - 1);
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/* Check if page is cache inhibited */
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/* Check if page is cache inhibited */
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data_ci = (mfspr(SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_CI) == SPR_DTLBTR_CI;
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data_ci = (mfspr(SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_CI) == SPR_DTLBTR_CI;
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runtime.sim.mem_cycles += config.dmmu.hitdelay;
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runtime.sim.mem_cycles += config.dmmu.hitdelay;
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ppn = mfspr(SPR_DTLBTR_BASE(way) + set) / config.dmmu.pagesize;
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ppn = mfspr(SPR_DTLBTR_BASE(way) + set) / config.dmmu.pagesize;
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return (ppn * config.dmmu.pagesize) + (virtaddr % config.dmmu.pagesize);
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return (ppn * config.dmmu.pagesize) + (virtaddr % config.dmmu.pagesize);
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}
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}
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else { /* No, we didn't. */
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else { /* No, we didn't. */
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dmmu_stats.loads_tlbmiss++;
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dmmu_stats.loads_tlbmiss++;
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#if 0
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#if 0
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for (i = 0; i < config.dmmu.nways; i++)
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for (i = 0; i < config.dmmu.nways; i++)
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if (getsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU) < minlru)
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if (getsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU) < minlru)
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minway = i;
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minway = i;
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setsprbits(SPR_DTLBMR_BASE(minway) + set, SPR_DTLBMR_VPN, vpn);
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setsprbits(SPR_DTLBMR_BASE(minway) + set, SPR_DTLBMR_VPN, vpn);
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for (i = 0; i < config.dmmu.nways; i++)
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for (i = 0; i < config.dmmu.nways; i++)
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if (getsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU))
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if (getsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU))
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setsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU, getsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU) - 1);
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setsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU, getsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU) - 1);
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setsprbits(SPR_DTLBMR_BASE(minway) + set, SPR_DTLBMR_LRU, config.dmmu.ustates - 1);
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setsprbits(SPR_DTLBMR_BASE(minway) + set, SPR_DTLBMR_LRU, config.dmmu.ustates - 1);
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setsprbits(SPR_DTLBTR_BASE(minway) + set, SPR_DTLBTR_PPN, vpn); /* 1 to 1 */
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setsprbits(SPR_DTLBTR_BASE(minway) + set, SPR_DTLBTR_PPN, vpn); /* 1 to 1 */
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setsprbits(SPR_DTLBMR_BASE(minway) + set, SPR_DTLBMR_V, 1);
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setsprbits(SPR_DTLBMR_BASE(minway) + set, SPR_DTLBMR_V, 1);
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#endif
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#endif
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except_handle(EXCEPT_DTLBMISS, virtaddr);
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except_handle(EXCEPT_DTLBMISS, virtaddr);
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TRACE("DTLB miss (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,
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runtime.sim.cycles);
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/* if tlb refill implemented in HW */
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/* if tlb refill implemented in HW */
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/* return getsprbits(SPR_DTLBTR_BASE(minway) + set, SPR_DTLBTR_PPN) * config.dmmu.pagesize + (virtaddr % config.dmmu.pagesize); */
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/* return getsprbits(SPR_DTLBTR_BASE(minway) + set, SPR_DTLBTR_PPN) * config.dmmu.pagesize + (virtaddr % config.dmmu.pagesize); */
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runtime.sim.mem_cycles += config.dmmu.missdelay;
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runtime.sim.mem_cycles += config.dmmu.missdelay;
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return 0;
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return 0;
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}
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}
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}
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}
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/* DESC: try to find EA -> PA transaltion without changing
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/* DESC: try to find EA -> PA transaltion without changing
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* any of precessor states. if this is not passible gives up
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* any of precessor states. if this is not passible gives up
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* (without triggering exceptions)
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* (without triggering exceptions)
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*
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*
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* PRMS: virtaddr - EA for which to find translation
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* PRMS: virtaddr - EA for which to find translation
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*
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*
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* write_access - 0 ignore testing for write access
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* write_access - 0 ignore testing for write access
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* 1 test for write access, if fails
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* 1 test for write access, if fails
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* do not return translation
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* do not return translation
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*
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*
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* through_dc - 1 go through data cache
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* through_dc - 1 go through data cache
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* 0 ignore data cache
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* 0 ignore data cache
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*
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*
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* RTRN: 0 - no DMMU, DMMU disabled or ITLB miss
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* RTRN: 0 - no DMMU, DMMU disabled or ITLB miss
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* else - appropriate PA (note it DMMU is not present
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* else - appropriate PA (note it DMMU is not present
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* PA === EA)
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* PA === EA)
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*/
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*/
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oraddr_t peek_into_dtlb(oraddr_t virtaddr, int write_access, int through_dc)
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oraddr_t peek_into_dtlb(oraddr_t virtaddr, int write_access, int through_dc)
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{
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{
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int set, way = -1;
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int set, way = -1;
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int i;
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int i;
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oraddr_t tagaddr;
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oraddr_t tagaddr;
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oraddr_t vpn, ppn;
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oraddr_t vpn, ppn;
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if (!(mfspr(SPR_SR) & SPR_SR_DME) || !testsprbits(SPR_UPR, SPR_UPR_DMP)) {
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if (!(mfspr(SPR_SR) & SPR_SR_DME) || !testsprbits(SPR_UPR, SPR_UPR_DMP)) {
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if (through_dc)
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if (through_dc)
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data_ci = (virtaddr >= 0x80000000);
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data_ci = (virtaddr >= 0x80000000);
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return virtaddr;
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return virtaddr;
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}
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}
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/* Which set to check out? */
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/* Which set to check out? */
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set = (virtaddr / config.dmmu.pagesize) % config.dmmu.nsets;
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set = (virtaddr / config.dmmu.pagesize) % config.dmmu.nsets;
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tagaddr = (virtaddr / config.dmmu.pagesize) / config.dmmu.nsets;
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tagaddr = (virtaddr / config.dmmu.pagesize) / config.dmmu.nsets;
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vpn = virtaddr / (config.dmmu.pagesize * config.dmmu.nsets);
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vpn = virtaddr / (config.dmmu.pagesize * config.dmmu.nsets);
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/* Scan all ways and try to find a matching way. */
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/* Scan all ways and try to find a matching way. */
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for (i = 0; i < config.dmmu.nways; i++)
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for (i = 0; i < config.dmmu.nways; i++)
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if (((mfspr(SPR_DTLBMR_BASE(i) + set) / (config.dmmu.pagesize * config.dmmu.nsets)) == vpn) &&
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if (((mfspr(SPR_DTLBMR_BASE(i) + set) / (config.dmmu.pagesize * config.dmmu.nsets)) == vpn) &&
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testsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_V))
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testsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_V))
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way = i;
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way = i;
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/* Did we find our tlb entry? */
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/* Did we find our tlb entry? */
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if (way >= 0) { /* Yes, we did. */
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if (way >= 0) { /* Yes, we did. */
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dmmu_stats.loads_tlbhit++;
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dmmu_stats.loads_tlbhit++;
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debug(5, "DTLB hit (virtaddr=%"PRIxADDR").\n", virtaddr);
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TRACE("DTLB hit (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,
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runtime.sim.cycles);
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/* Test for page fault */
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/* Test for page fault */
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if (mfspr (SPR_SR) & SPR_SR_SM) {
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if (mfspr (SPR_SR) & SPR_SR_SM) {
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if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SWE)
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if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SWE)
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|| !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SRE))
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|| !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SRE))
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/* otherwise exception DPF would be raised */
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/* otherwise exception DPF would be raised */
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return(0);
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return(0);
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} else {
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} else {
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if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_UWE)
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if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_UWE)
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|| !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_URE))
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|| !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_URE))
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/* otherwise exception DPF would be raised */
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/* otherwise exception DPF would be raised */
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return(0);
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return(0);
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}
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}
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if (through_dc) {
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if (through_dc) {
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/* Check if page is cache inhibited */
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/* Check if page is cache inhibited */
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data_ci = (mfspr(SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_CI) == SPR_DTLBTR_CI;
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data_ci = (mfspr(SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_CI) == SPR_DTLBTR_CI;
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}
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}
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ppn = mfspr(SPR_DTLBTR_BASE(way) + set) / config.dmmu.pagesize;
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ppn = mfspr(SPR_DTLBTR_BASE(way) + set) / config.dmmu.pagesize;
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return (ppn * config.dmmu.pagesize) + (virtaddr % config.dmmu.pagesize);
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return (ppn * config.dmmu.pagesize) + (virtaddr % config.dmmu.pagesize);
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}
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}
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else { /* No, we didn't. */
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else { /* No, we didn't. */
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return(0);
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return(0);
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}
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}
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PRINTF("ERR, should never have happened\n");
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ERR("ERR, should never have happened\n");
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return(0);
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return(0);
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}
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}
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oraddr_t dmmu_translate(oraddr_t virtaddr, int write_access)
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oraddr_t dmmu_translate(oraddr_t virtaddr, int write_access)
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{
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{
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oraddr_t phyaddr = dmmu_simulate_tlb(virtaddr, write_access);
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oraddr_t phyaddr = dmmu_simulate_tlb(virtaddr, write_access);
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/* PRINTF("DMMU translate(%"PRIxADDR") = %"PRIxADDR"\n", virtaddr, phyaddr);*/
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/* PRINTF("DMMU translate(%"PRIxADDR") = %"PRIxADDR"\n", virtaddr, phyaddr);*/
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return phyaddr;
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return phyaddr;
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}
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}
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void dtlb_info()
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void dtlb_info()
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{
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{
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if (!testsprbits(SPR_UPR, SPR_UPR_DMP)) {
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if (!testsprbits(SPR_UPR, SPR_UPR_DMP)) {
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PRINTF("DMMU not implemented. Set UPR[DMP].\n");
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PRINTF("DMMU not implemented. Set UPR[DMP].\n");
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return;
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return;
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}
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}
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PRINTF("Data MMU %dKB: ", config.dmmu.nsets * config.dmmu.entrysize * config.dmmu.nways / 1024);
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PRINTF("Data MMU %dKB: ", config.dmmu.nsets * config.dmmu.entrysize * config.dmmu.nways / 1024);
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PRINTF("%d ways, %d sets, entry size %d bytes\n", config.dmmu.nways, config.dmmu.nsets, config.dmmu.entrysize);
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PRINTF("%d ways, %d sets, entry size %d bytes\n", config.dmmu.nways, config.dmmu.nsets, config.dmmu.entrysize);
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}
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}
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/* First check if virtual address is covered by DTLB and if it is:
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/* First check if virtual address is covered by DTLB and if it is:
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- increment DTLB read hit stats,
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- increment DTLB read hit stats,
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- set 'lru' at this way to config.dmmu.ustates - 1 and
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- set 'lru' at this way to config.dmmu.ustates - 1 and
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decrement 'lru' of other ways unless they have reached 0,
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decrement 'lru' of other ways unless they have reached 0,
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- check page access attributes and invoke DMMU page fault exception
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- check page access attributes and invoke DMMU page fault exception
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handler if necessary
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handler if necessary
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and if not:
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and if not:
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- increment DTLB read miss stats
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- increment DTLB read miss stats
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- find lru way and entry and invoke DTLB miss exception handler
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- find lru way and entry and invoke DTLB miss exception handler
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- set 'lru' with config.dmmu.ustates - 1 and decrement 'lru' of other
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- set 'lru' with config.dmmu.ustates - 1 and decrement 'lru' of other
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ways unless they have reached 0
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ways unless they have reached 0
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*/
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*/
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void dtlb_status(int start_set)
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void dtlb_status(int start_set)
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{
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{
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int set;
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int set;
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int way;
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int way;
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int end_set = config.dmmu.nsets;
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int end_set = config.dmmu.nsets;
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if (!testsprbits(SPR_UPR, SPR_UPR_DMP)) {
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if (!testsprbits(SPR_UPR, SPR_UPR_DMP)) {
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PRINTF("DMMU not implemented. Set UPR[DMP].\n");
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PRINTF("DMMU not implemented. Set UPR[DMP].\n");
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return;
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return;
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}
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}
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if ((start_set >= 0) && (start_set < end_set))
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if ((start_set >= 0) && (start_set < end_set))
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end_set = start_set + 1;
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end_set = start_set + 1;
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else
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else
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start_set = 0;
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start_set = 0;
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if (start_set < end_set) PRINTF("\nDMMU: ");
|
if (start_set < end_set) PRINTF("\nDMMU: ");
|
/* Scan set(s) and way(s). */
|
/* Scan set(s) and way(s). */
|
for (set = start_set; set < end_set; set++) {
|
for (set = start_set; set < end_set; set++) {
|
PRINTF("\nSet %x: ", set);
|
PRINTF("\nSet %x: ", set);
|
for (way = 0; way < config.dmmu.nways; way++) {
|
for (way = 0; way < config.dmmu.nways; way++) {
|
PRINTF(" way %d: ", way);
|
PRINTF(" way %d: ", way);
|
PRINTF("vpn=%lx ", getsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBMR_VPN));
|
PRINTF("vpn=%lx ", getsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBMR_VPN));
|
PRINTF("lru=%lx ", getsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBMR_LRU));
|
PRINTF("lru=%lx ", getsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBMR_LRU));
|
PRINTF("pl1=%lx ", getsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBMR_PL1));
|
PRINTF("pl1=%lx ", getsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBMR_PL1));
|
PRINTF("v=%lx ", getsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBMR_V));
|
PRINTF("v=%lx ", getsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBMR_V));
|
|
|
PRINTF("a=%lx ", getsprbits(SPR_DTLBTR_BASE(way) + set, SPR_DTLBTR_A));
|
PRINTF("a=%lx ", getsprbits(SPR_DTLBTR_BASE(way) + set, SPR_DTLBTR_A));
|
PRINTF("d=%lx ", getsprbits(SPR_DTLBTR_BASE(way) + set, SPR_DTLBTR_D));
|
PRINTF("d=%lx ", getsprbits(SPR_DTLBTR_BASE(way) + set, SPR_DTLBTR_D));
|
PRINTF("ure=%lx ", getsprbits(SPR_DTLBTR_BASE(way) + set, SPR_DTLBTR_URE));
|
PRINTF("ure=%lx ", getsprbits(SPR_DTLBTR_BASE(way) + set, SPR_DTLBTR_URE));
|
PRINTF("uwe=%lx ", getsprbits(SPR_DTLBTR_BASE(way) + set, SPR_DTLBTR_UWE));
|
PRINTF("uwe=%lx ", getsprbits(SPR_DTLBTR_BASE(way) + set, SPR_DTLBTR_UWE));
|
PRINTF("sre=%lx ", getsprbits(SPR_DTLBTR_BASE(way) + set, SPR_DTLBTR_SRE));
|
PRINTF("sre=%lx ", getsprbits(SPR_DTLBTR_BASE(way) + set, SPR_DTLBTR_SRE));
|
PRINTF("swe=%lx ", getsprbits(SPR_DTLBTR_BASE(way) + set, SPR_DTLBTR_SWE));
|
PRINTF("swe=%lx ", getsprbits(SPR_DTLBTR_BASE(way) + set, SPR_DTLBTR_SWE));
|
PRINTF("ppn=%lx ", getsprbits(SPR_DTLBTR_BASE(way) + set, SPR_DTLBTR_PPN));
|
PRINTF("ppn=%lx ", getsprbits(SPR_DTLBTR_BASE(way) + set, SPR_DTLBTR_PPN));
|
}
|
}
|
}
|
}
|
if (start_set < end_set) PRINTF("\n");
|
if (start_set < end_set) PRINTF("\n");
|
}
|
}
|
|
|
/*---------------------------------------------------[ DMMU configuration ]---*/
|
/*---------------------------------------------------[ DMMU configuration ]---*/
|
void dmmu_enabled(union param_val val, void *dat)
|
void dmmu_enabled(union param_val val, void *dat)
|
{
|
{
|
setsprbits (SPR_UPR, SPR_UPR_DMP, val.int_val ? 1 : 0);
|
setsprbits (SPR_UPR, SPR_UPR_DMP, val.int_val ? 1 : 0);
|
config.dmmu.enabled = val.int_val;
|
config.dmmu.enabled = val.int_val;
|
}
|
}
|
|
|
void dmmu_nsets(union param_val val, void *dat)
|
void dmmu_nsets(union param_val val, void *dat)
|
{
|
{
|
if (is_power2(val.int_val) && val.int_val <= 256) {
|
if (is_power2(val.int_val) && val.int_val <= 256) {
|
config.dmmu.nsets = val.int_val;
|
config.dmmu.nsets = val.int_val;
|
setsprbits (SPR_DMMUCFGR, SPR_DMMUCFGR_NTS, log2(val.int_val));
|
setsprbits (SPR_DMMUCFGR, SPR_DMMUCFGR_NTS, log2(val.int_val));
|
}
|
}
|
else
|
else
|
CONFIG_ERROR("value of power of two and lower or equal than 256 expected.");
|
CONFIG_ERROR("value of power of two and lower or equal than 256 expected.");
|
}
|
}
|
|
|
void dmmu_nways(union param_val val, void *dat)
|
void dmmu_nways(union param_val val, void *dat)
|
{
|
{
|
if (val.int_val >= 1 && val.int_val <= 4) {
|
if (val.int_val >= 1 && val.int_val <= 4) {
|
config.dmmu.nways = val.int_val;
|
config.dmmu.nways = val.int_val;
|
setsprbits (SPR_DMMUCFGR, SPR_DMMUCFGR_NTW, val.int_val-1);
|
setsprbits (SPR_DMMUCFGR, SPR_DMMUCFGR_NTW, val.int_val-1);
|
}
|
}
|
else
|
else
|
CONFIG_ERROR("value 1, 2, 3 or 4 expected.");
|
CONFIG_ERROR("value 1, 2, 3 or 4 expected.");
|
}
|
}
|
|
|
void dmmu_pagesize(union param_val val, void *dat)
|
void dmmu_pagesize(union param_val val, void *dat)
|
{
|
{
|
if (is_power2(val.int_val))
|
if (is_power2(val.int_val))
|
config.dmmu.pagesize = val.int_val;
|
config.dmmu.pagesize = val.int_val;
|
else
|
else
|
CONFIG_ERROR("value of power of two expected.");
|
CONFIG_ERROR("value of power of two expected.");
|
}
|
}
|
|
|
void dmmu_entrysize(union param_val val, void *dat)
|
void dmmu_entrysize(union param_val val, void *dat)
|
{
|
{
|
if (is_power2(val.int_val))
|
if (is_power2(val.int_val))
|
config.dmmu.entrysize = val.int_val;
|
config.dmmu.entrysize = val.int_val;
|
else
|
else
|
CONFIG_ERROR("value of power of two expected.");
|
CONFIG_ERROR("value of power of two expected.");
|
}
|
}
|
|
|
void dmmu_ustates(union param_val val, void *dat)
|
void dmmu_ustates(union param_val val, void *dat)
|
{
|
{
|
if (val.int_val >= 2 && val.int_val <= 4)
|
if (val.int_val >= 2 && val.int_val <= 4)
|
config.dmmu.ustates = val.int_val;
|
config.dmmu.ustates = val.int_val;
|
else
|
else
|
CONFIG_ERROR("invalid USTATE.");
|
CONFIG_ERROR("invalid USTATE.");
|
}
|
}
|
|
|
void dmmu_missdelay(union param_val val, void *dat)
|
void dmmu_missdelay(union param_val val, void *dat)
|
{
|
{
|
config.dmmu.missdelay = val.int_val;
|
config.dmmu.missdelay = val.int_val;
|
}
|
}
|
|
|
void dmmu_hitdelay(union param_val val, void *dat)
|
void dmmu_hitdelay(union param_val val, void *dat)
|
{
|
{
|
config.immu.hitdelay = val.int_val;
|
config.immu.hitdelay = val.int_val;
|
}
|
}
|
|
|
void reg_dmmu_sec(void)
|
void reg_dmmu_sec(void)
|
{
|
{
|
struct config_section *sec = reg_config_sec("dmmu", NULL, NULL);
|
struct config_section *sec = reg_config_sec("dmmu", NULL, NULL);
|
|
|
reg_config_param(sec, "enabled", paramt_int, dmmu_enabled);
|
reg_config_param(sec, "enabled", paramt_int, dmmu_enabled);
|
reg_config_param(sec, "nsets", paramt_int, dmmu_nsets);
|
reg_config_param(sec, "nsets", paramt_int, dmmu_nsets);
|
reg_config_param(sec, "nways", paramt_int, dmmu_nways);
|
reg_config_param(sec, "nways", paramt_int, dmmu_nways);
|
reg_config_param(sec, "pagesize", paramt_int, dmmu_pagesize);
|
reg_config_param(sec, "pagesize", paramt_int, dmmu_pagesize);
|
reg_config_param(sec, "entrysize", paramt_int, dmmu_entrysize);
|
reg_config_param(sec, "entrysize", paramt_int, dmmu_entrysize);
|
reg_config_param(sec, "ustates", paramt_int, dmmu_ustates);
|
reg_config_param(sec, "ustates", paramt_int, dmmu_ustates);
|
reg_config_param(sec, "missdelay", paramt_int, dmmu_missdelay);
|
reg_config_param(sec, "missdelay", paramt_int, dmmu_missdelay);
|
reg_config_param(sec, "hitdelay", paramt_int, dmmu_hitdelay);
|
reg_config_param(sec, "hitdelay", paramt_int, dmmu_hitdelay);
|
}
|
}
|
|
|
