/* immu.c -- Instruction MMU simulation
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/* immu.c -- Instruction MMU simulation
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* IMMU model (not functional yet, currently just copy of data cache). */
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/* IMMU model (not functional yet, currently just copy of data cache). */
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#include "config.h"
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#include "config.h"
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#ifdef HAVE_INTTYPES_H
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#ifdef HAVE_INTTYPES_H
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#include <inttypes.h>
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#include <inttypes.h>
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#endif
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#endif
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#include "port.h"
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#include "port.h"
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#include "arch.h"
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#include "arch.h"
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#include "immu.h"
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#include "immu.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "opcode/or32.h"
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#include "opcode/or32.h"
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#include "spr_defs.h"
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#include "spr_defs.h"
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#include "execute.h"
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#include "execute.h"
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#include "stats.h"
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#include "stats.h"
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#include "sprs.h"
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#include "sprs.h"
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#include "except.h"
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#include "except.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "debug.h"
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#include "debug.h"
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DEFAULT_DEBUG_CHANNEL(immu);
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DEFAULT_DEBUG_CHANNEL(immu);
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extern int cont_run;
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extern int cont_run;
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/* Insn MMU */
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/* Insn MMU */
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static inline oraddr_t immu_simulate_tlb(oraddr_t virtaddr)
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static inline oraddr_t immu_simulate_tlb(oraddr_t virtaddr)
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{
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{
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int set, way = -1;
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int set, way = -1;
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int i;
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int i;
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oraddr_t tagaddr;
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oraddr_t tagaddr;
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oraddr_t vpn, ppn;
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oraddr_t vpn, ppn;
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if (!(mfspr(SPR_SR) & SPR_SR_IME) || !(testsprbits(SPR_UPR, SPR_UPR_IMP))) {
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if (!(mfspr(SPR_SR) & SPR_SR_IME) || !(testsprbits(SPR_UPR, SPR_UPR_IMP))) {
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insn_ci = (virtaddr >= 0x80000000);
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insn_ci = (virtaddr >= 0x80000000);
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return virtaddr;
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return virtaddr;
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}
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}
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TRACE("IMMU enabled, checking mmu ways\n");
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TRACE("IMMU enabled, checking mmu ways\n");
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/* Which set to check out? */
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/* Which set to check out? */
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set = (virtaddr / config.immu.pagesize) % config.immu.nsets;
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set = (virtaddr / config.immu.pagesize) % config.immu.nsets;
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tagaddr = (virtaddr / config.immu.pagesize) / config.immu.nsets;
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tagaddr = (virtaddr / config.immu.pagesize) / config.immu.nsets;
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vpn = virtaddr / (config.immu.pagesize * config.immu.nsets);
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vpn = virtaddr / (config.immu.pagesize * config.immu.nsets);
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/* Scan all ways and try to find a matching way. */
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/* Scan all ways and try to find a matching way. */
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for (i = 0; i < config.immu.nways; i++)
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for (i = 0; i < config.immu.nways; i++)
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if (((mfspr(SPR_ITLBMR_BASE(i) + set) / (config.immu.pagesize * config.immu.nsets)) == vpn) &&
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if (((mfspr(SPR_ITLBMR_BASE(i) + set) / (config.immu.pagesize * config.immu.nsets)) == vpn) &&
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testsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_V))
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testsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_V))
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way = i;
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way = i;
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/* Did we find our tlb entry? */
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/* Did we find our tlb entry? */
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if (way >= 0) { /* Yes, we did. */
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if (way >= 0) { /* Yes, we did. */
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immu_stats.fetch_tlbhit++;
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immu_stats.fetch_tlbhit++;
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TRACE("ITLB hit (virtaddr=%"PRIxADDR").\n", virtaddr);
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TRACE("ITLB hit (virtaddr=%"PRIxADDR").\n", virtaddr);
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/* Set LRUs */
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/* Set LRUs */
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for (i = 0; i < config.immu.nways; i++)
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for (i = 0; i < config.immu.nways; i++)
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if (testsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU))
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if (testsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU))
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setsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU, getsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU) - 1);
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setsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU, getsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU) - 1);
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setsprbits(SPR_ITLBMR_BASE(way) + set, SPR_ITLBMR_LRU, config.immu.nsets - 1);
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setsprbits(SPR_ITLBMR_BASE(way) + set, SPR_ITLBMR_LRU, config.immu.nsets - 1);
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/* Check if page is cache inhibited */
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/* Check if page is cache inhibited */
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insn_ci = (mfspr(SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_CI) == SPR_ITLBTR_CI;
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insn_ci = (mfspr(SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_CI) == SPR_ITLBTR_CI;
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runtime.sim.mem_cycles += config.immu.hitdelay;
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runtime.sim.mem_cycles += config.immu.hitdelay;
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/* Test for page fault */
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/* Test for page fault */
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if (mfspr (SPR_SR) & SPR_SR_SM) {
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if (mfspr (SPR_SR) & SPR_SR_SM) {
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if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_SXE))
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if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_SXE))
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except_handle(EXCEPT_IPF, virtaddr);
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except_handle(EXCEPT_IPF, virtaddr);
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} else {
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} else {
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if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_UXE))
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if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_UXE))
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except_handle(EXCEPT_IPF, virtaddr);
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except_handle(EXCEPT_IPF, virtaddr);
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}
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}
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ppn = mfspr(SPR_ITLBTR_BASE(way) + set) / config.immu.pagesize;
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ppn = mfspr(SPR_ITLBTR_BASE(way) + set) / config.immu.pagesize;
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return (ppn * config.immu.pagesize) + (virtaddr % config.immu.pagesize);
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return (ppn * config.immu.pagesize) + (virtaddr % config.immu.pagesize);
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}
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}
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else { /* No, we didn't. */
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else { /* No, we didn't. */
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immu_stats.fetch_tlbmiss++;
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immu_stats.fetch_tlbmiss++;
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#if 0
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#if 0
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for (i = 0; i < config.immu.nways; i++)
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for (i = 0; i < config.immu.nways; i++)
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if (getsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU) < minlru)
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if (getsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU) < minlru)
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minway = i;
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minway = i;
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setsprbits(SPR_ITLBMR_BASE(minway) + set, SPR_ITLBMR_VPN, vpn);
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setsprbits(SPR_ITLBMR_BASE(minway) + set, SPR_ITLBMR_VPN, vpn);
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for (i = 0; i < config.immu.nways; i++)
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for (i = 0; i < config.immu.nways; i++)
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if (testsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU))
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if (testsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU))
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setsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU, getsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU) - 1);
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setsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU, getsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU) - 1);
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setsprbits(SPR_ITLBMR_BASE(minway) + set, SPR_ITLBMR_LRU, config.immu.ustates - 1);
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setsprbits(SPR_ITLBMR_BASE(minway) + set, SPR_ITLBMR_LRU, config.immu.ustates - 1);
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setsprbits(SPR_ITLBTR_BASE(minway) + set, SPR_ITLBTR_PPN, vpn); /* 1 to 1 */
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setsprbits(SPR_ITLBTR_BASE(minway) + set, SPR_ITLBTR_PPN, vpn); /* 1 to 1 */
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setsprbits(SPR_ITLBMR_BASE(minway) + set, SPR_ITLBMR_V, 1);
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setsprbits(SPR_ITLBMR_BASE(minway) + set, SPR_ITLBMR_V, 1);
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#endif
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#endif
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/* if tlb refill implemented in HW */
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/* if tlb refill implemented in HW */
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/* return getsprbits(SPR_ITLBTR_BASE(minway) + set, SPR_ITLBTR_PPN) * config.immu.pagesize + (virtaddr % config.immu.pagesize); */
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/* return getsprbits(SPR_ITLBTR_BASE(minway) + set, SPR_ITLBTR_PPN) * config.immu.pagesize + (virtaddr % config.immu.pagesize); */
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runtime.sim.mem_cycles += config.immu.missdelay;
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runtime.sim.mem_cycles += config.immu.missdelay;
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except_handle(EXCEPT_ITLBMISS, virtaddr);
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except_handle(EXCEPT_ITLBMISS, virtaddr);
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return 0;
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return 0;
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}
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}
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}
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}
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/* DESC: try to find EA -> PA transaltion without changing
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/* DESC: try to find EA -> PA transaltion without changing
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* any of precessor states. if this is not passible gives up
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* any of precessor states. if this is not passible gives up
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* (without triggering exceptions).
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* (without triggering exceptions).
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*
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*
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* PRMS: virtaddr - EA for which to find translation
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* PRMS: virtaddr - EA for which to find translation
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*
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*
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* RTRN: 0 - no IMMU, IMMU disabled or ITLB miss
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* RTRN: 0 - no IMMU, IMMU disabled or ITLB miss
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* else - appropriate PA (note it IMMU is not present
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* else - appropriate PA (note it IMMU is not present
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* PA === EA)
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* PA === EA)
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*/
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*/
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oraddr_t peek_into_itlb(oraddr_t virtaddr)
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oraddr_t peek_into_itlb(oraddr_t virtaddr)
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{
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{
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int set, way = -1;
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int set, way = -1;
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int i;
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int i;
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oraddr_t tagaddr;
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oraddr_t tagaddr;
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oraddr_t vpn, ppn;
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oraddr_t vpn, ppn;
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if (!(mfspr(SPR_SR) & SPR_SR_IME) || !(testsprbits(SPR_UPR, SPR_UPR_IMP))) {
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if (!(mfspr(SPR_SR) & SPR_SR_IME) || !(testsprbits(SPR_UPR, SPR_UPR_IMP))) {
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return(virtaddr);
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return(virtaddr);
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}
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}
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/* Which set to check out? */
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/* Which set to check out? */
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set = (virtaddr / config.immu.pagesize) % config.immu.nsets;
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set = (virtaddr / config.immu.pagesize) % config.immu.nsets;
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tagaddr = (virtaddr / config.immu.pagesize) / config.immu.nsets;
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tagaddr = (virtaddr / config.immu.pagesize) / config.immu.nsets;
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vpn = virtaddr / (config.immu.pagesize * config.immu.nsets);
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vpn = virtaddr / (config.immu.pagesize * config.immu.nsets);
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/* Scan all ways and try to find a matching way. */
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/* Scan all ways and try to find a matching way. */
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for (i = 0; i < config.immu.nways; i++)
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for (i = 0; i < config.immu.nways; i++)
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if (((mfspr(SPR_ITLBMR_BASE(i) + set) / (config.immu.pagesize * config.immu.nsets)) == vpn) &&
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if (((mfspr(SPR_ITLBMR_BASE(i) + set) / (config.immu.pagesize * config.immu.nsets)) == vpn) &&
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testsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_V))
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testsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_V))
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way = i;
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way = i;
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/* Did we find our tlb entry? */
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/* Did we find our tlb entry? */
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if (way >= 0) { /* Yes, we did. */
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if (way >= 0) { /* Yes, we did. */
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/* Test for page fault */
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/* Test for page fault */
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if (mfspr (SPR_SR) & SPR_SR_SM) {
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if (mfspr (SPR_SR) & SPR_SR_SM) {
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if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_SXE)) {
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if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_SXE)) {
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/* no luck, giving up */
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/* no luck, giving up */
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return(0);
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return(0);
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}
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}
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} else {
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} else {
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if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_UXE)) {
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if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_UXE)) {
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/* no luck, giving up */
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/* no luck, giving up */
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return(0);
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return(0);
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}
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}
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}
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}
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ppn = mfspr(SPR_ITLBTR_BASE(way) + set) / config.immu.pagesize;
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ppn = mfspr(SPR_ITLBTR_BASE(way) + set) / config.immu.pagesize;
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return (ppn * config.immu.pagesize) + (virtaddr % config.immu.pagesize);
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return (ppn * config.immu.pagesize) + (virtaddr % config.immu.pagesize);
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}
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}
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else {
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else {
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return(0);
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return(0);
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}
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}
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ERR("should never have happened\n");
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ERR("should never have happened\n");
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return(0);
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return(0);
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}
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}
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oraddr_t immu_translate(oraddr_t virtaddr)
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oraddr_t immu_translate(oraddr_t virtaddr)
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{
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{
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oraddr_t phyaddr = immu_simulate_tlb(virtaddr);
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oraddr_t phyaddr = immu_simulate_tlb(virtaddr);
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/* PRINTF("IMMU translate(%x) = %x\n", virtaddr, phyaddr);*/
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/* PRINTF("IMMU translate(%x) = %x\n", virtaddr, phyaddr);*/
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return phyaddr;
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return phyaddr;
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}
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}
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void itlb_info()
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void itlb_info()
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{
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{
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if (!testsprbits(SPR_UPR, SPR_UPR_IMP)) {
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if (!testsprbits(SPR_UPR, SPR_UPR_IMP)) {
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PRINTF("IMMU not implemented. Set UPR[IMP].\n");
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PRINTF("IMMU not implemented. Set UPR[IMP].\n");
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return;
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return;
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}
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}
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PRINTF("Insn MMU %dKB: ", config.immu.nsets * config.immu.entrysize * config.immu.nways / 1024);
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PRINTF("Insn MMU %dKB: ", config.immu.nsets * config.immu.entrysize * config.immu.nways / 1024);
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PRINTF("%d ways, %d sets, entry size %d bytes\n", config.immu.nways, config.immu.nsets, config.immu.entrysize);
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PRINTF("%d ways, %d sets, entry size %d bytes\n", config.immu.nways, config.immu.nsets, config.immu.entrysize);
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}
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}
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/* First check if virtual address is covered by ITLB and if it is:
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/* First check if virtual address is covered by ITLB and if it is:
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- increment ITLB read hit stats,
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- increment ITLB read hit stats,
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- set 'lru' at this way to config.immu.ustates - 1 and
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- set 'lru' at this way to config.immu.ustates - 1 and
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decrement 'lru' of other ways unless they have reached 0,
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decrement 'lru' of other ways unless they have reached 0,
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- check page access attributes and invoke IMMU page fault exception
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- check page access attributes and invoke IMMU page fault exception
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handler if necessary
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handler if necessary
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and if not:
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and if not:
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- increment ITLB read miss stats
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- increment ITLB read miss stats
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- find lru way and entry and invoke ITLB miss exception handler
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- find lru way and entry and invoke ITLB miss exception handler
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- set 'lru' with config.immu.ustates - 1 and decrement 'lru' of other
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- set 'lru' with config.immu.ustates - 1 and decrement 'lru' of other
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ways unless they have reached 0
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ways unless they have reached 0
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*/
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*/
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void itlb_status(int start_set)
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void itlb_status(int start_set)
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{
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{
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int set;
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int set;
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int way;
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int way;
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int end_set = config.immu.nsets;
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int end_set = config.immu.nsets;
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if (!testsprbits(SPR_UPR, SPR_UPR_IMP)) {
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if (!testsprbits(SPR_UPR, SPR_UPR_IMP)) {
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PRINTF("IMMU not implemented. Set UPR[IMP].\n");
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PRINTF("IMMU not implemented. Set UPR[IMP].\n");
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return;
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return;
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}
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}
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if ((start_set >= 0) && (start_set < end_set))
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if ((start_set >= 0) && (start_set < end_set))
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end_set = start_set + 1;
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end_set = start_set + 1;
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else
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else
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start_set = 0;
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start_set = 0;
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if (start_set < end_set) PRINTF("\nIMMU: ");
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if (start_set < end_set) PRINTF("\nIMMU: ");
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/* Scan set(s) and way(s). */
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/* Scan set(s) and way(s). */
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for (set = start_set; set < end_set; set++) {
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for (set = start_set; set < end_set; set++) {
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PRINTF("\nSet %x: ", set);
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PRINTF("\nSet %x: ", set);
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for (way = 0; way < config.immu.nways; way++) {
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for (way = 0; way < config.immu.nways; way++) {
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PRINTF(" way %d: ", way);
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PRINTF(" way %d: ", way);
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PRINTF("vpn=%lx ", getsprbits(SPR_ITLBMR_BASE(way) + set, SPR_ITLBMR_VPN));
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PRINTF("vpn=%lx ", getsprbits(SPR_ITLBMR_BASE(way) + set, SPR_ITLBMR_VPN));
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PRINTF("lru=%lx ", getsprbits(SPR_ITLBMR_BASE(way) + set, SPR_ITLBMR_LRU));
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PRINTF("lru=%lx ", getsprbits(SPR_ITLBMR_BASE(way) + set, SPR_ITLBMR_LRU));
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PRINTF("pl1=%lx ", getsprbits(SPR_ITLBMR_BASE(way) + set, SPR_ITLBMR_PL1));
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PRINTF("pl1=%lx ", getsprbits(SPR_ITLBMR_BASE(way) + set, SPR_ITLBMR_PL1));
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PRINTF("v=%lx ", getsprbits(SPR_ITLBMR_BASE(way) + set, SPR_ITLBMR_V));
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PRINTF("v=%lx ", getsprbits(SPR_ITLBMR_BASE(way) + set, SPR_ITLBMR_V));
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PRINTF("a=%lx ", getsprbits(SPR_ITLBTR_BASE(way) + set, SPR_ITLBTR_A));
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PRINTF("a=%lx ", getsprbits(SPR_ITLBTR_BASE(way) + set, SPR_ITLBTR_A));
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PRINTF("d=%lx ", getsprbits(SPR_ITLBTR_BASE(way) + set, SPR_ITLBTR_D));
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PRINTF("d=%lx ", getsprbits(SPR_ITLBTR_BASE(way) + set, SPR_ITLBTR_D));
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PRINTF("uxe=%lx ", getsprbits(SPR_ITLBTR_BASE(way) + set, SPR_ITLBTR_UXE));
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PRINTF("uxe=%lx ", getsprbits(SPR_ITLBTR_BASE(way) + set, SPR_ITLBTR_UXE));
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PRINTF("sxe=%lx ", getsprbits(SPR_ITLBTR_BASE(way) + set, SPR_ITLBTR_SXE));
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PRINTF("sxe=%lx ", getsprbits(SPR_ITLBTR_BASE(way) + set, SPR_ITLBTR_SXE));
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PRINTF("ppn=%lx ", getsprbits(SPR_ITLBTR_BASE(way) + set, SPR_ITLBTR_PPN));
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PRINTF("ppn=%lx ", getsprbits(SPR_ITLBTR_BASE(way) + set, SPR_ITLBTR_PPN));
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}
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}
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}
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}
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if (start_set < end_set) PRINTF("\n");
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if (start_set < end_set) PRINTF("\n");
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}
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}
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/*---------------------------------------------------[ IMMU configuration ]---*/
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/*---------------------------------------------------[ IMMU configuration ]---*/
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void immu_enabled(union param_val val, void *dat)
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void immu_enabled(union param_val val, void *dat)
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{
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{
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setsprbits (SPR_UPR, SPR_UPR_IMP, val.int_val ? 1 : 0);
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setsprbits (SPR_UPR, SPR_UPR_IMP, val.int_val ? 1 : 0);
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config.immu.enabled = val.int_val;
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config.immu.enabled = val.int_val;
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}
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}
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|
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void immu_nsets(union param_val val, void *dat)
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void immu_nsets(union param_val val, void *dat)
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{
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{
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if (is_power2(val.int_val) && val.int_val <= 256) {
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if (is_power2(val.int_val) && val.int_val <= 256) {
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config.immu.nsets = val.int_val;
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config.immu.nsets = val.int_val;
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setsprbits (SPR_IMMUCFGR, SPR_IMMUCFGR_NTS, log2(val.int_val));
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setsprbits (SPR_IMMUCFGR, SPR_IMMUCFGR_NTS, log2(val.int_val));
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}
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}
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else
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else
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CONFIG_ERROR("value of power of two and lower or equal than 256 expected.");
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CONFIG_ERROR("value of power of two and lower or equal than 256 expected.");
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}
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}
|
|
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void immu_nways(union param_val val, void *dat)
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void immu_nways(union param_val val, void *dat)
|
{
|
{
|
if (val.int_val >= 1 && val.int_val <= 4) {
|
if (val.int_val >= 1 && val.int_val <= 4) {
|
config.immu.nways = val.int_val;
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config.immu.nways = val.int_val;
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setsprbits (SPR_DMMUCFGR, SPR_DMMUCFGR_NTW, val.int_val-1);
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setsprbits (SPR_DMMUCFGR, SPR_DMMUCFGR_NTW, val.int_val-1);
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}
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}
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else
|
else
|
CONFIG_ERROR("value 1, 2, 3 or 4 expected.");
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CONFIG_ERROR("value 1, 2, 3 or 4 expected.");
|
}
|
}
|
|
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void immu_pagesize(union param_val val, void *dat)
|
void immu_pagesize(union param_val val, void *dat)
|
{
|
{
|
if (is_power2(val.int_val))
|
if (is_power2(val.int_val))
|
config.immu.pagesize = val.int_val;
|
config.immu.pagesize = val.int_val;
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else
|
else
|
CONFIG_ERROR("value of power of two expected.");
|
CONFIG_ERROR("value of power of two expected.");
|
}
|
}
|
|
|
void immu_entrysize(union param_val val, void *dat)
|
void immu_entrysize(union param_val val, void *dat)
|
{
|
{
|
if (is_power2(val.int_val))
|
if (is_power2(val.int_val))
|
config.immu.entrysize = val.int_val;
|
config.immu.entrysize = val.int_val;
|
else
|
else
|
CONFIG_ERROR("value of power of two expected.");
|
CONFIG_ERROR("value of power of two expected.");
|
}
|
}
|
|
|
void immu_ustates(union param_val val, void *dat)
|
void immu_ustates(union param_val val, void *dat)
|
{
|
{
|
if (val.int_val >= 2 && val.int_val <= 4)
|
if (val.int_val >= 2 && val.int_val <= 4)
|
config.immu.ustates = val.int_val;
|
config.immu.ustates = val.int_val;
|
else
|
else
|
CONFIG_ERROR("invalid USTATE.");
|
CONFIG_ERROR("invalid USTATE.");
|
}
|
}
|
|
|
void immu_missdelay(union param_val val, void *dat)
|
void immu_missdelay(union param_val val, void *dat)
|
{
|
{
|
config.immu.missdelay = val.int_val;
|
config.immu.missdelay = val.int_val;
|
}
|
}
|
|
|
void immu_hitdelay(union param_val val, void *dat)
|
void immu_hitdelay(union param_val val, void *dat)
|
{
|
{
|
config.immu.hitdelay = val.int_val;
|
config.immu.hitdelay = val.int_val;
|
}
|
}
|
|
|
void reg_immu_sec(void)
|
void reg_immu_sec(void)
|
{
|
{
|
struct config_section *sec = reg_config_sec("immu", NULL, NULL);
|
struct config_section *sec = reg_config_sec("immu", NULL, NULL);
|
|
|
reg_config_param(sec, "enabled", paramt_int, immu_enabled);
|
reg_config_param(sec, "enabled", paramt_int, immu_enabled);
|
reg_config_param(sec, "nsets", paramt_int, immu_nsets);
|
reg_config_param(sec, "nsets", paramt_int, immu_nsets);
|
reg_config_param(sec, "nways", paramt_int, immu_nways);
|
reg_config_param(sec, "nways", paramt_int, immu_nways);
|
reg_config_param(sec, "pagesize", paramt_int, immu_pagesize);
|
reg_config_param(sec, "pagesize", paramt_int, immu_pagesize);
|
reg_config_param(sec, "entrysize", paramt_int, immu_entrysize);
|
reg_config_param(sec, "entrysize", paramt_int, immu_entrysize);
|
reg_config_param(sec, "ustates", paramt_int, immu_ustates);
|
reg_config_param(sec, "ustates", paramt_int, immu_ustates);
|
reg_config_param(sec, "missdelay", paramt_int, immu_missdelay);
|
reg_config_param(sec, "missdelay", paramt_int, immu_missdelay);
|
reg_config_param(sec, "hitdelay", paramt_int, immu_hitdelay);
|
reg_config_param(sec, "hitdelay", paramt_int, immu_hitdelay);
|
}
|
}
|
|
|
