/* immu.c -- Instruction MMU simulation
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/* immu.c -- Instruction MMU simulation
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* IMMU model (not functional yet, currently just copy of data cache). */
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/* IMMU model (not functional yet, currently just copy of data cache). */
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#include "immu.h"
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#include "immu.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "stats.h"
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#include "stats.h"
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#include "sprs.h"
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#include "sprs.h"
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#include "except.h"
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#include "except.h"
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#include "sim-config.h"
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#include "sim-config.h"
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extern int cont_run;
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extern int cont_run;
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/* Insn MMU */
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/* Insn MMU */
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inline unsigned long immu_simulate_tlb(unsigned long virtaddr)
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inline unsigned long immu_simulate_tlb(unsigned long virtaddr)
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{
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{
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int set, way = -1;
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int set, way = -1;
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int i;
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int i;
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unsigned long tagaddr;
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unsigned long tagaddr;
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unsigned long vpn, ppn;
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unsigned long vpn, ppn;
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extern int mem_cycles;
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extern int mem_cycles;
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if (!(mfspr(SPR_SR) & SPR_SR_IME) || !(testsprbits(SPR_UPR, SPR_UPR_IMP)))
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if (!(mfspr(SPR_SR) & SPR_SR_IME) || !(testsprbits(SPR_UPR, SPR_UPR_IMP))) {
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insn_ci = (virtaddr >= 0x80000000);
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return virtaddr;
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return virtaddr;
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}
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/* Which set to check out? */
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/* Which set to check out? */
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set = (virtaddr / config.immu.pagesize) % config.immu.nsets;
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set = (virtaddr / config.immu.pagesize) % config.immu.nsets;
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tagaddr = (virtaddr / config.immu.pagesize) / config.immu.nsets;
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tagaddr = (virtaddr / config.immu.pagesize) / config.immu.nsets;
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vpn = virtaddr / (config.immu.pagesize * config.immu.nsets);
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vpn = virtaddr / (config.immu.pagesize * config.immu.nsets);
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/* Scan all ways and try to find a matching way. */
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/* Scan all ways and try to find a matching way. */
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for (i = 0; i < config.immu.nways; i++)
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for (i = 0; i < config.immu.nways; i++)
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if (((mfspr(SPR_ITLBMR_BASE(i) + set) / (config.immu.pagesize * config.immu.nsets)) == vpn) &&
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if (((mfspr(SPR_ITLBMR_BASE(i) + set) / (config.immu.pagesize * config.immu.nsets)) == vpn) &&
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testsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_V))
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testsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_V))
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way = i;
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way = i;
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/* Did we find our tlb entry? */
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/* Did we find our tlb entry? */
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if (way >= 0) { /* Yes, we did. */
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if (way >= 0) { /* Yes, we did. */
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immu_stats.fetch_tlbhit++;
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immu_stats.fetch_tlbhit++;
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debug(5, "ITLB hit (virtaddr=%x).\n", virtaddr);
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debug(5, "ITLB hit (virtaddr=%x).\n", virtaddr);
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/* Test for page fault */
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/* Test for page fault */
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if (mfspr (SPR_SR) & SPR_SR_SM) {
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if (mfspr (SPR_SR) & SPR_SR_SM) {
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if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_SXE))
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if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_SXE))
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except_handle(EXCEPT_IPF, virtaddr);
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except_handle(EXCEPT_IPF, virtaddr);
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} else {
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} else {
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if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_UXE))
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if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_UXE))
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except_handle(EXCEPT_IPF, virtaddr);
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except_handle(EXCEPT_IPF, virtaddr);
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}
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}
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/* Set LRUs */
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/* Set LRUs */
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for (i = 0; i < config.immu.nways; i++)
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for (i = 0; i < config.immu.nways; i++)
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if (testsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU))
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if (testsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU))
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setsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU, getsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU) - 1);
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setsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU, getsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU) - 1);
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setsprbits(SPR_ITLBMR_BASE(way) + set, SPR_ITLBMR_LRU, config.immu.ustates - 1);
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setsprbits(SPR_ITLBMR_BASE(way) + set, SPR_ITLBMR_LRU, config.immu.ustates - 1);
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/* Check if page is cache inhibited */
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insn_ci = (mfspr(SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_CI) == SPR_ITLBTR_CI;
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mem_cycles += config.immu.hitdelay;
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mem_cycles += config.immu.hitdelay;
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ppn = mfspr(SPR_ITLBTR_BASE(way) + set) / config.immu.pagesize;
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ppn = mfspr(SPR_ITLBTR_BASE(way) + set) / config.immu.pagesize;
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return (ppn * config.immu.pagesize) + (virtaddr % config.immu.pagesize);
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return (ppn * config.immu.pagesize) + (virtaddr % config.immu.pagesize);
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}
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}
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else { /* No, we didn't. */
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else { /* No, we didn't. */
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int minlru = config.immu.ustates - 1;
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int minlru = config.immu.ustates - 1;
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int minway = 0;
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int minway = 0;
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immu_stats.fetch_tlbmiss++;
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immu_stats.fetch_tlbmiss++;
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#if 0
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#if 0
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for (i = 0; i < config.immu.nways; i++)
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for (i = 0; i < config.immu.nways; i++)
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if (getsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU) < minlru)
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if (getsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU) < minlru)
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minway = i;
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minway = i;
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setsprbits(SPR_ITLBMR_BASE(minway) + set, SPR_ITLBMR_VPN, vpn);
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setsprbits(SPR_ITLBMR_BASE(minway) + set, SPR_ITLBMR_VPN, vpn);
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for (i = 0; i < config.immu.nways; i++)
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for (i = 0; i < config.immu.nways; i++)
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if (testsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU))
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if (testsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU))
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setsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU, getsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU) - 1);
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setsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU, getsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU) - 1);
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setsprbits(SPR_ITLBMR_BASE(minway) + set, SPR_ITLBMR_LRU, config.immu.ustates - 1);
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setsprbits(SPR_ITLBMR_BASE(minway) + set, SPR_ITLBMR_LRU, config.immu.ustates - 1);
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setsprbits(SPR_ITLBTR_BASE(minway) + set, SPR_ITLBTR_PPN, vpn); /* 1 to 1 */
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setsprbits(SPR_ITLBTR_BASE(minway) + set, SPR_ITLBTR_PPN, vpn); /* 1 to 1 */
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setsprbits(SPR_ITLBMR_BASE(minway) + set, SPR_ITLBMR_V, 1);
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setsprbits(SPR_ITLBMR_BASE(minway) + set, SPR_ITLBMR_V, 1);
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#endif
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#endif
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except_handle(EXCEPT_ITLBMISS, virtaddr);
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except_handle(EXCEPT_ITLBMISS, virtaddr);
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/* if tlb refill implemented in HW */
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/* if tlb refill implemented in HW */
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/* return getsprbits(SPR_ITLBTR_BASE(minway) + set, SPR_ITLBTR_PPN) * config.immu.pagesize + (virtaddr % config.immu.pagesize); */
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/* return getsprbits(SPR_ITLBTR_BASE(minway) + set, SPR_ITLBTR_PPN) * config.immu.pagesize + (virtaddr % config.immu.pagesize); */
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mem_cycles += config.immu.missdelay;
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mem_cycles += config.immu.missdelay;
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return 0;
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return 0;
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}
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}
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}
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}
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unsigned long immu_translate(unsigned long virtaddr)
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unsigned long immu_translate(unsigned long virtaddr)
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{
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{
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unsigned long phyaddr = immu_simulate_tlb(virtaddr);
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unsigned long phyaddr = immu_simulate_tlb(virtaddr);
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/* printf("IMMU translate(%x) = %x\n", virtaddr, phyaddr);*/
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/* printf("IMMU translate(%x) = %x\n", virtaddr, phyaddr);*/
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return phyaddr;
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return phyaddr;
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}
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}
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void itlb_info()
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void itlb_info()
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{
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{
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if (!testsprbits(SPR_UPR, SPR_UPR_IMP)) {
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if (!testsprbits(SPR_UPR, SPR_UPR_IMP)) {
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printf("IMMU not implemented. Set UPR[IMP].\n");
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printf("IMMU not implemented. Set UPR[IMP].\n");
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return;
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return;
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}
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}
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printf("Insn MMU %dKB: ", config.immu.nsets * config.immu.entrysize * config.immu.nways / 1024);
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printf("Insn MMU %dKB: ", config.immu.nsets * config.immu.entrysize * config.immu.nways / 1024);
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printf("%d ways, %d sets, entry size %d bytes\n", config.immu.nways, config.immu.nsets, config.immu.entrysize);
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printf("%d ways, %d sets, entry size %d bytes\n", config.immu.nways, config.immu.nsets, config.immu.entrysize);
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}
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}
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/* First check if virtual address is covered by ITLB and if it is:
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/* First check if virtual address is covered by ITLB and if it is:
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- increment ITLB read hit stats,
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- increment ITLB read hit stats,
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- set 'lru' at this way to config.immu.ustates - 1 and
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- set 'lru' at this way to config.immu.ustates - 1 and
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decrement 'lru' of other ways unless they have reached 0,
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decrement 'lru' of other ways unless they have reached 0,
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- check page access attributes and invoke IMMU page fault exception
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- check page access attributes and invoke IMMU page fault exception
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handler if necessary
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handler if necessary
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and if not:
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and if not:
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- increment ITLB read miss stats
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- increment ITLB read miss stats
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- find lru way and entry and invoke ITLB miss exception handler
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- find lru way and entry and invoke ITLB miss exception handler
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- set 'lru' with config.immu.ustates - 1 and decrement 'lru' of other
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- set 'lru' with config.immu.ustates - 1 and decrement 'lru' of other
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ways unless they have reached 0
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ways unless they have reached 0
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*/
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*/
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void itlb_status(int start_set)
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void itlb_status(int start_set)
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{
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{
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int set;
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int set;
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int way;
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int way;
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int end_set = config.immu.nsets;
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int end_set = config.immu.nsets;
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if (!testsprbits(SPR_UPR, SPR_UPR_IMP)) {
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if (!testsprbits(SPR_UPR, SPR_UPR_IMP)) {
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printf("IMMU not implemented. Set UPR[IMP].\n");
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printf("IMMU not implemented. Set UPR[IMP].\n");
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return;
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return;
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}
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}
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if ((start_set >= 0) && (start_set < end_set))
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if ((start_set >= 0) && (start_set < end_set))
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end_set = start_set + 1;
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end_set = start_set + 1;
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else
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else
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start_set = 0;
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start_set = 0;
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if (start_set < end_set) printf("\nIMMU: ");
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if (start_set < end_set) printf("\nIMMU: ");
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/* Scan set(s) and way(s). */
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/* Scan set(s) and way(s). */
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for (set = start_set; set < end_set; set++) {
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for (set = start_set; set < end_set; set++) {
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printf("\nSet %x: ", set);
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printf("\nSet %x: ", set);
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for (way = 0; way < config.immu.nways; way++) {
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for (way = 0; way < config.immu.nways; way++) {
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printf(" way %d: ", way);
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printf(" way %d: ", way);
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printf("vpn=%x ", getsprbits(SPR_ITLBMR_BASE(way) + set, SPR_ITLBMR_VPN));
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printf("vpn=%x ", getsprbits(SPR_ITLBMR_BASE(way) + set, SPR_ITLBMR_VPN));
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printf("lru=%x ", getsprbits(SPR_ITLBMR_BASE(way) + set, SPR_ITLBMR_LRU));
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printf("lru=%x ", getsprbits(SPR_ITLBMR_BASE(way) + set, SPR_ITLBMR_LRU));
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printf("pl1=%x ", getsprbits(SPR_ITLBMR_BASE(way) + set, SPR_ITLBMR_PL1));
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printf("pl1=%x ", getsprbits(SPR_ITLBMR_BASE(way) + set, SPR_ITLBMR_PL1));
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printf("v=%x ", getsprbits(SPR_ITLBMR_BASE(way) + set, SPR_ITLBMR_V));
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printf("v=%x ", getsprbits(SPR_ITLBMR_BASE(way) + set, SPR_ITLBMR_V));
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printf("a=%x ", getsprbits(SPR_ITLBTR_BASE(way) + set, SPR_ITLBTR_A));
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printf("a=%x ", getsprbits(SPR_ITLBTR_BASE(way) + set, SPR_ITLBTR_A));
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printf("d=%x ", getsprbits(SPR_ITLBTR_BASE(way) + set, SPR_ITLBTR_D));
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printf("d=%x ", getsprbits(SPR_ITLBTR_BASE(way) + set, SPR_ITLBTR_D));
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printf("uxe=%x ", getsprbits(SPR_ITLBTR_BASE(way) + set, SPR_ITLBTR_UXE));
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printf("uxe=%x ", getsprbits(SPR_ITLBTR_BASE(way) + set, SPR_ITLBTR_UXE));
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printf("sxe=%x ", getsprbits(SPR_ITLBTR_BASE(way) + set, SPR_ITLBTR_SXE));
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printf("sxe=%x ", getsprbits(SPR_ITLBTR_BASE(way) + set, SPR_ITLBTR_SXE));
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printf("ppn=%x ", getsprbits(SPR_ITLBTR_BASE(way) + set, SPR_ITLBTR_PPN));
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printf("ppn=%x ", getsprbits(SPR_ITLBTR_BASE(way) + set, SPR_ITLBTR_PPN));
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}
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}
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}
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}
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if (start_set < end_set) printf("\n");
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if (start_set < end_set) printf("\n");
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}
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}
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