/* dcache_model.c -- data cache simulation
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/* dcache_model.c -- data cache simulation
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* Cache functions.
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/* Cache functions.
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At the moment this functions only simulate functionality of data
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At the moment this functions only simulate functionality of data
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caches and do not influence on fetche/decode/execute stages and timings.
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caches and do not influence on fetche/decode/execute stages and timings.
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They are here only to verify performance of various cache configurations.
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They are here only to verify performance of various cache configurations.
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*/
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*/
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#include <stdio.h>
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#include <stdio.h>
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#include <string.h>
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#include <string.h>
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#include <errno.h>
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#include <errno.h>
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#include <stdarg.h>
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#include <stdarg.h>
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#include "dcache_model.h"
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#include "dcache_model.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "stats.h"
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#include "stats.h"
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#include "spr_defs.h"
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#include "spr_defs.h"
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#include "sprs.h"
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#include "sprs.h"
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#include "sim-config.h"
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#include "sim-config.h"
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/* Data cache */
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/* Data cache */
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struct dc_set {
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struct dc_set {
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struct {
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struct {
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unsigned long line[MAX_DC_BLOCK_SIZE];
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unsigned long line[MAX_DC_BLOCK_SIZE];
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unsigned long tagaddr; /* tag address */
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unsigned long tagaddr; /* tag address */
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int lru; /* least recently used */
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int lru; /* least recently used */
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} way[MAX_DC_WAYS];
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} way[MAX_DC_WAYS];
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} dc[MAX_DC_SETS];
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} dc[MAX_DC_SETS];
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void dc_info()
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void dc_info()
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{
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{
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if (!testsprbits(SPR_UPR, SPR_UPR_DCP)) {
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if (!testsprbits(SPR_UPR, SPR_UPR_DCP)) {
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printf("DCache not implemented. Set UPR[DCP].\n");
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printf("DCache not implemented. Set UPR[DCP].\n");
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return;
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return;
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}
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}
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printf("Data cache %dKB: ", config.dc.nsets * config.dc.blocksize * config.dc.nways / 1024);
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printf("Data cache %dKB: ", config.dc.nsets * config.dc.blocksize * config.dc.nways / 1024);
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printf("%d ways, %d sets, block size %d bytes\n", config.dc.nways, config.dc.nsets, config.dc.blocksize);
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printf("%d ways, %d sets, block size %d bytes\n", config.dc.nways, config.dc.nsets, config.dc.blocksize);
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}
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}
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/* First check if data is already in the cache and if it is:
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/* First check if data is already in the cache and if it is:
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- increment DC read hit stats,
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- increment DC read hit stats,
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- set 'lru' at this way to config.dc.ustates - 1 and
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- set 'lru' at this way to config.dc.ustates - 1 and
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decrement 'lru' of other ways unless they have reached 0,
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decrement 'lru' of other ways unless they have reached 0,
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and if not:
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and if not:
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- increment DC read miss stats
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- increment DC read miss stats
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- find lru way and entry and replace old tag with tag of the 'dataaddr'
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- find lru way and entry and replace old tag with tag of the 'dataaddr'
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- set 'lru' with config.dc.ustates - 1 and decrement 'lru' of other
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- set 'lru' with config.dc.ustates - 1 and decrement 'lru' of other
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ways unless they have reached 0
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ways unless they have reached 0
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- refill cache line
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- refill cache line
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*/
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*/
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unsigned long dc_simulate_read(unsigned long dataaddr, int width)
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unsigned long dc_simulate_read(unsigned long dataaddr, int width)
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{
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{
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int set, way = -1;
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int set, way = -1;
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int i;
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int i;
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unsigned long tagaddr;
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unsigned long tagaddr;
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extern int mem_cycles;
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unsigned long tmp;
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unsigned long tmp;
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if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) ||
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if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) ||
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(!testsprbits(SPR_SR, SPR_SR_DCE)) ||
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(!testsprbits(SPR_SR, SPR_SR_DCE)) ||
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data_ci) {
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data_ci) {
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if (width == 4)
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if (width == 4)
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return evalsim_mem32(dataaddr);
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return evalsim_mem32(dataaddr);
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else if (width == 2)
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else if (width == 2)
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return (unsigned long)evalsim_mem16(dataaddr);
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return (unsigned long)evalsim_mem16(dataaddr);
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else if (width == 1)
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else if (width == 1)
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return (unsigned long)evalsim_mem8(dataaddr);
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return (unsigned long)evalsim_mem8(dataaddr);
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}
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}
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/* Which set to check out? */
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/* Which set to check out? */
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set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
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set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
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tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
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tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
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/* Scan all ways and try to find a matching way. */
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/* Scan all ways and try to find a matching way. */
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for (i = 0; i < config.dc.nways; i++)
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for (i = 0; i < config.dc.nways; i++)
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if (dc[set].way[i].tagaddr == tagaddr)
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if (dc[set].way[i].tagaddr == tagaddr)
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way = i;
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way = i;
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/* Did we find our cached data? */
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/* Did we find our cached data? */
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if (way >= 0) { /* Yes, we did. */
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if (way >= 0) { /* Yes, we did. */
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dc_stats.readhit++;
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dc_stats.readhit++;
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for (i = 0; i < config.dc.nways; i++)
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for (i = 0; i < config.dc.nways; i++)
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if (dc[set].way[i].lru > dc[set].way[way].lru)
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if (dc[set].way[i].lru > dc[set].way[way].lru)
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dc[set].way[i].lru--;
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dc[set].way[i].lru--;
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dc[set].way[way].lru = config.dc.ustates - 1;
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dc[set].way[way].lru = config.dc.ustates - 1;
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mem_cycles += config.dc.load_hitdelay;
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runtime.sim.mem_cycles += config.dc.load_hitdelay;
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tmp = dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
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tmp = dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
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if (width == 4)
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if (width == 4)
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return tmp;
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return tmp;
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else if (width == 2) {
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else if (width == 2) {
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tmp = (unsigned long)((tmp >> ((dataaddr & 2) ? 0 : 16)) & 0xffff);
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tmp = (unsigned long)((tmp >> ((dataaddr & 2) ? 0 : 16)) & 0xffff);
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return tmp;
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return tmp;
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}
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}
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else if (width == 1) {
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else if (width == 1) {
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tmp = (unsigned long)((tmp >> (8 * (3 - (dataaddr & 3)))) & 0xff);
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tmp = (unsigned long)((tmp >> (8 * (3 - (dataaddr & 3)))) & 0xff);
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return tmp;
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return tmp;
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}
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}
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} else { /* No, we didn't. */
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} else { /* No, we didn't. */
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int minlru = config.dc.ustates - 1;
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int minlru = config.dc.ustates - 1;
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int minway = 0;
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int minway = 0;
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dc_stats.readmiss++;
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dc_stats.readmiss++;
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for (i = 0; i < config.dc.nways; i++)
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for (i = 0; i < config.dc.nways; i++)
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if (dc[set].way[i].lru < minlru)
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if (dc[set].way[i].lru < minlru)
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minway = i;
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minway = i;
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for (i = 0; i < (config.dc.blocksize); i += 4) {
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for (i = 0; i < (config.dc.blocksize); i += 4) {
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dc[set].way[minway].line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] =
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dc[set].way[minway].line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] =
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evalsim_mem32((dataaddr & ~(config.dc.blocksize - 1)) + (((dataaddr & ~3ul)+ i) & (config.dc.blocksize - 1)));
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evalsim_mem32((dataaddr & ~(config.dc.blocksize - 1)) + (((dataaddr & ~3ul)+ i) & (config.dc.blocksize - 1)));
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if(!cur_area) {
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if(!cur_area) {
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dc[set].way[minway].tagaddr = -1;
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dc[set].way[minway].tagaddr = -1;
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dc[set].way[minway].lru = 0;
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dc[set].way[minway].lru = 0;
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return 0;
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return 0;
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}
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}
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}
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}
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dc[set].way[minway].tagaddr = tagaddr;
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dc[set].way[minway].tagaddr = tagaddr;
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for (i = 0; i < config.dc.nways; i++)
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for (i = 0; i < config.dc.nways; i++)
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if (dc[set].way[i].lru)
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if (dc[set].way[i].lru)
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dc[set].way[i].lru--;
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dc[set].way[i].lru--;
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dc[set].way[minway].lru = config.dc.ustates - 1;
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dc[set].way[minway].lru = config.dc.ustates - 1;
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mem_cycles += config.dc.load_missdelay;
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runtime.sim.mem_cycles += config.dc.load_missdelay;
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tmp = dc[set].way[minway].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
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tmp = dc[set].way[minway].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
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if (width == 4)
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if (width == 4)
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return tmp;
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return tmp;
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else if (width == 2) {
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else if (width == 2) {
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tmp = (unsigned long)((tmp >> ((dataaddr & 2) ? 0 : 16)) & 0xffff);
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tmp = (unsigned long)((tmp >> ((dataaddr & 2) ? 0 : 16)) & 0xffff);
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return tmp;
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return tmp;
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}
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}
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else if (width == 1) {
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else if (width == 1) {
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tmp = (unsigned long)((tmp >> (8 * (3 - (dataaddr & 3)))) & 0xff);
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tmp = (unsigned long)((tmp >> (8 * (3 - (dataaddr & 3)))) & 0xff);
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return tmp;
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return tmp;
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}
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}
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}
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}
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}
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}
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/* First check if data is already in the cache and if it is:
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/* First check if data is already in the cache and if it is:
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- increment DC write hit stats,
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- increment DC write hit stats,
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- set 'lru' at this way to config.dc.ustates - 1 and
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- set 'lru' at this way to config.dc.ustates - 1 and
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decrement 'lru' of other ways unless they have reached 0,
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decrement 'lru' of other ways unless they have reached 0,
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and if not:
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and if not:
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- increment DC write miss stats
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- increment DC write miss stats
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- find lru way and entry and replace old tag with tag of the 'dataaddr'
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- find lru way and entry and replace old tag with tag of the 'dataaddr'
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- set 'lru' with config.dc.ustates - 1 and decrement 'lru' of other
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- set 'lru' with config.dc.ustates - 1 and decrement 'lru' of other
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ways unless they have reached 0
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ways unless they have reached 0
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*/
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*/
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void dc_simulate_write(unsigned long dataaddr, unsigned long data, int width)
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void dc_simulate_write(unsigned long dataaddr, unsigned long data, int width)
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{
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{
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int set, way = -1;
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int set, way = -1;
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int i;
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int i;
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unsigned long tagaddr;
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unsigned long tagaddr;
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extern int mem_cycles;
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unsigned long tmp;
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unsigned long tmp;
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if (width == 4)
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if (width == 4)
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setsim_mem32(dataaddr, data);
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setsim_mem32(dataaddr, data);
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else if (width == 2)
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else if (width == 2)
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setsim_mem16(dataaddr, (unsigned short)data);
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setsim_mem16(dataaddr, (unsigned short)data);
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else if (width == 1)
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else if (width == 1)
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setsim_mem8(dataaddr, (unsigned char)data);
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setsim_mem8(dataaddr, (unsigned char)data);
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if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) ||
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if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) ||
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(!testsprbits(SPR_SR, SPR_SR_DCE)) ||
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(!testsprbits(SPR_SR, SPR_SR_DCE)) ||
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data_ci ||
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data_ci ||
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(!cur_area))
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(!cur_area))
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return;
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return;
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/* Which set to check out? */
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/* Which set to check out? */
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set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
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set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
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tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
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tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
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/* Scan all ways and try to find a matching way. */
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/* Scan all ways and try to find a matching way. */
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for (i = 0; i < config.dc.nways; i++)
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for (i = 0; i < config.dc.nways; i++)
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if (dc[set].way[i].tagaddr == tagaddr)
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if (dc[set].way[i].tagaddr == tagaddr)
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way = i;
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way = i;
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/* Did we find our cached data? */
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/* Did we find our cached data? */
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if (way >= 0) { /* Yes, we did. */
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if (way >= 0) { /* Yes, we did. */
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dc_stats.writehit++;
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dc_stats.writehit++;
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for (i = 0; i < config.dc.nways; i++)
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for (i = 0; i < config.dc.nways; i++)
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if (dc[set].way[i].lru > dc[set].way[way].lru)
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if (dc[set].way[i].lru > dc[set].way[way].lru)
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dc[set].way[i].lru--;
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dc[set].way[i].lru--;
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dc[set].way[way].lru = config.dc.ustates - 1;
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dc[set].way[way].lru = config.dc.ustates - 1;
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mem_cycles += config.dc.store_hitdelay;
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runtime.sim.mem_cycles += config.dc.store_hitdelay;
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tmp = dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
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tmp = dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
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if (width == 4)
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if (width == 4)
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tmp = data;
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tmp = data;
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else if (width == 2) {
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else if (width == 2) {
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tmp &= 0xffff << ((dataaddr & 2) ? 16 : 0);
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tmp &= 0xffff << ((dataaddr & 2) ? 16 : 0);
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tmp |= (unsigned long)(data & 0xffff) << ((dataaddr & 2) ? 0 : 16);
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tmp |= (unsigned long)(data & 0xffff) << ((dataaddr & 2) ? 0 : 16);
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}
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}
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else if (width == 1) {
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else if (width == 1) {
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tmp &= ~(0xff << (8 * (3 - (dataaddr & 3))));
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tmp &= ~(0xff << (8 * (3 - (dataaddr & 3))));
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tmp |= (unsigned long)(data & 0xff) << (8 * (3 - (dataaddr & 3)));
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tmp |= (unsigned long)(data & 0xff) << (8 * (3 - (dataaddr & 3)));
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}
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}
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dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2] = tmp;
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dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2] = tmp;
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}
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}
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else { /* No, we didn't. */
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else { /* No, we didn't. */
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int minlru = config.dc.ustates - 1;
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int minlru = config.dc.ustates - 1;
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int minway = 0;
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int minway = 0;
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dc_stats.writemiss++;
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dc_stats.writemiss++;
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for (i = 0; i < config.dc.nways; i++)
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for (i = 0; i < config.dc.nways; i++)
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if (dc[set].way[i].lru < minlru)
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if (dc[set].way[i].lru < minlru)
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minway = i;
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minway = i;
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for (i = 0; i < (config.dc.blocksize); i += 4) {
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for (i = 0; i < (config.dc.blocksize); i += 4) {
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dc[set].way[minway].line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] =
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dc[set].way[minway].line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] =
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evalsim_mem32((dataaddr & ~(config.dc.blocksize - 1)) + (((dataaddr & ~3ul)+ i) & (config.dc.blocksize - 1)));
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evalsim_mem32((dataaddr & ~(config.dc.blocksize - 1)) + (((dataaddr & ~3ul)+ i) & (config.dc.blocksize - 1)));
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if(!cur_area) {
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if(!cur_area) {
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dc[set].way[minway].tagaddr = -1;
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dc[set].way[minway].tagaddr = -1;
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dc[set].way[minway].lru = 0;
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dc[set].way[minway].lru = 0;
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return;
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return;
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}
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}
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}
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}
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|
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dc[set].way[minway].tagaddr = tagaddr;
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dc[set].way[minway].tagaddr = tagaddr;
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for (i = 0; i < config.dc.nways; i++)
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for (i = 0; i < config.dc.nways; i++)
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if (dc[set].way[i].lru)
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if (dc[set].way[i].lru)
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dc[set].way[i].lru--;
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dc[set].way[i].lru--;
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dc[set].way[minway].lru = config.dc.ustates - 1;
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dc[set].way[minway].lru = config.dc.ustates - 1;
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mem_cycles += config.dc.store_missdelay;
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runtime.sim.mem_cycles += config.dc.store_missdelay;
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}
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}
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}
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}
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|
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/* First check if data is already in the cache and if it is:
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/* First check if data is already in the cache and if it is:
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- invalidate block if way isn't locked
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- invalidate block if way isn't locked
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otherwise don't do anything.
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otherwise don't do anything.
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*/
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*/
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|
|
void dc_inv(unsigned long dataaddr)
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void dc_inv(unsigned long dataaddr)
|
{
|
{
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int set, way = -1;
|
int set, way = -1;
|
int i;
|
int i;
|
unsigned long tagaddr;
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unsigned long tagaddr;
|
|
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if (!testsprbits(SPR_UPR, SPR_UPR_DCP))
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if (!testsprbits(SPR_UPR, SPR_UPR_DCP))
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return;
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return;
|
|
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/* Which set to check out? */
|
/* Which set to check out? */
|
set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
|
set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
|
tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
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tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
|
|
|
if (!testsprbits(SPR_SR, SPR_SR_DCE)) {
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if (!testsprbits(SPR_SR, SPR_SR_DCE)) {
|
for (i = 0; i < config.dc.nways; i++) {
|
for (i = 0; i < config.dc.nways; i++) {
|
dc[set].way[i].tagaddr = -1;
|
dc[set].way[i].tagaddr = -1;
|
dc[set].way[i].lru = 0;
|
dc[set].way[i].lru = 0;
|
}
|
}
|
return;
|
return;
|
}
|
}
|
/* Scan all ways and try to find a matching way. */
|
/* Scan all ways and try to find a matching way. */
|
for (i = 0; i < config.dc.nways; i++)
|
for (i = 0; i < config.dc.nways; i++)
|
if (dc[set].way[i].tagaddr == tagaddr)
|
if (dc[set].way[i].tagaddr == tagaddr)
|
way = i;
|
way = i;
|
|
|
/* Did we find our cached data? */
|
/* Did we find our cached data? */
|
if (way >= 0) { /* Yes, we did. */
|
if (way >= 0) { /* Yes, we did. */
|
dc[set].way[way].tagaddr = -1;
|
dc[set].way[way].tagaddr = -1;
|
dc[set].way[way].lru = 0;
|
dc[set].way[way].lru = 0;
|
}
|
}
|
}
|
}
|
|
|
inline void dc_clock()
|
inline void dc_clock()
|
{
|
{
|
unsigned long addr;
|
unsigned long addr;
|
|
|
if (addr = mfspr(SPR_DCBPR)) {
|
if (addr = mfspr(SPR_DCBPR)) {
|
dc_simulate_read(addr, 4);
|
dc_simulate_read(addr, 4);
|
mtspr(SPR_DCBPR, 0);
|
mtspr(SPR_DCBPR, 0);
|
}
|
}
|
if ((addr = mfspr(SPR_DCBFR)) != -1) {
|
if ((addr = mfspr(SPR_DCBFR)) != -1) {
|
dc_inv(addr);
|
dc_inv(addr);
|
mtspr(SPR_DCBFR, -1);
|
mtspr(SPR_DCBFR, -1);
|
}
|
}
|
if (addr = mfspr(SPR_DCBIR)) {
|
if (addr = mfspr(SPR_DCBIR)) {
|
dc_inv(addr);
|
dc_inv(addr);
|
mtspr(SPR_DCBIR, 0);
|
mtspr(SPR_DCBIR, 0);
|
}
|
}
|
if (addr = mfspr(SPR_DCBWR)) {
|
if (addr = mfspr(SPR_DCBWR)) {
|
mtspr(SPR_DCBWR, 0);
|
mtspr(SPR_DCBWR, 0);
|
}
|
}
|
if (addr = mfspr(SPR_DCBLR)) {
|
if (addr = mfspr(SPR_DCBLR)) {
|
mtspr(SPR_DCBLR, 0);
|
mtspr(SPR_DCBLR, 0);
|
}
|
}
|
}
|
}
|
|
|
