/* 16450.c -- Simulation of 8250/16450 serial UART
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/* 16450.c -- Simulation of 8250/16450 serial UART
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* This is functional simulation of 8250/16450 UARTs. Since we RX/TX data
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/* This is functional simulation of 8250/16450 UARTs. Since we RX/TX data
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via file streams, we can't simulate modem control lines coming from the
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via file streams, we can't simulate modem control lines coming from the
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DCE and similar details of communication with the DCE.
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DCE and similar details of communication with the DCE.
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This simulated UART device is intended for basic UART device driver
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This simulated UART device is intended for basic UART device driver
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verification. From device driver perspective this device looks like a
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verification. From device driver perspective this device looks like a
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regular UART but never reports and modem control lines changes (the
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regular UART but never reports and modem control lines changes (the
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only DCE responses are incoming characters from the file stream).
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only DCE responses are incoming characters from the file stream).
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*/
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*/
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#include <stdlib.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdio.h>
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#include <string.h>
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#include <string.h>
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#include "abstract.h"
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#include "abstract.h"
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#include "16450.h"
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#include "16450.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "pic.h"
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#include "pic.h"
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#include "vapi.h"
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#include "vapi.h"
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#include "sched.h"
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#include "sched.h"
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#include "channel.h"
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#define MIN(a,b) ((a) < (b) ? (a) : (b))
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#define MIN(a,b) ((a) < (b) ? (a) : (b))
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static struct dev_16450 uarts[MAX_UARTS];
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static struct dev_16450 uarts[MAX_UARTS]; /* simulation info */
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static struct channel * channels[MAX_UARTS] = { NULL, }; /* emulation info */
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static int thre_int;
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static int thre_int;
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/* Number of clock cycles (one clock cycle is one call to the uart_clock())
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/* Number of clock cycles (one clock cycle is one call to the uart_clock())
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before a single character is transmitted or received. */
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before a single character is transmitted or received. */
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static unsigned long char_clks(int dll, int dlh, int lcr)
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static unsigned long char_clks(int dll, int dlh, int lcr)
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{
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{
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float bauds_per_char = 1.;
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float bauds_per_char = 1.;
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unsigned long char_clks = ((dlh << 8) + dll);
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unsigned long char_clks = ((dlh << 8) + dll);
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if (lcr & UART_LCR_PARITY)
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if (lcr & UART_LCR_PARITY)
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bauds_per_char = bauds_per_char + 1.;
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bauds_per_char = bauds_per_char + 1.;
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/* stop bits 1 or two */
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/* stop bits 1 or two */
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if (lcr & UART_LCR_STOP)
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if (lcr & UART_LCR_STOP)
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bauds_per_char = bauds_per_char + 2.;
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bauds_per_char = bauds_per_char + 2.;
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else
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else
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if ((lcr & 0x3) != 0)
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if ((lcr & 0x3) != 0)
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bauds_per_char = bauds_per_char + 1.;
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bauds_per_char = bauds_per_char + 1.;
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else
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else
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bauds_per_char = bauds_per_char + 1.5;
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bauds_per_char = bauds_per_char + 1.5;
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bauds_per_char = bauds_per_char + (5. + (lcr & 0x3));
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bauds_per_char = bauds_per_char + (5. + (lcr & 0x3));
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return char_clks * bauds_per_char;
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return char_clks * bauds_per_char;
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}
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}
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/* Set a specific UART register with value. */
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/* Set a specific UART register with value. */
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void uart_write_byte(unsigned long addr, unsigned long value)
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void uart_write_byte(unsigned long addr, unsigned long value)
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{
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{
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int chipsel;
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int chipsel;
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debug(4, "uart_write_byte(%x,%02x)\n", addr, (unsigned)value);
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debug(4, "uart_write_byte(%x,%02x)\n", addr, (unsigned)value);
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for(chipsel = 0; chipsel < MAX_UARTS; chipsel++)
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for(chipsel = 0; chipsel < MAX_UARTS; chipsel++)
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if ((addr & ~(UART_ADDR_SPACE-1)) == config.uarts[chipsel].baseaddr)
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if ((addr & ~(UART_ADDR_SPACE-1)) == config.uarts[chipsel].baseaddr)
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break;
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break;
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if (chipsel >= MAX_UARTS) return;
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if (chipsel >= MAX_UARTS) return;
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if (uarts[chipsel].regs.lcr & UART_LCR_DLAB) {
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if (uarts[chipsel].regs.lcr & UART_LCR_DLAB) {
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switch (addr % UART_ADDR_SPACE) {
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switch (addr % UART_ADDR_SPACE) {
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case UART_DLL:
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case UART_DLL:
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uarts[chipsel].regs.dll = value;
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uarts[chipsel].regs.dll = value;
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uarts[chipsel].char_clks = char_clks(uarts[chipsel].regs.dll, uarts[chipsel].regs.dlh, uarts[chipsel].regs.lcr);
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uarts[chipsel].char_clks = char_clks(uarts[chipsel].regs.dll, uarts[chipsel].regs.dlh, uarts[chipsel].regs.lcr);
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return;
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return;
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case UART_DLH:
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case UART_DLH:
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uarts[chipsel].regs.dlh = value;
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uarts[chipsel].regs.dlh = value;
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return;
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return;
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}
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}
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}
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}
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switch (addr % UART_ADDR_SPACE) {
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switch (addr % UART_ADDR_SPACE) {
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case UART_TXBUF:
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case UART_TXBUF:
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if (uarts[chipsel].istat.txbuf_full < uarts[chipsel].fifo_len) {
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if (uarts[chipsel].istat.txbuf_full < uarts[chipsel].fifo_len) {
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uarts[chipsel].istat.txbuf_full++;
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uarts[chipsel].istat.txbuf_full++;
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uarts[chipsel].regs.txbuf[uarts[chipsel].istat.txbuf_head] = value;
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uarts[chipsel].regs.txbuf[uarts[chipsel].istat.txbuf_head] = value;
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uarts[chipsel].istat.txbuf_head = (uarts[chipsel].istat.txbuf_head + 1) % uarts[chipsel].fifo_len;
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uarts[chipsel].istat.txbuf_head = (uarts[chipsel].istat.txbuf_head + 1) % uarts[chipsel].fifo_len;
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} else
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} else
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uarts[chipsel].regs.txbuf[uarts[chipsel].istat.txbuf_head] = value;
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uarts[chipsel].regs.txbuf[uarts[chipsel].istat.txbuf_head] = value;
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uarts[chipsel].regs.lsr &= ~(UART_LSR_TXSERE | UART_LSR_TXBUFE);
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uarts[chipsel].regs.lsr &= ~(UART_LSR_TXSERE | UART_LSR_TXBUFE);
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uarts[chipsel].istat.thre_int = 0;
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uarts[chipsel].istat.thre_int = 0;
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break;
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break;
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case UART_FCR:
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case UART_FCR:
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uarts[chipsel].regs.fcr = value & UART_VALID_FCR;
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uarts[chipsel].regs.fcr = value & UART_VALID_FCR;
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if (uarts[chipsel].fifo_len == 1 && (value & UART_FCR_FIE)
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if (uarts[chipsel].fifo_len == 1 && (value & UART_FCR_FIE)
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|| uarts[chipsel].fifo_len != 1 && !(value & UART_FCR_FIE))
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|| uarts[chipsel].fifo_len != 1 && !(value & UART_FCR_FIE))
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value |= UART_FCR_RRXFI | UART_FCR_RTXFI;
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value |= UART_FCR_RRXFI | UART_FCR_RTXFI;
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uarts[chipsel].fifo_len = (value & UART_FCR_FIE) ? 16 : 1;
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uarts[chipsel].fifo_len = (value & UART_FCR_FIE) ? 16 : 1;
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if (value & UART_FCR_RTXFI) {
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if (value & UART_FCR_RTXFI) {
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uarts[chipsel].istat.txbuf_head = uarts[chipsel].istat.txbuf_tail = 0;
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uarts[chipsel].istat.txbuf_head = uarts[chipsel].istat.txbuf_tail = 0;
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uarts[chipsel].istat.txbuf_full = 0;
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uarts[chipsel].istat.txbuf_full = 0;
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uarts[chipsel].regs.lsr &= ~UART_LSR_TXBUFE;
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uarts[chipsel].regs.lsr &= ~UART_LSR_TXBUFE;
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}
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}
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if (value & UART_FCR_RRXFI) {
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if (value & UART_FCR_RRXFI) {
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uarts[chipsel].istat.rxbuf_head = uarts[chipsel].istat.rxbuf_tail = 0;
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uarts[chipsel].istat.rxbuf_head = uarts[chipsel].istat.rxbuf_tail = 0;
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uarts[chipsel].istat.rxbuf_full = 0;
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uarts[chipsel].istat.rxbuf_full = 0;
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uarts[chipsel].regs.lsr &= ~UART_LSR_RDRDY;
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uarts[chipsel].regs.lsr &= ~UART_LSR_RDRDY;
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}
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}
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break;
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break;
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case UART_IER:
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case UART_IER:
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uarts[chipsel].regs.ier = value & UART_VALID_IER;
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uarts[chipsel].regs.ier = value & UART_VALID_IER;
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#if 0
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#if 0
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if (uarts[chipsel].regs.ier & UART_IER_THRI)
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if (uarts[chipsel].regs.ier & UART_IER_THRI)
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uarts[chipsel].istat.thre_int = 1;
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uarts[chipsel].istat.thre_int = 1;
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#endif
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#endif
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break;
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break;
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case UART_LCR:
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case UART_LCR:
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uarts[chipsel].regs.lcr = value & UART_VALID_LCR;
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uarts[chipsel].regs.lcr = value & UART_VALID_LCR;
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uarts[chipsel].char_clks = char_clks(uarts[chipsel].regs.dll, uarts[chipsel].regs.dlh, uarts[chipsel].regs.lcr);
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uarts[chipsel].char_clks = char_clks(uarts[chipsel].regs.dll, uarts[chipsel].regs.dlh, uarts[chipsel].regs.lcr);
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break;
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break;
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case UART_MCR:
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case UART_MCR:
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uarts[chipsel].regs.mcr = value & UART_VALID_MCR;
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uarts[chipsel].regs.mcr = value & UART_VALID_MCR;
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break;
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break;
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case UART_SCR:
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case UART_SCR:
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uarts[chipsel].regs.scr = value;
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uarts[chipsel].regs.scr = value;
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break;
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break;
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default:
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default:
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debug(1, "write out of range (addr %x)\n", addr);
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debug(1, "write out of range (addr %x)\n", addr);
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}
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}
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}
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}
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/* Read a specific UART register. */
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/* Read a specific UART register. */
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unsigned long uart_read_byte(unsigned long addr)
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unsigned long uart_read_byte(unsigned long addr)
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{
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{
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unsigned char value = 0;
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unsigned char value = 0;
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int chipsel;
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int chipsel;
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debug(4, "uart_read_byte(%x)", addr);
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debug(4, "uart_read_byte(%x)", addr);
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for(chipsel = 0; chipsel < MAX_UARTS; chipsel++)
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for(chipsel = 0; chipsel < MAX_UARTS; chipsel++)
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if ((addr & ~(UART_ADDR_SPACE-1)) == config.uarts[chipsel].baseaddr)
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if ((addr & ~(UART_ADDR_SPACE-1)) == config.uarts[chipsel].baseaddr)
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break;
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break;
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if (chipsel >= MAX_UARTS)
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if (chipsel >= MAX_UARTS)
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return 0;
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return 0;
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if (uarts[chipsel].regs.lcr & UART_LCR_DLAB) {
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if (uarts[chipsel].regs.lcr & UART_LCR_DLAB) {
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switch (addr % UART_ADDR_SPACE) {
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switch (addr % UART_ADDR_SPACE) {
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case UART_DLL:
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case UART_DLL:
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value = uarts[chipsel].regs.dll;
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value = uarts[chipsel].regs.dll;
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debug(4, "= %x\n", value);
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debug(4, "= %x\n", value);
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return value;
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return value;
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case UART_DLH:
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case UART_DLH:
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value = uarts[chipsel].regs.dlh;
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value = uarts[chipsel].regs.dlh;
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debug(4, "= %x\n", value);
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debug(4, "= %x\n", value);
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return value;
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return value;
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}
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}
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}
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}
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switch (addr % UART_ADDR_SPACE) {
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switch (addr % UART_ADDR_SPACE) {
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case UART_RXBUF:
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case UART_RXBUF:
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{ /* Print out FIFO for debugging */
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{ /* Print out FIFO for debugging */
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int i;
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int i;
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debug(4, "(%i/%i,%i,%i:", uarts[chipsel].istat.rxbuf_full, uarts[chipsel].fifo_len,
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debug(4, "(%i/%i,%i,%i:", uarts[chipsel].istat.rxbuf_full, uarts[chipsel].fifo_len,
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uarts[chipsel].istat.rxbuf_head, uarts[chipsel].istat.rxbuf_tail);
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uarts[chipsel].istat.rxbuf_head, uarts[chipsel].istat.rxbuf_tail);
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for (i = 0; i < uarts[chipsel].istat.rxbuf_full; i++)
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for (i = 0; i < uarts[chipsel].istat.rxbuf_full; i++)
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debug(4, "%02x ", uarts[chipsel].regs.rxbuf[(uarts[chipsel].istat.rxbuf_tail + i) % uarts[chipsel].fifo_len]);
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debug(4, "%02x ", uarts[chipsel].regs.rxbuf[(uarts[chipsel].istat.rxbuf_tail + i) % uarts[chipsel].fifo_len]);
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debug(4, ")");
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debug(4, ")");
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}
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}
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if (uarts[chipsel].istat.rxbuf_full) {
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if (uarts[chipsel].istat.rxbuf_full) {
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value = uarts[chipsel].regs.rxbuf[uarts[chipsel].istat.rxbuf_tail];
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value = uarts[chipsel].regs.rxbuf[uarts[chipsel].istat.rxbuf_tail];
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uarts[chipsel].istat.rxbuf_tail = (uarts[chipsel].istat.rxbuf_tail + 1) % uarts[chipsel].fifo_len;
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uarts[chipsel].istat.rxbuf_tail = (uarts[chipsel].istat.rxbuf_tail + 1) % uarts[chipsel].fifo_len;
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uarts[chipsel].istat.rxbuf_full--;
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uarts[chipsel].istat.rxbuf_full--;
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}
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}
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if (uarts[chipsel].istat.rxbuf_full)
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if (uarts[chipsel].istat.rxbuf_full)
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uarts[chipsel].regs.lsr |= UART_LSR_RDRDY;
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uarts[chipsel].regs.lsr |= UART_LSR_RDRDY;
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else
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else
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uarts[chipsel].regs.lsr &= ~UART_LSR_RDRDY;
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uarts[chipsel].regs.lsr &= ~UART_LSR_RDRDY;
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uarts[chipsel].istat.timeout_count = 0;
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uarts[chipsel].istat.timeout_count = 0;
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break;
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break;
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case UART_IER:
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case UART_IER:
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value = uarts[chipsel].regs.ier & UART_VALID_IER;
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value = uarts[chipsel].regs.ier & UART_VALID_IER;
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break;
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break;
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case UART_IIR:
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case UART_IIR:
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value = (uarts[chipsel].regs.iir & UART_VALID_IIR) | 0xc0;
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value = (uarts[chipsel].regs.iir & UART_VALID_IIR) | 0xc0;
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if (uarts[chipsel].regs.ier & UART_IER_THRI)
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if (uarts[chipsel].regs.ier & UART_IER_THRI)
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uarts[chipsel].istat.thre_int = 0;
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uarts[chipsel].istat.thre_int = 0;
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break;
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break;
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case UART_LCR:
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case UART_LCR:
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value = uarts[chipsel].regs.lcr & UART_VALID_LCR;
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value = uarts[chipsel].regs.lcr & UART_VALID_LCR;
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break;
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break;
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case UART_MCR:
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case UART_MCR:
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value = 0;
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value = 0;
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break;
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break;
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case UART_LSR:
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case UART_LSR:
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value = uarts[chipsel].regs.lsr & UART_VALID_LSR;
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value = uarts[chipsel].regs.lsr & UART_VALID_LSR;
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uarts[chipsel].regs.lsr &=
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uarts[chipsel].regs.lsr &=
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~(UART_LSR_OVRRUN | UART_LSR_BREAK | UART_LSR_PARITY
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~(UART_LSR_OVRRUN | UART_LSR_BREAK | UART_LSR_PARITY
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| UART_LSR_FRAME | UART_LSR_RXERR);
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| UART_LSR_FRAME | UART_LSR_RXERR);
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break;
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break;
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case UART_MSR:
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case UART_MSR:
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value = uarts[chipsel].regs.msr & UART_VALID_MSR;
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value = uarts[chipsel].regs.msr & UART_VALID_MSR;
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uarts[chipsel].regs.msr = 0;
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uarts[chipsel].regs.msr = 0;
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break;
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break;
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case UART_SCR:
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case UART_SCR:
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value = uarts[chipsel].regs.scr;
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value = uarts[chipsel].regs.scr;
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break;
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break;
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default:
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default:
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debug(1, "read out of range (addr %x)\n", addr);
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debug(1, "read out of range (addr %x)\n", addr);
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}
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}
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debug(4, " = %x\n", value);
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debug(4, " = %x\n", value);
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return value;
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return value;
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}
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}
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/* Function that handles incoming VAPI data. */
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/* Function that handles incoming VAPI data. */
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void uart_vapi_read (unsigned long id, unsigned long data)
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void uart_vapi_read (unsigned long id, unsigned long data)
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{
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{
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int uart;
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int uart;
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debug(4, "UART: id %08x, data %08x\n", id, data);
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debug(4, "UART: id %08x, data %08x\n", id, data);
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uart = id & VAPI_DEVICE_ID;
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uart = id & VAPI_DEVICE_ID;
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uarts[uart].vapi_buf[uarts[uart].vapi_buf_head_ptr] = data;
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uarts[uart].vapi_buf[uarts[uart].vapi_buf_head_ptr] = data;
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uarts[uart].vapi_buf_head_ptr = (uarts[uart].vapi_buf_head_ptr + 1) % UART_VAPI_BUF_LEN;
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uarts[uart].vapi_buf_head_ptr = (uarts[uart].vapi_buf_head_ptr + 1) % UART_VAPI_BUF_LEN;
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if (uarts[uart].vapi_buf_tail_ptr == uarts[uart].vapi_buf_head_ptr) {
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if (uarts[uart].vapi_buf_tail_ptr == uarts[uart].vapi_buf_head_ptr) {
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fprintf (stderr, "FATAL: uart VAPI buffer to small.\n");
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fprintf (stderr, "FATAL: uart VAPI buffer to small.\n");
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exit (1);
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exit (1);
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}
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}
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}
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}
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|
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static void send_char (int uart, int bits_send)
|
static void send_char (int uart, int bits_send)
|
{
|
{
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PRINTF ("'%c'\n", uarts[uart].iregs.txser);
|
PRINTF ("'%c'\n", uarts[uart].iregs.txser);
|
debug(4, "TX \'%c\' via UART%d...\n", uarts[uart].iregs.txser, uart);
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debug(4, "TX \'%c\' via UART%d...\n", uarts[uart].iregs.txser, uart);
|
if (uarts[uart].regs.mcr & UART_MCR_LOOP)
|
if (uarts[uart].regs.mcr & UART_MCR_LOOP)
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uarts[uart].iregs.loopback = uarts[uart].iregs.txser;
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uarts[uart].iregs.loopback = uarts[uart].iregs.txser;
|
else {
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else {
|
/* Send to either VAPI or to file */
|
/* Send to either VAPI or to file */
|
if (config.uarts[uart].vapi_id) {
|
if (config.uarts[uart].vapi_id) {
|
int par, pe, fe, nbits;
|
int par, pe, fe, nbits;
|
int j, data;
|
int j, data;
|
unsigned long packet = 0;
|
unsigned long packet = 0;
|
|
|
nbits = MIN (bits_send, (uarts[uart].regs.lcr & UART_LCR_WLEN8) + 5);
|
nbits = MIN (bits_send, (uarts[uart].regs.lcr & UART_LCR_WLEN8) + 5);
|
/* Encode a packet */
|
/* Encode a packet */
|
packet = uarts[uart].iregs.txser & ((1 << nbits) - 1);
|
packet = uarts[uart].iregs.txser & ((1 << nbits) - 1);
|
|
|
/* Calculate parity */
|
/* Calculate parity */
|
for (j = 0, par = 0; j < nbits; j++)
|
for (j = 0, par = 0; j < nbits; j++)
|
par ^= (packet >> j) & 1;
|
par ^= (packet >> j) & 1;
|
|
|
if (uarts[uart].regs.lcr & UART_LCR_PARITY) {
|
if (uarts[uart].regs.lcr & UART_LCR_PARITY) {
|
if (uarts[uart].regs.lcr & UART_LCR_SPAR) {
|
if (uarts[uart].regs.lcr & UART_LCR_SPAR) {
|
packet |= 1 << nbits;
|
packet |= 1 << nbits;
|
} else {
|
} else {
|
if (uarts[uart].regs.lcr & UART_LCR_EPAR)
|
if (uarts[uart].regs.lcr & UART_LCR_EPAR)
|
packet |= par << nbits;
|
packet |= par << nbits;
|
else
|
else
|
packet |= (par ^ 1) << nbits;
|
packet |= (par ^ 1) << nbits;
|
}
|
}
|
nbits++;
|
nbits++;
|
}
|
}
|
packet |= 1 << (nbits++);
|
packet |= 1 << (nbits++);
|
if (uarts[uart].regs.lcr & UART_LCR_STOP)
|
if (uarts[uart].regs.lcr & UART_LCR_STOP)
|
packet |= 1 << (nbits++);
|
packet |= 1 << (nbits++);
|
|
|
/* Decode a packet */
|
/* Decode a packet */
|
nbits = (uarts[uart].vapi.lcr & UART_LCR_WLEN8) + 5;
|
nbits = (uarts[uart].vapi.lcr & UART_LCR_WLEN8) + 5;
|
data = packet & ((1 << nbits) - 1);
|
data = packet & ((1 << nbits) - 1);
|
|
|
/* Calculate parity, including parity bit */
|
/* Calculate parity, including parity bit */
|
for (j = 0, par = 0; j < nbits + 1; j++)
|
for (j = 0, par = 0; j < nbits + 1; j++)
|
par ^= (packet >> j) & 1;
|
par ^= (packet >> j) & 1;
|
|
|
if (uarts[uart].vapi.lcr & UART_LCR_PARITY) {
|
if (uarts[uart].vapi.lcr & UART_LCR_PARITY) {
|
if (uarts[uart].vapi.lcr & UART_LCR_SPAR) {
|
if (uarts[uart].vapi.lcr & UART_LCR_SPAR) {
|
pe = !((packet >> nbits) & 1);
|
pe = !((packet >> nbits) & 1);
|
} else {
|
} else {
|
if (uarts[uart].vapi.lcr & UART_LCR_EPAR)
|
if (uarts[uart].vapi.lcr & UART_LCR_EPAR)
|
pe = par != 0;
|
pe = par != 0;
|
else
|
else
|
pe = par != 1;
|
pe = par != 1;
|
}
|
}
|
nbits++;
|
nbits++;
|
} else
|
} else
|
pe = 0;
|
pe = 0;
|
|
|
fe = ((packet >> (nbits++)) & 1) ^ 1;
|
fe = ((packet >> (nbits++)) & 1) ^ 1;
|
if (uarts[uart].vapi.lcr & UART_LCR_STOP)
|
if (uarts[uart].vapi.lcr & UART_LCR_STOP)
|
fe |= ((packet >> (nbits++)) & 1) ^ 1;
|
fe |= ((packet >> (nbits++)) & 1) ^ 1;
|
|
|
debug (4, "lcr vapi %02x, uart %02x\n", uarts[uart].vapi.lcr, uarts[uart].regs.lcr);
|
debug (4, "lcr vapi %02x, uart %02x\n", uarts[uart].vapi.lcr, uarts[uart].regs.lcr);
|
data |= (uarts[uart].vapi.lcr << 8) | (pe << 16) | (fe << 17) | (uarts[uart].vapi.lcr << 8);
|
data |= (uarts[uart].vapi.lcr << 8) | (pe << 16) | (fe << 17) | (uarts[uart].vapi.lcr << 8);
|
PRINTF ("vapi_send (%08x, %08x)\n", config.uarts[uart].vapi_id, data);
|
PRINTF ("vapi_send (%08x, %08x)\n", config.uarts[uart].vapi_id, data);
|
debug (4, "vapi_send (%08x, %08x)\n", config.uarts[uart].vapi_id, data);
|
debug (4, "vapi_send (%08x, %08x)\n", config.uarts[uart].vapi_id, data);
|
vapi_send (config.uarts[uart].vapi_id, data);
|
vapi_send (config.uarts[uart].vapi_id, data);
|
} else {
|
} else {
|
fputc((int)(uarts[uart].iregs.txser & 0xFF), uarts[uart].txfs);
|
char buffer[1] = { uarts[uart].iregs.txser & 0xFF };
|
fflush(uarts[uart].txfs);
|
channel_write(channels[uart], buffer, 1);
|
}
|
}
|
}
|
}
|
uarts[uart].istat.txser_full = 0;
|
uarts[uart].istat.txser_full = 0;
|
uarts[uart].istat.txser_clks = 0;
|
uarts[uart].istat.txser_clks = 0;
|
}
|
}
|
|
|
/* Adds a character to the FIFO */
|
/* Adds a character to the FIFO */
|
|
|
void uart_add_char (int uart, int ch)
|
void uart_add_char (int uart, int ch)
|
{
|
{
|
if (uarts[uart].istat.rxbuf_full + 1 > uarts[uart].fifo_len)
|
if (uarts[uart].istat.rxbuf_full + 1 > uarts[uart].fifo_len)
|
uarts[uart].regs.lsr |= UART_LSR_OVRRUN | UART_LSR_RXERR;
|
uarts[uart].regs.lsr |= UART_LSR_OVRRUN | UART_LSR_RXERR;
|
else {
|
else {
|
debug(4, "add %02x\n", ch);
|
debug(4, "add %02x\n", ch);
|
uarts[uart].regs.rxbuf[uarts[uart].istat.rxbuf_head] = ch;
|
uarts[uart].regs.rxbuf[uarts[uart].istat.rxbuf_head] = ch;
|
uarts[uart].istat.rxbuf_head = (uarts[uart].istat.rxbuf_head + 1) % uarts[uart].fifo_len;
|
uarts[uart].istat.rxbuf_head = (uarts[uart].istat.rxbuf_head + 1) % uarts[uart].fifo_len;
|
uarts[uart].istat.rxbuf_full++;
|
uarts[uart].istat.rxbuf_full++;
|
}
|
}
|
uarts[uart].regs.lsr |= UART_LSR_RDRDY;
|
uarts[uart].regs.lsr |= UART_LSR_RDRDY;
|
uarts[uart].istat.timeout_count = 0;
|
uarts[uart].istat.timeout_count = 0;
|
}
|
}
|
|
|
/* Simulation hook. Must be called every clock cycle to simulate all UART
|
/* Simulation hook. Must be called every clock cycle to simulate all UART
|
devices. It does internal functional UART simulation. */
|
devices. It does internal functional UART simulation. */
|
void uart_clock16 (int i)
|
void uart_clock16 (int i)
|
{
|
{
|
int retval;
|
int retval;
|
|
|
/* Schedule for later */
|
/* Schedule for later */
|
SCHED_ADD (uart_clock16, i, runtime.sim.cycles + UART_CLOCK_DIVIDER);
|
SCHED_ADD (uart_clock16, i, runtime.sim.cycles + UART_CLOCK_DIVIDER);
|
|
|
/* If VAPI is not selected, UART communicates with two file streams;
|
/* If VAPI is not selected, UART communicates with two file streams;
|
if VAPI is selected, we use VAPI streams. */
|
if VAPI is selected, we use VAPI streams. */
|
/* if txfs is corrupted, skip this uart. */
|
/* if txfs is corrupted, skip this uart. */
|
if (!config.uarts[i].vapi_id && !uarts[i].txfs) return;
|
if (!config.uarts[i].vapi_id && !channel_ok(channels[i])) return;
|
|
|
if (uarts[i].vapi.next_break_cnt >= 0)
|
if (uarts[i].vapi.next_break_cnt >= 0)
|
if (--uarts[i].vapi.next_break_cnt < 0) {
|
if (--uarts[i].vapi.next_break_cnt < 0) {
|
if (!(uarts[i].vapi.cur_break = uarts[i].vapi.next_break))
|
if (!(uarts[i].vapi.cur_break = uarts[i].vapi.next_break))
|
uarts[i].istat.break_set = 0;
|
uarts[i].istat.break_set = 0;
|
}
|
}
|
|
|
/***************** Transmit *****************/
|
/***************** Transmit *****************/
|
if (!uarts[i].istat.txser_full) {
|
if (!uarts[i].istat.txser_full) {
|
// uarts[i].regs.lsr |= UART_LSR_TXBUFE;
|
// uarts[i].regs.lsr |= UART_LSR_TXBUFE;
|
if (uarts[i].istat.txbuf_full) {
|
if (uarts[i].istat.txbuf_full) {
|
uarts[i].iregs.txser = uarts[i].regs.txbuf[uarts[i].istat.txbuf_tail];
|
uarts[i].iregs.txser = uarts[i].regs.txbuf[uarts[i].istat.txbuf_tail];
|
uarts[i].istat.txbuf_tail = (uarts[i].istat.txbuf_tail + 1) % uarts[i].fifo_len;
|
uarts[i].istat.txbuf_tail = (uarts[i].istat.txbuf_tail + 1) % uarts[i].fifo_len;
|
uarts[i].istat.txser_full = 1;
|
uarts[i].istat.txser_full = 1;
|
uarts[i].istat.txbuf_full--;
|
uarts[i].istat.txbuf_full--;
|
uarts[i].regs.lsr &= ~UART_LSR_TXSERE;
|
uarts[i].regs.lsr &= ~UART_LSR_TXSERE;
|
uarts[i].istat.thre_int = 1;
|
uarts[i].istat.thre_int = 1;
|
} else {
|
} else {
|
uarts[i].regs.lsr |= UART_LSR_TXSERE;
|
uarts[i].regs.lsr |= UART_LSR_TXSERE;
|
uarts[i].regs.lsr |= UART_LSR_TXBUFE;
|
uarts[i].regs.lsr |= UART_LSR_TXBUFE;
|
}
|
}
|
} else if (uarts[i].char_clks <= uarts[i].istat.txser_clks++) {
|
} else if (uarts[i].char_clks <= uarts[i].istat.txser_clks++) {
|
send_char(i, (uarts[i].regs.lcr & UART_LCR_WLEN8) + 5); /* We've sent all bits */
|
send_char(i, (uarts[i].regs.lcr & UART_LCR_WLEN8) + 5); /* We've sent all bits */
|
} else {
|
} else {
|
/* We are still sending char here*/
|
/* We are still sending char here*/
|
|
|
/* Check if we set the break bit */
|
/* Check if we set the break bit */
|
if (uarts[i].regs.lcr & UART_LCR_SBC) {
|
if (uarts[i].regs.lcr & UART_LCR_SBC) {
|
if (!uarts[i].vapi.break_sent) {
|
if (!uarts[i].vapi.break_sent) {
|
#if 0
|
#if 0
|
/* Send broken frame */
|
/* Send broken frame */
|
int nbits_sent = ((uarts[i].regs.lcr & UART_LCR_WLEN8) + 5) * (uarts[i].istat.txser_clks - 1) / uarts[i].char_clks;
|
int nbits_sent = ((uarts[i].regs.lcr & UART_LCR_WLEN8) + 5) * (uarts[i].istat.txser_clks - 1) / uarts[i].char_clks;
|
send_char(i, nbits_sent);
|
send_char(i, nbits_sent);
|
#endif
|
#endif
|
/* Send one break signal */
|
/* Send one break signal */
|
vapi_send (config.uarts[i].vapi_id, UART_LCR_SBC << 8);
|
vapi_send (config.uarts[i].vapi_id, UART_LCR_SBC << 8);
|
uarts[i].vapi.break_sent = 1;
|
uarts[i].vapi.break_sent = 1;
|
}
|
}
|
/* mark as character was sent */
|
/* mark as character was sent */
|
uarts[i].istat.txser_full = 0;
|
uarts[i].istat.txser_full = 0;
|
uarts[i].istat.txser_clks = 0;
|
uarts[i].istat.txser_clks = 0;
|
} else
|
} else
|
uarts[i].vapi.break_sent = 0;
|
uarts[i].vapi.break_sent = 0;
|
}
|
}
|
|
|
/***************** Receive *****************/
|
/***************** Receive *****************/
|
|
|
/* Is there a break? */
|
/* Is there a break? */
|
if (uarts[i].vapi.cur_break) {
|
if (uarts[i].vapi.cur_break) {
|
uarts[i].vapi.cur_break_cnt++;
|
uarts[i].vapi.cur_break_cnt++;
|
if (uarts[i].vapi.cur_break_cnt > UART_BREAK_COUNT * uarts[i].vapi.char_clks) {
|
if (uarts[i].vapi.cur_break_cnt > UART_BREAK_COUNT * uarts[i].vapi.char_clks) {
|
if (!uarts[i].istat.break_set) {
|
if (!uarts[i].istat.break_set) {
|
unsigned lsr;
|
unsigned lsr;
|
uarts[i].istat.break_set = 1;
|
uarts[i].istat.break_set = 1;
|
lsr = UART_LSR_BREAK | UART_LSR_RXERR | UART_LSR_RDRDY;
|
lsr = UART_LSR_BREAK | UART_LSR_RXERR | UART_LSR_RDRDY;
|
PRINTF ("[%x]\n", uarts[i].regs.lsr);
|
PRINTF ("[%x]\n", uarts[i].regs.lsr);
|
uarts[i].istat.rxser_full = 0;
|
uarts[i].istat.rxser_full = 0;
|
uarts[i].istat.rxser_clks = 0;
|
uarts[i].istat.rxser_clks = 0;
|
uart_add_char (i, lsr << 8);
|
uart_add_char (i, lsr << 8);
|
} else
|
} else
|
uarts[i].vapi.cur_break_cnt = 0;
|
uarts[i].vapi.cur_break_cnt = 0;
|
}
|
}
|
if (uarts[i].istat.rxser_full) {
|
if (uarts[i].istat.rxser_full) {
|
uarts[i].istat.rxser_full = 0;
|
uarts[i].istat.rxser_full = 0;
|
uarts[i].istat.rxser_clks = 0;
|
uarts[i].istat.rxser_clks = 0;
|
}
|
}
|
} else {
|
} else {
|
if (uarts[i].istat.rxser_full) {
|
if (uarts[i].istat.rxser_full) {
|
if (uarts[i].char_clks <= uarts[i].istat.rxser_clks++) {
|
if (uarts[i].char_clks <= uarts[i].istat.rxser_clks++) {
|
/* Set unused character bits to zero and allow lsr register in fifo */
|
/* Set unused character bits to zero and allow lsr register in fifo */
|
uarts[i].iregs.rxser &= ((1 << ((uarts[i].regs.lcr & 3) + 5)) - 1) | 0xff00;
|
uarts[i].iregs.rxser &= ((1 << ((uarts[i].regs.lcr & 3) + 5)) - 1) | 0xff00;
|
debug(4, "Receiving 0x%02x'%c' via UART%d...\n", uarts[i].iregs.rxser, uarts[i].iregs.rxser, i);
|
debug(4, "Receiving 0x%02x'%c' via UART%d...\n", uarts[i].iregs.rxser, uarts[i].iregs.rxser, i);
|
uarts[i].istat.rxser_full = 0;
|
uarts[i].istat.rxser_full = 0;
|
uarts[i].istat.rxser_clks = 0;
|
uarts[i].istat.rxser_clks = 0;
|
uart_add_char (i, uarts[i].iregs.rxser);
|
uart_add_char (i, uarts[i].iregs.rxser);
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
/* Check if there is something waiting, and put it into rxser */
|
/* Check if there is something waiting, and put it into rxser */
|
if (uarts[i].regs.mcr & UART_MCR_LOOP) {
|
if (uarts[i].regs.mcr & UART_MCR_LOOP) {
|
uarts[i].iregs.rxser = uarts[i].iregs.loopback;
|
uarts[i].iregs.rxser = uarts[i].iregs.loopback;
|
uarts[i].istat.rxser_full = 1;
|
uarts[i].istat.rxser_full = 1;
|
} else {
|
} else {
|
if (!config.uarts[i].vapi_id) {
|
if (!config.uarts[i].vapi_id) {
|
if(uarts[i].istat.rxser_full == 0) {
|
if(uarts[i].istat.rxser_full == 0) {
|
if (uarts[i].slowdown)
|
if (uarts[i].slowdown)
|
uarts[i].slowdown--;
|
uarts[i].slowdown--;
|
else if((retval = fgetc(uarts[i].rxfs)) != EOF) {
|
else {
|
uarts[i].iregs.rxser = (char)retval;
|
char buffer[1];
|
|
retval = channel_read(channels[i], buffer, 1);
|
|
if(retval < 0)
|
|
perror(config.uarts[i].channel);
|
|
else if(retval > 0) {
|
|
uarts[i].iregs.rxser = buffer[0];
|
uarts[i].istat.rxser_full = 1;
|
uarts[i].istat.rxser_full = 1;
|
} else uarts[i].slowdown = UART_FGETC_SLOWDOWN;
|
} else
|
|
uarts[i].slowdown = UART_FGETC_SLOWDOWN;
|
|
}
|
}
|
}
|
} else { /* VAPI */
|
} else { /* VAPI */
|
int received = 0;
|
int received = 0;
|
/* do not handle commands while receiving */
|
/* do not handle commands while receiving */
|
if (uarts[i].istat.rxser_full) return;
|
if (uarts[i].istat.rxser_full) return;
|
while (!received) {
|
while (!received) {
|
if (uarts[i].vapi_buf_head_ptr != uarts[i].vapi_buf_tail_ptr) {
|
if (uarts[i].vapi_buf_head_ptr != uarts[i].vapi_buf_tail_ptr) {
|
unsigned long data = uarts[i].vapi_buf[uarts[i].vapi_buf_tail_ptr];
|
unsigned long data = uarts[i].vapi_buf[uarts[i].vapi_buf_tail_ptr];
|
debug(4, "Handling: %08x (%i,%i)\n", data, uarts[i].vapi_buf_head_ptr, uarts[i].vapi_buf_tail_ptr);
|
debug(4, "Handling: %08x (%i,%i)\n", data, uarts[i].vapi_buf_head_ptr, uarts[i].vapi_buf_tail_ptr);
|
uarts[i].vapi_buf_tail_ptr = (uarts[i].vapi_buf_tail_ptr + 1) % UART_VAPI_BUF_LEN;
|
uarts[i].vapi_buf_tail_ptr = (uarts[i].vapi_buf_tail_ptr + 1) % UART_VAPI_BUF_LEN;
|
switch (data >> 24) {
|
switch (data >> 24) {
|
case 0x00:
|
case 0x00:
|
uarts[i].vapi.lcr = (data >> 8) & 0xff;
|
uarts[i].vapi.lcr = (data >> 8) & 0xff;
|
/* Put data into rx fifo */
|
/* Put data into rx fifo */
|
uarts[i].iregs.rxser = data & 0xff;
|
uarts[i].iregs.rxser = data & 0xff;
|
uarts[i].vapi.char_clks = char_clks (uarts[i].vapi.dll, uarts[i].vapi.dlh, uarts[i].vapi.lcr);
|
uarts[i].vapi.char_clks = char_clks (uarts[i].vapi.dll, uarts[i].vapi.dlh, uarts[i].vapi.lcr);
|
if ((uarts[i].vapi.lcr & ~UART_LCR_SBC) != (uarts[i].regs.lcr & ~UART_LCR_SBC)
|
if ((uarts[i].vapi.lcr & ~UART_LCR_SBC) != (uarts[i].regs.lcr & ~UART_LCR_SBC)
|
|| uarts[i].vapi.char_clks != uarts[i].char_clks
|
|| uarts[i].vapi.char_clks != uarts[i].char_clks
|
|| uarts[i].vapi.skew < -MAX_SKEW || uarts[i].vapi.skew > MAX_SKEW) {
|
|| uarts[i].vapi.skew < -MAX_SKEW || uarts[i].vapi.skew > MAX_SKEW) {
|
debug (3, "WARNING: unmatched VAPI (%02x) and uart (%02x) modes.\n",
|
debug (3, "WARNING: unmatched VAPI (%02x) and uart (%02x) modes.\n",
|
uarts[i].vapi.lcr & ~UART_LCR_SBC, uarts[i].regs.lcr & ~UART_LCR_SBC);
|
uarts[i].vapi.lcr & ~UART_LCR_SBC, uarts[i].regs.lcr & ~UART_LCR_SBC);
|
/* Set error bits */
|
/* Set error bits */
|
uarts[i].iregs.rxser |= (UART_LSR_FRAME | UART_LSR_RXERR) << 8;
|
uarts[i].iregs.rxser |= (UART_LSR_FRAME | UART_LSR_RXERR) << 8;
|
if (uarts[i].regs.lcr & UART_LCR_PARITY) uarts[i].iregs.rxser |= UART_LSR_PARITY << 8;
|
if (uarts[i].regs.lcr & UART_LCR_PARITY) uarts[i].iregs.rxser |= UART_LSR_PARITY << 8;
|
}
|
}
|
uarts[i].istat.rxser_full = 1;
|
uarts[i].istat.rxser_full = 1;
|
received = 1;
|
received = 1;
|
break;
|
break;
|
case 0x01:
|
case 0x01:
|
uarts[i].vapi.dll = (data >> 0) & 0xff;
|
uarts[i].vapi.dll = (data >> 0) & 0xff;
|
uarts[i].vapi.dlh = (data >> 8) & 0xff;
|
uarts[i].vapi.dlh = (data >> 8) & 0xff;
|
break;
|
break;
|
case 0x02:
|
case 0x02:
|
uarts[i].vapi.lcr = (data >> 8) & 0xff;
|
uarts[i].vapi.lcr = (data >> 8) & 0xff;
|
break;
|
break;
|
case 0x03:
|
case 0x03:
|
uarts[i].vapi.skew = (signed short)(data & 0xffff);
|
uarts[i].vapi.skew = (signed short)(data & 0xffff);
|
break;
|
break;
|
case 0x04:
|
case 0x04:
|
uarts[i].vapi.next_break_cnt = data & 0xffff;
|
uarts[i].vapi.next_break_cnt = data & 0xffff;
|
uarts[i].vapi.next_break = (data >> 16) & 1;
|
uarts[i].vapi.next_break = (data >> 16) & 1;
|
break;
|
break;
|
default:
|
default:
|
debug (0, "WARNING: Invalid vapi command %02x\n", data >> 24);
|
debug (0, "WARNING: Invalid vapi command %02x\n", data >> 24);
|
break;
|
break;
|
}
|
}
|
} else break;
|
} else break;
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
/***************** Loopback *****************/
|
/***************** Loopback *****************/
|
if (uarts[i].regs.mcr & UART_MCR_LOOP) {
|
if (uarts[i].regs.mcr & UART_MCR_LOOP) {
|
debug(5, "uart_clock: Loopback\n");
|
debug(5, "uart_clock: Loopback\n");
|
if ((uarts[i].regs.mcr & UART_MCR_AUX2) !=
|
if ((uarts[i].regs.mcr & UART_MCR_AUX2) !=
|
((uarts[i].regs.msr & UART_MSR_DCD) >> 4))
|
((uarts[i].regs.msr & UART_MSR_DCD) >> 4))
|
uarts[i].regs.msr |= UART_MSR_DDCD;
|
uarts[i].regs.msr |= UART_MSR_DDCD;
|
if ((uarts[i].regs.mcr & UART_MCR_AUX1) <
|
if ((uarts[i].regs.mcr & UART_MCR_AUX1) <
|
((uarts[i].regs.msr & UART_MSR_RI) >> 4))
|
((uarts[i].regs.msr & UART_MSR_RI) >> 4))
|
uarts[i].regs.msr |= UART_MSR_TERI;
|
uarts[i].regs.msr |= UART_MSR_TERI;
|
if ((uarts[i].regs.mcr & UART_MCR_RTS) !=
|
if ((uarts[i].regs.mcr & UART_MCR_RTS) !=
|
((uarts[i].regs.msr & UART_MSR_CTS) >> 3))
|
((uarts[i].regs.msr & UART_MSR_CTS) >> 3))
|
uarts[i].regs.msr |= UART_MSR_DCTS;
|
uarts[i].regs.msr |= UART_MSR_DCTS;
|
if ((uarts[i].regs.mcr & UART_MCR_DTR) !=
|
if ((uarts[i].regs.mcr & UART_MCR_DTR) !=
|
((uarts[i].regs.msr & UART_MSR_DSR) >> 5))
|
((uarts[i].regs.msr & UART_MSR_DSR) >> 5))
|
uarts[i].regs.msr |= UART_MSR_DDSR;
|
uarts[i].regs.msr |= UART_MSR_DDSR;
|
uarts[i].regs.msr &= ~(UART_MSR_DCD | UART_MSR_RI
|
uarts[i].regs.msr &= ~(UART_MSR_DCD | UART_MSR_RI
|
| UART_MSR_DSR | UART_MSR_CTS);
|
| UART_MSR_DSR | UART_MSR_CTS);
|
uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_AUX2) << 4);
|
uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_AUX2) << 4);
|
uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_AUX1) << 4);
|
uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_AUX1) << 4);
|
uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_RTS) << 3);
|
uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_RTS) << 3);
|
uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_DTR) << 5);
|
uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_DTR) << 5);
|
}
|
}
|
|
|
if (uarts[i].regs.lsr & UART_LSR_RDRDY)
|
if (uarts[i].regs.lsr & UART_LSR_RDRDY)
|
uarts[i].istat.timeout_count++;
|
uarts[i].istat.timeout_count++;
|
|
|
/* Update LSR error bits from the ones from rx FIFO */
|
/* Update LSR error bits from the ones from rx FIFO */
|
if (uarts[i].istat.rxbuf_full) {
|
if (uarts[i].istat.rxbuf_full) {
|
uarts[i].regs.lsr |= uarts[i].regs.rxbuf[uarts[i].istat.rxbuf_tail] >> 8;
|
uarts[i].regs.lsr |= uarts[i].regs.rxbuf[uarts[i].istat.rxbuf_tail] >> 8;
|
/* we must delete the lsr status, so that we can clear it from lsr */
|
/* we must delete the lsr status, so that we can clear it from lsr */
|
uarts[i].regs.rxbuf[uarts[i].istat.rxbuf_tail] &= 0xff;
|
uarts[i].regs.rxbuf[uarts[i].istat.rxbuf_tail] &= 0xff;
|
}
|
}
|
|
|
/* Interrupt detection in proper priority order. */
|
/* Interrupt detection in proper priority order. */
|
uarts[i].regs.iir = UART_IIR_NO_INT;
|
uarts[i].regs.iir = UART_IIR_NO_INT;
|
if (uarts[i].regs.ier & UART_IER_RLSI && /* Receiver LS */
|
if (uarts[i].regs.ier & UART_IER_RLSI && /* Receiver LS */
|
uarts[i].regs.lsr & (UART_LSR_OVRRUN | UART_LSR_PARITY
|
uarts[i].regs.lsr & (UART_LSR_OVRRUN | UART_LSR_PARITY
|
| UART_LSR_FRAME | UART_LSR_BREAK)) {
|
| UART_LSR_FRAME | UART_LSR_BREAK)) {
|
uarts[i].regs.iir = UART_IIR_RLSI;
|
uarts[i].regs.iir = UART_IIR_RLSI;
|
} else if ((uarts[i].regs.ier & UART_IER_RDI) /* RD available */
|
} else if ((uarts[i].regs.ier & UART_IER_RDI) /* RD available */
|
&& (uarts[i].istat.rxbuf_full >= UART_FIFO_TRIGGER(uarts[i].regs.fcr >> 6))
|
&& (uarts[i].istat.rxbuf_full >= UART_FIFO_TRIGGER(uarts[i].regs.fcr >> 6))
|
&& (uarts[i].regs.lsr & UART_LSR_RDRDY)) {
|
&& (uarts[i].regs.lsr & UART_LSR_RDRDY)) {
|
uarts[i].regs.iir = UART_IIR_RDI;
|
uarts[i].regs.iir = UART_IIR_RDI;
|
} else if ((uarts[i].regs.ier & UART_IER_RDI) /* timeout */
|
} else if ((uarts[i].regs.ier & UART_IER_RDI) /* timeout */
|
&& (uarts[i].istat.timeout_count >= UART_CHAR_TIMEOUT * uarts[i].char_clks)) {
|
&& (uarts[i].istat.timeout_count >= UART_CHAR_TIMEOUT * uarts[i].char_clks)) {
|
uarts[i].regs.iir = UART_IIR_CTI;
|
uarts[i].regs.iir = UART_IIR_CTI;
|
} else if (uarts[i].regs.ier & UART_IER_THRI && /* Transm. empty */
|
} else if (uarts[i].regs.ier & UART_IER_THRI && /* Transm. empty */
|
uarts[i].regs.lsr & UART_LSR_TXBUFE &&
|
uarts[i].regs.lsr & UART_LSR_TXBUFE &&
|
uarts[i].istat.thre_int == 1) {
|
uarts[i].istat.thre_int == 1) {
|
uarts[i].regs.iir = UART_IIR_THRI;
|
uarts[i].regs.iir = UART_IIR_THRI;
|
} else if (uarts[i].regs.ier & UART_IER_MSI && /* Modem status */
|
} else if (uarts[i].regs.ier & UART_IER_MSI && /* Modem status */
|
uarts[i].regs.msr & (UART_MSR_DCTS | UART_MSR_DDSR
|
uarts[i].regs.msr & (UART_MSR_DCTS | UART_MSR_DDSR
|
| UART_MSR_TERI | UART_MSR_DDCD)) {
|
| UART_MSR_TERI | UART_MSR_DDCD)) {
|
uarts[i].regs.iir = UART_IIR_MSI;
|
uarts[i].regs.iir = UART_IIR_MSI;
|
}
|
}
|
if (!(uarts[i].regs.iir & UART_IIR_NO_INT)) {
|
if (!(uarts[i].regs.iir & UART_IIR_NO_INT)) {
|
debug (4, "uarts[i].regs.iir = %i\t", uarts[i].regs.iir);
|
debug (4, "uarts[i].regs.iir = %i\t", uarts[i].regs.iir);
|
report_interrupt(config.uarts[i].irq);
|
report_interrupt(config.uarts[i].irq);
|
}
|
}
|
}
|
}
|
|
|
/* Reset. It initializes all registers of all UART devices to zero values,
|
/* Reset. It initializes all registers of all UART devices to zero values,
|
(re)opens all RX/TX file streams and places devices in memory address
|
(re)opens all RX/TX file streams and places devices in memory address
|
space. */
|
space. */
|
void uart_reset()
|
void uart_reset()
|
{
|
{
|
int i;
|
int i;
|
if (config.sim.verbose && config.nuarts) PRINTF("Resetting %u UART(s).\n", config.nuarts);
|
if (config.sim.verbose && config.nuarts) PRINTF("Resetting %u UART(s).\n", config.nuarts);
|
memset(uarts, 0, sizeof(uarts));
|
memset(uarts, 0, sizeof(uarts));
|
|
|
for(i = 0; i < config.nuarts; i++) {
|
for(i = 0; i < config.nuarts; i++) {
|
if (config.uarts[i].vapi_id) {
|
if (config.uarts[i].vapi_id) {
|
if ((config.uarts[i].vapi_id & VAPI_DEVICE_ID) != i) {
|
if ((config.uarts[i].vapi_id & VAPI_DEVICE_ID) != i) {
|
fprintf (stderr, "ERROR: Wrong vapi_id (0x%x) for uart %i, last byte is required to be %02x; ignoring.\n", config.uarts[i].vapi_id, i, i);
|
fprintf (stderr, "ERROR: Wrong vapi_id (0x%x) for uart %i, last byte is required to be %02x; ignoring.\n", config.uarts[i].vapi_id, i, i);
|
config.uarts[i].vapi_id = 0;
|
config.uarts[i].vapi_id = 0;
|
uarts[i].txfs = 0;
|
|
} else {
|
} else {
|
vapi_install_handler (config.uarts[i].vapi_id, uart_vapi_read);
|
vapi_install_handler (config.uarts[i].vapi_id, uart_vapi_read);
|
register_memoryarea(config.uarts[i].baseaddr, UART_ADDR_SPACE, 1, 0, uart_read_byte, uart_write_byte);
|
register_memoryarea(config.uarts[i].baseaddr, UART_ADDR_SPACE, 1, 0, uart_read_byte, uart_write_byte);
|
}
|
}
|
} else if (config.uarts[i].txfile) { /* MM: Try to create stream. */
|
} else if (config.uarts[i].channel[0]) { /* MM: Try to create stream. */
|
if (!(uarts[i].rxfs = fopen(config.uarts[i].rxfile, "r"))
|
if(channels[i])
|
&& !(uarts[i].rxfs = fopen(config.uarts[i].rxfile, "r+"))) {
|
channel_close(channels[i]);
|
debug (0, "WARNING: UART%d has problems with RX file stream.\n", i);
|
else
|
|
channels[i] = channel_init(config.uarts[i].channel);
|
|
if(channel_open(channels[i]) < 0) {
|
|
debug (0, "WARNING: UART%d has problems with channel \"%s\".\n", i, config.uarts[i].channel);
|
continue;
|
continue;
|
}
|
}
|
uarts[i].txfs = fopen(config.uarts[i].txfile, "a");
|
if (config.sim.verbose)
|
if (uarts[i].rxfs && uarts[i].txfs && config.sim.verbose) {
|
|
PRINTF("UART%d at 0x%.8x uses ", i, config.uarts[i].baseaddr);
|
PRINTF("UART%d at 0x%.8x uses ", i, config.uarts[i].baseaddr);
|
PRINTF("%s for RX and %s for TX.\n", config.uarts[i].rxfile, config.uarts[i].txfile);
|
|
} else
|
|
debug (1, "WARNING: UART%d has problems with TX file stream.\n", i);
|
|
register_memoryarea(config.uarts[i].baseaddr, UART_ADDR_SPACE, 1, 0, uart_read_byte, uart_write_byte);
|
register_memoryarea(config.uarts[i].baseaddr, UART_ADDR_SPACE, 1, 0, uart_read_byte, uart_write_byte);
|
|
} else {
|
|
debug (0, "WARNING: UART%d has no vapi nor channel specified\n", i);
|
|
continue;
|
}
|
}
|
|
|
if (config.uarts[i].uart16550)
|
if (config.uarts[i].uart16550)
|
uarts[i].fifo_len = 16;
|
uarts[i].fifo_len = 16;
|
else
|
else
|
uarts[i].fifo_len = 1;
|
uarts[i].fifo_len = 1;
|
|
|
uarts[i].istat.rxbuf_head = uarts[i].istat.rxbuf_tail = 0;
|
uarts[i].istat.rxbuf_head = uarts[i].istat.rxbuf_tail = 0;
|
uarts[i].istat.txbuf_head = uarts[i].istat.txbuf_tail = 0;
|
uarts[i].istat.txbuf_head = uarts[i].istat.txbuf_tail = 0;
|
|
|
uarts[i].istat.break_set = 0;
|
uarts[i].istat.break_set = 0;
|
uarts[i].istat.timeout_count = 0;
|
uarts[i].istat.timeout_count = 0;
|
uarts[i].istat.thre_int = 1; /* FIFO is empty at start */
|
uarts[i].istat.thre_int = 1; /* FIFO is empty at start */
|
uarts[i].slowdown = UART_FGETC_SLOWDOWN;
|
uarts[i].slowdown = UART_FGETC_SLOWDOWN;
|
|
|
uarts[i].regs.lcr = UART_LCR_RESET;
|
uarts[i].regs.lcr = UART_LCR_RESET;
|
uarts[i].vapi.cur_break = uarts[i].vapi.cur_break_cnt = uarts[i].vapi.next_break = 0;
|
uarts[i].vapi.cur_break = uarts[i].vapi.cur_break_cnt = uarts[i].vapi.next_break = 0;
|
uarts[i].vapi.next_break_cnt = -1;
|
uarts[i].vapi.next_break_cnt = -1;
|
PRINTF ("%i\n", i);
|
PRINTF ("%i\n", i);
|
SCHED_ADD (uart_clock16, i, runtime.sim.cycles + UART_CLOCK_DIVIDER);
|
SCHED_ADD (uart_clock16, i, runtime.sim.cycles + UART_CLOCK_DIVIDER);
|
}
|
}
|
}
|
}
|
|
|
/* Print register values on stdout. */
|
/* Print register values on stdout. */
|
void uart_status()
|
void uart_status()
|
{
|
{
|
int i, j;
|
int i, j;
|
|
|
for(i = 0; i < config.nuarts; i++) {
|
for(i = 0; i < config.nuarts; i++) {
|
if ( !config.uarts[i].baseaddr )
|
if ( !config.uarts[i].baseaddr )
|
continue;
|
continue;
|
PRINTF("\nUART%d visible registers at 0x%.8x:\n", i, config.uarts[i].baseaddr);
|
PRINTF("\nUART%d visible registers at 0x%.8x:\n", i, config.uarts[i].baseaddr);
|
PRINTF("RXBUF:");
|
PRINTF("RXBUF:");
|
for (j = uarts[i].istat.rxbuf_head; j != uarts[i].istat.rxbuf_tail; j = (j + 1) % uarts[i].fifo_len)
|
for (j = uarts[i].istat.rxbuf_head; j != uarts[i].istat.rxbuf_tail; j = (j + 1) % uarts[i].fifo_len)
|
PRINTF (" %.2x", uarts[i].regs.rxbuf[j]);
|
PRINTF (" %.2x", uarts[i].regs.rxbuf[j]);
|
PRINTF(" TXBUF: %.2x\n", uarts[i].regs.txbuf);
|
PRINTF(" TXBUF: %.2x\n", uarts[i].regs.txbuf);
|
PRINTF("DLL : %.2x DLH : %.2x\n", uarts[i].regs.dll, uarts[i].regs.dlh);
|
PRINTF("DLL : %.2x DLH : %.2x\n", uarts[i].regs.dll, uarts[i].regs.dlh);
|
PRINTF("IER : %.2x IIR : %.2x\n", uarts[i].regs.ier, uarts[i].regs.iir);
|
PRINTF("IER : %.2x IIR : %.2x\n", uarts[i].regs.ier, uarts[i].regs.iir);
|
PRINTF("LCR : %.2x MCR : %.2x\n", uarts[i].regs.lcr, uarts[i].regs.mcr);
|
PRINTF("LCR : %.2x MCR : %.2x\n", uarts[i].regs.lcr, uarts[i].regs.mcr);
|
PRINTF("LSR : %.2x MSR : %.2x\n", uarts[i].regs.lsr, uarts[i].regs.msr);
|
PRINTF("LSR : %.2x MSR : %.2x\n", uarts[i].regs.lsr, uarts[i].regs.msr);
|
PRINTF("SCR : %.2x\n", uarts[i].regs.scr);
|
PRINTF("SCR : %.2x\n", uarts[i].regs.scr);
|
|
|
PRINTF("\nInternal registers (sim debug):\n");
|
PRINTF("\nInternal registers (sim debug):\n");
|
PRINTF("RXSER: %.2x TXSER: %.2x\n", uarts[i].iregs.rxser, uarts[i].iregs.txser);
|
PRINTF("RXSER: %.2x TXSER: %.2x\n", uarts[i].iregs.rxser, uarts[i].iregs.txser);
|
|
|
PRINTF("\nInternal status (sim debug):\n");
|
PRINTF("\nInternal status (sim debug):\n");
|
PRINTF("char_clks: %d\n", uarts[i].char_clks);
|
PRINTF("char_clks: %d\n", uarts[i].char_clks);
|
PRINTF("rxser_clks: %d txser_clks: %d\n", uarts[i].istat.rxser_clks, uarts[i].istat.txser_clks);
|
PRINTF("rxser_clks: %d txser_clks: %d\n", uarts[i].istat.rxser_clks, uarts[i].istat.txser_clks);
|
PRINTF("rxser: %d txser: %d\n", uarts[i].istat.rxser_full, uarts[i].istat.txser_full);
|
PRINTF("rxser: %d txser: %d\n", uarts[i].istat.rxser_full, uarts[i].istat.txser_full);
|
PRINTF("rxbuf: %d txbuf: %d\n", uarts[i].istat.rxbuf_full, uarts[i].istat.txbuf_full);
|
PRINTF("rxbuf: %d txbuf: %d\n", uarts[i].istat.rxbuf_full, uarts[i].istat.txbuf_full);
|
PRINTF("Using IRQ%i\n", config.uarts[i].irq);
|
PRINTF("Using IRQ%i\n", config.uarts[i].irq);
|
if (config.uarts[i].vapi_id)
|
if (config.uarts[i].vapi_id)
|
PRINTF ("Connected to vapi ID=%x\n\n", config.uarts[i].vapi_id);
|
PRINTF ("Connected to vapi ID=%x\n\n", config.uarts[i].vapi_id);
|
else
|
/* TODO: replace by a channel_status
|
PRINTF("RX fs: %p TX fs: %p\n\n", uarts[i].rxfs, uarts[i].txfs);
|
else
|
|
PRINTF("RX fs: %p TX fs: %p\n\n", uarts[i].rxfs, uarts[i].txfs);
|
|
*/
|
}
|
}
|
}
|
}
|
|
|
