/* 16450.c -- Simulation of 8250/16450 serial UART
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/* 16450.c -- Simulation of 8250/16450 serial UART
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* This is functional simulation of 8250/16450 UARTs. Since we RX/TX data
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/* This is functional simulation of 8250/16450 UARTs. Since we RX/TX data
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via file streams, we can't simulate modem control lines coming from the
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via file streams, we can't simulate modem control lines coming from the
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DCE and similar details of communication with the DCE.
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DCE and similar details of communication with the DCE.
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This simulated UART device is intended for basic UART device driver
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This simulated UART device is intended for basic UART device driver
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verification. From device driver perspective this device looks like a
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verification. From device driver perspective this device looks like a
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regular UART but never reports and modem control lines changes (the
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regular UART but never reports and modem control lines changes (the
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only DCE responses are incoming characters from the file stream).
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only DCE responses are incoming characters from the file stream).
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*/
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*/
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#include <stdlib.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdio.h>
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#include <string.h>
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#include <string.h>
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#include "abstract.h"
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#include "abstract.h"
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#include "16450.h"
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#include "16450.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "pic.h"
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#include "pic.h"
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static struct dev_16450 uarts[NR_UARTS];
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static struct dev_16450 uarts[NR_UARTS];
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static int thre_int;
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static int thre_int;
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/* Number of clock cycles (one clock cycle is one call to the uart_clock())
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/* Number of clock cycles (one clock cycle is one call to the uart_clock())
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before a single character is transmitted or received. */
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before a single character is transmitted or received. */
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static void set_char_clks(int uartchip)
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static void set_char_clks(int uartchip)
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{
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{
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int bauds_per_char = 0;
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int bauds_per_char = 0;
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uarts[uartchip].char_clks = (uarts[uartchip].regs.dlh << 8)
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uarts[uartchip].char_clks = (uarts[uartchip].regs.dlh << 8)
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+ uarts[uartchip].regs.dll;
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+ uarts[uartchip].regs.dll;
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if (uarts[uartchip].regs.lcr & UART_LCR_PARITY)
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if (uarts[uartchip].regs.lcr & UART_LCR_PARITY)
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bauds_per_char++;
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bauds_per_char++;
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if (uarts[uartchip].regs.lcr & UART_LCR_STOP)
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if (uarts[uartchip].regs.lcr & UART_LCR_STOP)
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bauds_per_char += 2;
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bauds_per_char += 2;
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else
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else
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bauds_per_char++;
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bauds_per_char++;
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bauds_per_char += (5 + (uarts[uartchip].regs.lcr & 0x2));
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bauds_per_char += (5 + (uarts[uartchip].regs.lcr & 0x2));
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uarts[uartchip].char_clks *= bauds_per_char;
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uarts[uartchip].char_clks *= bauds_per_char;
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}
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}
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/* Set a specific UART register with value. */
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/* Set a specific UART register with value. */
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void uart_write_byte(unsigned long addr, unsigned long value)
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void uart_write_byte(unsigned long addr, unsigned long value)
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{
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{
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int chipsel;
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int chipsel;
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debug("uart_write_byte(%x,%02x)\n", addr, (unsigned)value);
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debug("uart_write_byte(%x,%02x)\n", addr, (unsigned)value);
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for(chipsel = 0; chipsel < NR_UARTS; chipsel++)
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for(chipsel = 0; chipsel < NR_UARTS; chipsel++)
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if ((addr & ~(UART_ADDR_SPACE-1)) == uarts[chipsel].baseaddr)
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if ((addr & ~(UART_ADDR_SPACE-1)) == uarts[chipsel].baseaddr)
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break;
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break;
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else if (chipsel == NR_UARTS)
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else if (chipsel == NR_UARTS)
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return;
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return;
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if (uarts[chipsel].regs.lcr & UART_LCR_DLAB) {
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if (uarts[chipsel].regs.lcr & UART_LCR_DLAB) {
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switch (addr % UART_ADDR_SPACE) {
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switch (addr % UART_ADDR_SPACE) {
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case UART_DLL:
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case UART_DLL:
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uarts[chipsel].regs.dll = value;
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uarts[chipsel].regs.dll = value;
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break;
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break;
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case UART_DLH:
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case UART_DLH:
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uarts[chipsel].regs.dlh = value;
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uarts[chipsel].regs.dlh = value;
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break;
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break;
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case UART_LCR:
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case UART_LCR:
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uarts[chipsel].regs.lcr = value & UART_VALID_LCR;
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uarts[chipsel].regs.lcr = value & UART_VALID_LCR;
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break;
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break;
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default:
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default:
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debug("write out of range (addr %x, DLAB=1)\n", addr);
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debug("write out of range (addr %x, DLAB=1)\n", addr);
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}
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}
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set_char_clks(chipsel);
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set_char_clks(chipsel);
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return;
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return;
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}
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}
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switch (addr % UART_ADDR_SPACE) {
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switch (addr % UART_ADDR_SPACE) {
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case UART_TXBUF:
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case UART_TXBUF:
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uarts[chipsel].regs.txbuf = value;
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uarts[chipsel].regs.txbuf = value;
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uarts[chipsel].istat.txbuf = FULL;
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uarts[chipsel].istat.txbuf = FULL;
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uarts[chipsel].regs.lsr &= ~UART_LSR_TXBUFE;
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uarts[chipsel].regs.lsr &= ~UART_LSR_TXBUFE;
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uarts[chipsel].regs.lsr &= ~UART_LSR_TXSERE;
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uarts[chipsel].regs.lsr &= ~UART_LSR_TXSERE;
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uarts[chipsel].istat.thre_int = 0;
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uarts[chipsel].istat.thre_int = 0;
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break;
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break;
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case UART_IER:
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case UART_IER:
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uarts[chipsel].regs.ier = value & UART_VALID_IER;
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uarts[chipsel].regs.ier = value & UART_VALID_IER;
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break;
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break;
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case UART_LCR:
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case UART_LCR:
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uarts[chipsel].regs.lcr = value & UART_VALID_LCR;
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uarts[chipsel].regs.lcr = value & UART_VALID_LCR;
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break;
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break;
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case UART_MCR:
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case UART_MCR:
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uarts[chipsel].regs.mcr = value & UART_VALID_MCR;
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uarts[chipsel].regs.mcr = value & UART_VALID_MCR;
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break;
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break;
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case UART_SCR:
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case UART_SCR:
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uarts[chipsel].regs.scr = value;
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uarts[chipsel].regs.scr = value;
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break;
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break;
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default:
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default:
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debug("write out of range (addr %x)\n", addr);
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debug("write out of range (addr %x)\n", addr);
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}
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}
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set_char_clks(chipsel);
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set_char_clks(chipsel);
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return;
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return;
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}
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}
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/* Read a specific UART register. */
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/* Read a specific UART register. */
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unsigned long uart_read_byte(unsigned long addr)
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unsigned long uart_read_byte(unsigned long addr)
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{
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{
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unsigned char value = 0;
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unsigned char value = 0;
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int chipsel;
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int chipsel;
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debug("uart_read_byte(%x)\n", addr);
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debug("uart_read_byte(%x)\n", addr);
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for(chipsel = 0; chipsel < NR_UARTS; chipsel++)
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for(chipsel = 0; chipsel < NR_UARTS; chipsel++)
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if ((addr & ~(UART_ADDR_SPACE-1)) == uarts[chipsel].baseaddr)
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if ((addr & ~(UART_ADDR_SPACE-1)) == uarts[chipsel].baseaddr)
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break;
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break;
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else if (chipsel == NR_UARTS)
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else if (chipsel == NR_UARTS)
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return 0;
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return 0;
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if (uarts[chipsel].regs.lcr & UART_LCR_DLAB) {
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if (uarts[chipsel].regs.lcr & UART_LCR_DLAB) {
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switch (addr % UART_ADDR_SPACE) {
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switch (addr % UART_ADDR_SPACE) {
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case UART_DLL:
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case UART_DLL:
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value = uarts[chipsel].regs.dll;
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value = uarts[chipsel].regs.dll;
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break;
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break;
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case UART_DLH:
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case UART_DLH:
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value = uarts[chipsel].regs.dlh;
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value = uarts[chipsel].regs.dlh;
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break;
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break;
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default:
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default:
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debug("read out of range (addr %x, DLAB=1)\n", addr);
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debug("read out of range (addr %x, DLAB=1)\n", addr);
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}
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}
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return value;
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return value;
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}
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}
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switch (addr % UART_ADDR_SPACE) {
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switch (addr % UART_ADDR_SPACE) {
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case UART_RXBUF:
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case UART_RXBUF:
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value = uarts[chipsel].regs.rxbuf;
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value = uarts[chipsel].regs.rxbuf;
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uarts[chipsel].istat.rxbuf = EMPTY;
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uarts[chipsel].istat.rxbuf = EMPTY;
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uarts[chipsel].regs.lsr &= ~UART_LSR_RDRDY;
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uarts[chipsel].regs.lsr &= ~UART_LSR_RDRDY;
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break;
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break;
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case UART_IER:
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case UART_IER:
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value = uarts[chipsel].regs.ier & UART_VALID_IER;
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value = uarts[chipsel].regs.ier & UART_VALID_IER;
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break;
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break;
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case UART_IIR:
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case UART_IIR:
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value = uarts[chipsel].regs.iir & UART_VALID_IIR;
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value = uarts[chipsel].regs.iir & UART_VALID_IIR;
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uarts[chipsel].istat.thre_int = 0;
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uarts[chipsel].istat.thre_int = 0;
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break;
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break;
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case UART_LCR:
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case UART_LCR:
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value = uarts[chipsel].regs.lcr & UART_VALID_LCR;
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value = uarts[chipsel].regs.lcr & UART_VALID_LCR;
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break;
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break;
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case UART_MCR:
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case UART_MCR:
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value = uarts[chipsel].regs.mcr & UART_VALID_MCR;
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value = uarts[chipsel].regs.mcr & UART_VALID_MCR;
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break;
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break;
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case UART_LSR:
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case UART_LSR:
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value = uarts[chipsel].regs.lsr & UART_VALID_LSR;
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value = uarts[chipsel].regs.lsr & UART_VALID_LSR;
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uarts[chipsel].regs.lsr &=
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uarts[chipsel].regs.lsr &=
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~(UART_LSR_OVRRUN | UART_LSR_PARITY
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~(UART_LSR_OVRRUN | UART_LSR_PARITY
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| UART_LSR_FRAME | UART_LSR_BREAK);
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| UART_LSR_FRAME | UART_LSR_BREAK);
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break;
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break;
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case UART_MSR:
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case UART_MSR:
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value = uarts[chipsel].regs.msr & UART_VALID_MSR;
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value = uarts[chipsel].regs.msr & UART_VALID_MSR;
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uarts[chipsel].regs.msr = 0;
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uarts[chipsel].regs.msr = 0;
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break;
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break;
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case UART_SCR:
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case UART_SCR:
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value = uarts[chipsel].regs.scr;
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value = uarts[chipsel].regs.scr;
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break;
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break;
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default:
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default:
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debug("read out of range (addr %x)\n", addr);
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debug("read out of range (addr %x)\n", addr);
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}
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}
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return value;
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return value;
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}
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}
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/* Reset. It initializes all registers of all UART devices to zero values,
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/* Reset. It initializes all registers of all UART devices to zero values,
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(re)opens all RX/TX file streams and places devices in memory address
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(re)opens all RX/TX file streams and places devices in memory address
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space. */
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space. */
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void uart_reset()
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void uart_reset()
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{
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{
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int i;
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int i;
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printf("Resetting %u UART(s).\n", NR_UARTS);
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printf("Resetting %u UART(s).\n", NR_UARTS);
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memset(uarts, 0, sizeof(uarts));
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memset(uarts, 0, sizeof(uarts));
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for(i = 0; i < NR_UARTS; i++)
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for(i = 0; i < NR_UARTS; i++)
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if (config.uarts[i].txfile) { /* MM: Try to create stream. */
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if (config.uarts[i].txfile) { /* MM: Try to create stream. */
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if (!(uarts[i].rxfs = fopen(config.uarts[i].rxfile, "r"))
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if (!(uarts[i].rxfs = fopen(config.uarts[i].rxfile, "r"))
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&& !(uarts[i].rxfs = fopen(config.uarts[i].rxfile, "r+"))) {
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&& !(uarts[i].rxfs = fopen(config.uarts[i].rxfile, "r+"))) {
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printf("UART%d has problems with RX file stream.\n", i);
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printf("UART%d has problems with RX file stream.\n", i);
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continue;
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continue;
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}
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}
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uarts[i].txfs = fopen(config.uarts[i].txfile, "a");
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uarts[i].txfs = fopen(config.uarts[i].txfile, "a");
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uarts[i].baseaddr = config.uarts[i].baseaddr;
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uarts[i].baseaddr = config.uarts[i].baseaddr;
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if (uarts[i].txfs && uarts[i].txfs) {
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if (uarts[i].rxfs && uarts[i].txfs) {
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printf("UART%d at 0x%.8x uses ", i, uarts[i].baseaddr);
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printf("UART%d at 0x%.8x uses ", i, uarts[i].baseaddr);
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printf("%s for RX and %s for TX.\n", config.uarts[i].rxfile, config.uarts[i].txfile);
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printf("%s for RX and %s for TX.\n", config.uarts[i].rxfile, config.uarts[i].txfile);
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} else
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} else
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printf("UART%d has problems with TX file stream.\n", i);
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printf("UART%d has problems with TX file stream.\n", i);
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register_memoryarea(uarts[i].baseaddr, UART_ADDR_SPACE, 1, uart_read_byte, uart_write_byte, 0);
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register_memoryarea(uarts[i].baseaddr, UART_ADDR_SPACE, 1, uart_read_byte, uart_write_byte, 0);
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}
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}
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}
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}
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/* Simulation hook. Must be called every clock cycle to simulate all UART
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/* Simulation hook. Must be called every clock cycle to simulate all UART
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devices. It does internal functional UART simulation. */
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devices. It does internal functional UART simulation. */
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void uart_clock()
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void uart_clock()
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{
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{
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int i, retval;
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int i, retval;
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for(i = 0; i < NR_UARTS; i++) {
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for(i = 0; i < NR_UARTS; i++) {
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if (!uarts[i].txfs) {
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if (!uarts[i].txfs) {
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continue;
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continue;
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}
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}
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/* Transmit */
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/* Transmit */
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if (uarts[i].istat.txser == EMPTY) {
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if (uarts[i].istat.txser == EMPTY) {
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uarts[i].regs.lsr |= UART_LSR_TXBUFE;
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uarts[i].regs.lsr |= UART_LSR_TXBUFE;
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if (uarts[i].istat.txbuf == FULL) {
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if (uarts[i].istat.txbuf == FULL) {
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uarts[i].iregs.txser = uarts[i].regs.txbuf;
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uarts[i].iregs.txser = uarts[i].regs.txbuf;
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uarts[i].istat.txser = FULL;
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uarts[i].istat.txser = FULL;
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uarts[i].istat.txbuf = EMPTY;
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uarts[i].istat.txbuf = EMPTY;
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uarts[i].regs.lsr &= ~UART_LSR_TXSERE;
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uarts[i].regs.lsr &= ~UART_LSR_TXSERE;
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uarts[i].istat.thre_int = 1;
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uarts[i].istat.thre_int = 1;
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} else
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} else
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uarts[i].regs.lsr |= UART_LSR_TXSERE;
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uarts[i].regs.lsr |= UART_LSR_TXSERE;
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} else if (uarts[i].char_clks == uarts[i].istat.txser_clks++) {
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} else if (uarts[i].char_clks == uarts[i].istat.txser_clks++) {
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debug("TX \'%c\' via UART%d...\n", uarts[i].iregs.txser, i);
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debug("TX \'%c\' via UART%d...\n", uarts[i].iregs.txser, i);
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if (uarts[i].regs.mcr & UART_MCR_LOOP)
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if (uarts[i].regs.mcr & UART_MCR_LOOP)
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uarts[i].iregs.loopback = uarts[i].iregs.txser;
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uarts[i].iregs.loopback = uarts[i].iregs.txser;
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else {
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else {
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fputc((int)uarts[i].iregs.txser, uarts[i].txfs);
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fputc((int)uarts[i].iregs.txser, uarts[i].txfs);
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fflush(uarts[i].txfs);
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fflush(uarts[i].txfs);
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}
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}
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uarts[i].istat.txser = EMPTY;
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uarts[i].istat.txser = EMPTY;
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uarts[i].istat.txser_clks = 0;
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uarts[i].istat.txser_clks = 0;
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}
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}
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/* Receive */
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/* Receive */
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if (uarts[i].istat.rxser == EMPTY)
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if (uarts[i].istat.rxser == EMPTY)
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uarts[i].istat.rxser = FULL;
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uarts[i].istat.rxser = FULL;
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else if (uarts[i].char_clks == uarts[i].istat.rxser_clks++) {
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else if (uarts[i].char_clks == uarts[i].istat.rxser_clks++) {
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debug("Receiving via UART%d...\n", i);
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debug("Receiving via UART%d...\n", i);
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if (uarts[i].regs.mcr & UART_MCR_LOOP)
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if (uarts[i].regs.mcr & UART_MCR_LOOP)
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uarts[i].iregs.rxser = uarts[i].iregs.loopback;
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uarts[i].iregs.rxser = uarts[i].iregs.loopback;
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else if((retval = fgetc(uarts[i].rxfs)) != EOF) {
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else if((retval = fgetc(uarts[i].rxfs)) != EOF) {
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uarts[i].iregs.rxser = (char)retval;
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uarts[i].iregs.rxser = (char)retval;
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if (uarts[i].istat.rxbuf == FULL)
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if (uarts[i].istat.rxbuf == FULL)
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uarts[i].regs.lsr |= UART_LSR_OVRRUN;
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uarts[i].regs.lsr |= UART_LSR_OVRRUN;
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uarts[i].regs.lsr |= UART_LSR_RDRDY;
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uarts[i].regs.lsr |= UART_LSR_RDRDY;
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uarts[i].regs.rxbuf = uarts[i].iregs.rxser;
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uarts[i].regs.rxbuf = uarts[i].iregs.rxser;
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uarts[i].istat.rxbuf = FULL;
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uarts[i].istat.rxbuf = FULL;
|
}
|
}
|
uarts[i].istat.rxser = EMPTY;
|
uarts[i].istat.rxser = EMPTY;
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uarts[i].istat.rxser_clks = 0;
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uarts[i].istat.rxser_clks = 0;
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}
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}
|
|
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/* Loopback */
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/* Loopback */
|
if (uarts[i].regs.mcr & UART_MCR_LOOP) {
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if (uarts[i].regs.mcr & UART_MCR_LOOP) {
|
debug("uart_clock: Loopback\n");
|
debug("uart_clock: Loopback\n");
|
if ((uarts[i].regs.mcr & UART_MCR_AUX2) !=
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if ((uarts[i].regs.mcr & UART_MCR_AUX2) !=
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((uarts[i].regs.msr & UART_MSR_DCD) >> 4))
|
((uarts[i].regs.msr & UART_MSR_DCD) >> 4))
|
uarts[i].regs.msr |= UART_MSR_DDCD;
|
uarts[i].regs.msr |= UART_MSR_DDCD;
|
if ((uarts[i].regs.mcr & UART_MCR_AUX1) <
|
if ((uarts[i].regs.mcr & UART_MCR_AUX1) <
|
((uarts[i].regs.msr & UART_MSR_RI) >> 4))
|
((uarts[i].regs.msr & UART_MSR_RI) >> 4))
|
uarts[i].regs.msr |= UART_MSR_TERI;
|
uarts[i].regs.msr |= UART_MSR_TERI;
|
if ((uarts[i].regs.mcr & UART_MCR_RTS) !=
|
if ((uarts[i].regs.mcr & UART_MCR_RTS) !=
|
((uarts[i].regs.msr & UART_MSR_CTS) >> 3))
|
((uarts[i].regs.msr & UART_MSR_CTS) >> 3))
|
uarts[i].regs.msr |= UART_MSR_DCTS;
|
uarts[i].regs.msr |= UART_MSR_DCTS;
|
if ((uarts[i].regs.mcr & UART_MCR_DTR) !=
|
if ((uarts[i].regs.mcr & UART_MCR_DTR) !=
|
((uarts[i].regs.msr & UART_MSR_DSR) >> 5))
|
((uarts[i].regs.msr & UART_MSR_DSR) >> 5))
|
uarts[i].regs.msr |= UART_MSR_DDSR;
|
uarts[i].regs.msr |= UART_MSR_DDSR;
|
uarts[i].regs.msr &= ~(UART_MSR_DCD | UART_MSR_RI
|
uarts[i].regs.msr &= ~(UART_MSR_DCD | UART_MSR_RI
|
| UART_MSR_DSR | UART_MSR_CTS);
|
| UART_MSR_DSR | UART_MSR_CTS);
|
uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_AUX2) << 4);
|
uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_AUX2) << 4);
|
uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_AUX1) << 4);
|
uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_AUX1) << 4);
|
uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_RTS) << 3);
|
uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_RTS) << 3);
|
uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_DTR) << 5);
|
uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_DTR) << 5);
|
}
|
}
|
|
|
/* Interrupt detection in proper priority order. */
|
/* Interrupt detection in proper priority order. */
|
uarts[i].regs.iir = UART_IIR_NO_INT;
|
uarts[i].regs.iir = UART_IIR_NO_INT;
|
if (uarts[i].regs.ier & UART_IER_RLSI &&
|
if (uarts[i].regs.ier & UART_IER_RLSI &&
|
uarts[i].regs.lsr & (UART_LSR_OVRRUN | UART_LSR_PARITY
|
uarts[i].regs.lsr & (UART_LSR_OVRRUN | UART_LSR_PARITY
|
| UART_LSR_FRAME | UART_LSR_BREAK)) {
|
| UART_LSR_FRAME | UART_LSR_BREAK)) {
|
uarts[i].regs.iir = UART_IIR_RLSI;
|
uarts[i].regs.iir = UART_IIR_RLSI;
|
}
|
}
|
else if (uarts[i].regs.ier & UART_IER_RDI &&
|
else if (uarts[i].regs.ier & UART_IER_RDI &&
|
uarts[i].regs.lsr & UART_LSR_RDRDY) {
|
uarts[i].regs.lsr & UART_LSR_RDRDY) {
|
uarts[i].regs.iir = UART_IIR_RDI;
|
uarts[i].regs.iir = UART_IIR_RDI;
|
}
|
}
|
else if (uarts[i].regs.ier & UART_IER_THRI &&
|
else if (uarts[i].regs.ier & UART_IER_THRI &&
|
uarts[i].regs.lsr & UART_LSR_TXBUFE &&
|
uarts[i].regs.lsr & UART_LSR_TXBUFE &&
|
uarts[i].istat.thre_int == 1) {
|
uarts[i].istat.thre_int == 1) {
|
uarts[i].regs.iir = UART_IIR_THRI;
|
uarts[i].regs.iir = UART_IIR_THRI;
|
}
|
}
|
else if (uarts[i].regs.ier & UART_IER_MSI &&
|
else if (uarts[i].regs.ier & UART_IER_MSI &&
|
uarts[i].regs.msr & (UART_MSR_DCTS | UART_MSR_DDSR
|
uarts[i].regs.msr & (UART_MSR_DCTS | UART_MSR_DDSR
|
| UART_MSR_TERI | UART_MSR_DDCD)) {
|
| UART_MSR_TERI | UART_MSR_DDCD)) {
|
uarts[i].regs.iir = UART_IIR_MSI;
|
uarts[i].regs.iir = UART_IIR_MSI;
|
}
|
}
|
if (!(uarts[i].regs.iir & UART_IIR_NO_INT))
|
if (!(uarts[i].regs.iir & UART_IIR_NO_INT))
|
report_interrupt(INT_UART);
|
report_interrupt(INT_UART);
|
}
|
}
|
}
|
}
|
|
|
/* Print register values on stdout. */
|
/* Print register values on stdout. */
|
void uart_status()
|
void uart_status()
|
{
|
{
|
int i;
|
int i;
|
|
|
for(i = 0; i < NR_UARTS; i++) {
|
for(i = 0; i < NR_UARTS; i++) {
|
if ( !uarts[i].baseaddr )
|
if ( !uarts[i].baseaddr )
|
continue;
|
continue;
|
printf("\nUART%d visible registers at 0x%.8x:\n", i, uarts[i].baseaddr);
|
printf("\nUART%d visible registers at 0x%.8x:\n", i, uarts[i].baseaddr);
|
printf("RXBUF: %.2x TXBUF: %.2x\n", uarts[i].regs.rxbuf, uarts[i].regs.txbuf);
|
printf("RXBUF: %.2x TXBUF: %.2x\n", uarts[i].regs.rxbuf, uarts[i].regs.txbuf);
|
printf("DLL : %.2x DLH : %.2x\n", uarts[i].regs.dll, uarts[i].regs.dlh);
|
printf("DLL : %.2x DLH : %.2x\n", uarts[i].regs.dll, uarts[i].regs.dlh);
|
printf("IER : %.2x IIR : %.2x\n", uarts[i].regs.ier, uarts[i].regs.iir);
|
printf("IER : %.2x IIR : %.2x\n", uarts[i].regs.ier, uarts[i].regs.iir);
|
printf("LCR : %.2x MCR : %.2x\n", uarts[i].regs.lcr, uarts[i].regs.mcr);
|
printf("LCR : %.2x MCR : %.2x\n", uarts[i].regs.lcr, uarts[i].regs.mcr);
|
printf("LSR : %.2x MSR : %.2x\n", uarts[i].regs.lsr, uarts[i].regs.msr);
|
printf("LSR : %.2x MSR : %.2x\n", uarts[i].regs.lsr, uarts[i].regs.msr);
|
printf("SCR : %.2x\n", uarts[i].regs.scr);
|
printf("SCR : %.2x\n", uarts[i].regs.scr);
|
|
|
printf("\nInternal registers (sim debug):\n");
|
printf("\nInternal registers (sim debug):\n");
|
printf("RXSER: %.2x TXSER: %.2x\n", uarts[i].iregs.rxser, uarts[i].iregs.txser);
|
printf("RXSER: %.2x TXSER: %.2x\n", uarts[i].iregs.rxser, uarts[i].iregs.txser);
|
|
|
printf("\nInternal status (sim debug):\n");
|
printf("\nInternal status (sim debug):\n");
|
printf("char_clks: %d\n", uarts[i].char_clks);
|
printf("char_clks: %d\n", uarts[i].char_clks);
|
printf("rxser_clks: %d txser_clks: %d\n", uarts[i].istat.rxser_clks, uarts[i].istat.txser_clks);
|
printf("rxser_clks: %d txser_clks: %d\n", uarts[i].istat.rxser_clks, uarts[i].istat.txser_clks);
|
printf("rxser: %d txser: %d\n", uarts[i].istat.rxser, uarts[i].istat.txser);
|
printf("rxser: %d txser: %d\n", uarts[i].istat.rxser, uarts[i].istat.txser);
|
printf("rxbuf: %d txbuf: %d\n", uarts[i].istat.rxbuf, uarts[i].istat.txbuf);
|
printf("rxbuf: %d txbuf: %d\n", uarts[i].istat.rxbuf, uarts[i].istat.txbuf);
|
|
|
printf("RX fs: %p TX fs: %p\n\n", uarts[i].rxfs, uarts[i].txfs);
|
printf("RX fs: %p TX fs: %p\n\n", uarts[i].rxfs, uarts[i].txfs);
|
}
|
}
|
}
|
}
|
|
|
