/* except.c -- Simulation of OR1K exceptions
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/* except.c -- Simulation of OR1K exceptions
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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#include <stdlib.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdio.h>
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#include <string.h>
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#include <string.h>
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#include "config.h"
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#include "config.h"
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#ifdef HAVE_INTTYPES_H
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#ifdef HAVE_INTTYPES_H
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#include <inttypes.h>
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#include <inttypes.h>
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#endif
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#endif
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#include "port.h"
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#include "port.h"
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#include "arch.h"
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#include "arch.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "except.h"
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#include "except.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "debug_unit.h"
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#include "debug_unit.h"
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#include "opcode/or32.h"
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#include "opcode/or32.h"
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#include "spr_defs.h"
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#include "spr_defs.h"
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#include "execute.h"
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#include "execute.h"
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#include "sprs.h"
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#include "sprs.h"
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#if DYNAMIC_EXECUTION
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#if DYNAMIC_EXECUTION
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#include "sched.h"
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#include "sched.h"
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#include "rec_i386.h"
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#include "rec_i386.h"
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#include "op_support.h"
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#include "op_support.h"
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#endif
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#endif
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extern oraddr_t pcprev;
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extern oraddr_t pcprev;
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int except_pending = 0;
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int except_pending = 0;
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static const char *except_names[] = {
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static const char *except_names[] = {
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NULL,
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NULL,
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"Reset",
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"Reset",
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"Bus Error",
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"Bus Error",
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"Data Page Fault",
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"Data Page Fault",
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"Insn Page Fault",
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"Insn Page Fault",
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"Tick timer",
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"Tick timer",
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"Alignment",
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"Alignment",
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"Illegal instruction",
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"Illegal instruction",
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"Interrupt",
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"Interrupt",
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"Data TLB Miss",
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"Data TLB Miss",
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"Insn TLB Miss",
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"Insn TLB Miss",
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"Range",
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"Range",
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"System Call",
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"System Call",
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"Trap" };
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"Trap" };
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const char *except_name(oraddr_t except)
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const char *except_name(oraddr_t except)
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{
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{
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return except_names[except >> 8];
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return except_names[except >> 8];
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}
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}
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#if DYNAMIC_EXECUTION
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#if DYNAMIC_EXECUTION
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/* FIXME: Remove the need for this */
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/* FIXME: Remove the need for this */
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/* This is needed because immu_translate can be called from do_rfe and do_jump
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/* This is needed because immu_translate can be called from do_rfe and do_jump
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* in which case the scheduler does not need to get run. immu_translate can also
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* in which case the scheduler does not need to get run. immu_translate can also
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* be called from mtspr in which case the exceptions that it generates happen
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* be called from mtspr in which case the exceptions that it generates happen
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* during an instruction and the scheduler needs to get run. */
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* during an instruction and the scheduler needs to get run. */
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int immu_ex_from_insn = 0;
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int immu_ex_from_insn = 0;
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#endif
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#endif
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/* Asserts OR1K exception. */
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/* Asserts OR1K exception. */
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void except_handle(oraddr_t except, oraddr_t ea)
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void except_handle(oraddr_t except, oraddr_t ea)
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{
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{
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oraddr_t except_vector;
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oraddr_t except_vector;
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if(debug_ignore_exception (except))
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if(debug_ignore_exception (except))
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return;
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return;
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#if !(DYNAMIC_EXECUTION)
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#if !(DYNAMIC_EXECUTION)
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/* In the dynamic recompiler, this function never returns, so this is not
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/* In the dynamic recompiler, this function never returns, so this is not
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* needed. Ofcourse we could set it anyway, but then all code that checks
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* needed. Ofcourse we could set it anyway, but then all code that checks
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* this variable would break, since it is never reset */
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* this variable would break, since it is never reset */
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except_pending = 1;
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except_pending = 1;
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#endif
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#endif
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if (config.sim.verbose)
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if (config.sim.verbose)
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PRINTF("Exception 0x%"PRIxADDR" (%s) at 0x%"PRIxADDR", EA: 0x%"PRIxADDR
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PRINTF("Exception 0x%"PRIxADDR" (%s) at 0x%"PRIxADDR", EA: 0x%"PRIxADDR
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", ppc: 0x%"PRIxADDR", npc: 0x%"PRIxADDR", dpc: 0x%"PRIxADDR
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", ppc: 0x%"PRIxADDR", npc: 0x%"PRIxADDR", dpc: 0x%"PRIxADDR
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", cycles %lld, #%lld\n",
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", cycles %lld, #%lld\n",
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except, except_name(except), pcprev, ea, cpu_state.pc, pcnext,
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except, except_name(except), pcprev, ea, cpu_state.pc, pcnext,
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cpu_state.pc_delay, runtime.sim.cycles, runtime.cpu.instructions);
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cpu_state.pc_delay, runtime.sim.cycles, runtime.cpu.instructions);
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except_vector = except + (testsprbits (SPR_SR, SPR_SR_EPH) ? 0xf0000000 : 0x00000000);
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except_vector = except + (testsprbits (SPR_SR, SPR_SR_EPH) ? 0xf0000000 : 0x00000000);
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#if !(DYNAMIC_EXECUTION)
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#if !(DYNAMIC_EXECUTION)
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pcnext = except_vector;
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pcnext = except_vector;
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#endif
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#endif
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cpu_state.sprs[SPR_EEAR_BASE] = ea;
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cpu_state.sprs[SPR_EEAR_BASE] = ea;
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cpu_state.sprs[SPR_ESR_BASE] = cpu_state.sprs[SPR_SR];
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cpu_state.sprs[SPR_ESR_BASE] = cpu_state.sprs[SPR_SR];
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_OVE; /* Disable overflow flag exception. */
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_OVE; /* Disable overflow flag exception. */
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cpu_state.sprs[SPR_SR] |= SPR_SR_SM; /* SUPV mode */
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cpu_state.sprs[SPR_SR] |= SPR_SR_SM; /* SUPV mode */
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cpu_state.sprs[SPR_SR] &= ~(SPR_SR_IEE | SPR_SR_TEE); /* Disable interrupts. */
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cpu_state.sprs[SPR_SR] &= ~(SPR_SR_IEE | SPR_SR_TEE); /* Disable interrupts. */
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/* Address translation is always disabled when starting exception. */
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/* Address translation is always disabled when starting exception. */
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_DME;
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_DME;
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#if DYNAMIC_EXECUTION
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#if DYNAMIC_EXECUTION
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/* If we were called from do_scheduler and there were more jobs scheduled to
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/* If we were called from do_scheduler and there were more jobs scheduled to
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* run after this, they won't run unless the following call is made since this
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* run after this, they won't run unless the following call is made since this
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* function never returns. (If we weren't called from do_scheduler, then the
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* function never returns. (If we weren't called from do_scheduler, then the
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* job at the head of the queue will still have some time remaining) */
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* job at the head of the queue will still have some time remaining) */
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if(scheduler.job_queue->time <= 0)
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if(scheduler.job_queue->time <= 0)
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do_scheduler();
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do_scheduler();
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#endif
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#endif
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switch(except) {
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switch(except) {
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/* EPCR is irrelevent */
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/* EPCR is irrelevent */
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case EXCEPT_RESET:
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case EXCEPT_RESET:
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break;
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break;
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/* EPCR is loaded with address of instruction that caused the exception */
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/* EPCR is loaded with address of instruction that caused the exception */
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case EXCEPT_ITLBMISS:
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case EXCEPT_ITLBMISS:
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case EXCEPT_IPF:
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case EXCEPT_IPF:
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#if DYNAMIC_EXECUTION
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#if DYNAMIC_EXECUTION
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/* In immu_translate except_handle is called with except_handle(..., virtaddr) */
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/* In immu_translate except_handle is called with except_handle(..., virtaddr) */
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/* Add the immu miss delay to the cycle counter */
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/* Add the immu miss delay to the cycle counter */
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if(!immu_ex_from_insn)
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if(!immu_ex_from_insn)
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mtspr(SPR_EPCR_BASE, get_pc() - (cpu_state.delay_insn ? 4 : 0));
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mtspr(SPR_EPCR_BASE, get_pc() - (cpu_state.delay_insn ? 4 : 0));
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else
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else
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/* This exception came from an l.mtspr instruction in which case the pc
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/* This exception came from an l.mtspr instruction in which case the pc
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* points to the l.mtspr instruction when in acutal fact, it is the next
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* points to the l.mtspr instruction when in acutal fact, it is the next
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* instruction that would have faulted/missed. ea is used instead of
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* instruction that would have faulted/missed. ea is used instead of
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* cpu_state.pc + 4 because in the event that the l.mtspr instruction is
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* cpu_state.pc + 4 because in the event that the l.mtspr instruction is
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* in the delay slot of a page local jump the fault must happen on the
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* in the delay slot of a page local jump the fault must happen on the
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* instruction that was jumped to. This is handled in recheck_immu. */
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* instruction that was jumped to. This is handled in recheck_immu. */
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mtspr(SPR_EPCR_BASE, ea);
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mtspr(SPR_EPCR_BASE, ea);
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run_sched_out_of_line(immu_ex_from_insn);
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run_sched_out_of_line(immu_ex_from_insn);
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immu_ex_from_insn = 0;
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immu_ex_from_insn = 0;
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break;
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break;
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#endif
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#endif
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/* All these exceptions happen during a simulated instruction */
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/* All these exceptions happen during a simulated instruction */
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case EXCEPT_BUSERR:
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case EXCEPT_BUSERR:
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case EXCEPT_DPF:
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case EXCEPT_DPF:
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case EXCEPT_ALIGN:
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case EXCEPT_ALIGN:
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case EXCEPT_ILLEGAL:
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case EXCEPT_ILLEGAL:
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case EXCEPT_DTLBMISS:
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case EXCEPT_DTLBMISS:
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case EXCEPT_RANGE:
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case EXCEPT_RANGE:
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case EXCEPT_TRAP:
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case EXCEPT_TRAP:
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#if DYNAMIC_EXECUTION
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#if DYNAMIC_EXECUTION
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/* Since these exceptions happen during a simulated instruction and this
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/* Since these exceptions happen during a simulated instruction and this
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* function jumps out to the exception vector the scheduler would never have
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* function jumps out to the exception vector the scheduler would never have
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* a chance to run, therefore run it now */
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* a chance to run, therefore run it now */
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run_sched_out_of_line(1);
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run_sched_out_of_line(1);
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#endif
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#endif
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mtspr(SPR_EPCR_BASE, cpu_state.pc - (cpu_state.delay_insn ? 4 : 0));
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mtspr(SPR_EPCR_BASE, cpu_state.pc - (cpu_state.delay_insn ? 4 : 0));
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break;
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break;
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/* EPCR is loaded with address of next not-yet-executed instruction */
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/* EPCR is loaded with address of next not-yet-executed instruction */
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case EXCEPT_SYSCALL:
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case EXCEPT_SYSCALL:
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mtspr(SPR_EPCR_BASE, (cpu_state.pc + 4) - (cpu_state.delay_insn ? 4 : 0));
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mtspr(SPR_EPCR_BASE, (cpu_state.pc + 4) - (cpu_state.delay_insn ? 4 : 0));
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break;
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break;
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/* These exceptions happen AFTER (or before) an instruction has been
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/* These exceptions happen AFTER (or before) an instruction has been
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* simulated, therefore the pc already points to the *next* instruction */
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* simulated, therefore the pc already points to the *next* instruction */
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case EXCEPT_TICK:
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case EXCEPT_TICK:
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case EXCEPT_INT:
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case EXCEPT_INT:
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mtspr(SPR_EPCR_BASE, cpu_state.pc - (cpu_state.delay_insn ? 4 : 0));
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mtspr(SPR_EPCR_BASE, cpu_state.pc - (cpu_state.delay_insn ? 4 : 0));
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#if !(DYNAMIC_EXECUTION)
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#if !(DYNAMIC_EXECUTION)
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/* If we don't update the pc now, then it will only happen *after* the next
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/* If we don't update the pc now, then it will only happen *after* the next
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* instruction (There would be serious problems if the next instruction just
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* instruction (There would be serious problems if the next instruction just
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* happens to be a branch), when it should happen NOW. */
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* happens to be a branch), when it should happen NOW. */
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cpu_state.pc = pcnext;
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cpu_state.pc = pcnext;
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pcnext += 4;
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pcnext += 4;
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#else
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#else
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/* except_handle() mucks around with the temporaries, which are in the state
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/* except_handle() mucks around with the temporaries, which are in the state
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* of the last instruction executed and not the next one, to which the pc
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* of the last instruction executed and not the next one, to which the pc
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* now points to */
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* now points to */
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cpu_state.pc -= 4;
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cpu_state.pc -= 4;
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#endif
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#endif
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break;
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break;
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}
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}
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/* Address trnaslation is here because run_sched_out_of_line calls
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/* Address trnaslation is here because run_sched_out_of_line calls
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* eval_insn_direct which checks out the immu for the address translation but
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* eval_insn_direct which checks out the immu for the address translation but
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* if it would be disabled above then there would be not much point... */
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* if it would be disabled above then there would be not much point... */
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_IME;
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_IME;
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/* Complex/simple execution strictly don't need this because of the
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/* Complex/simple execution strictly don't need this because of the
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* next_delay_insn thingy but in the dynamic execution modell that doesn't
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* next_delay_insn thingy but in the dynamic execution modell that doesn't
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* exist and thus cpu_state.insn_delay would stick in the exception handler
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* exist and thus cpu_state.insn_delay would stick in the exception handler
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* causeing grief if the first instruction of the exception handler is also in
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* causeing grief if the first instruction of the exception handler is also in
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* the delay slot of the previous instruction */
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* the delay slot of the previous instruction */
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cpu_state.delay_insn = 0;
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cpu_state.delay_insn = 0;
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#if DYNAMIC_EXECUTION
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#if DYNAMIC_EXECUTION
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/* Save the registers that are in the temporaries */
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/* Save the registers that are in the temporaries */
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if(!cpu_state.ts_current)
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if(!cpu_state.ts_current)
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upd_reg_from_t(cpu_state.pc);
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upd_reg_from_t(cpu_state.pc);
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cpu_state.pc = except_vector;
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cpu_state.pc = except_vector;
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cpu_state.ts_current = 0;
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cpu_state.ts_current = 0;
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jump_dyn_code(except_vector);
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jump_dyn_code(except_vector);
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#endif
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#endif
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}
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}
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