/* pic.c -- Simulation of OpenRISC 1000 programmable interrupt controller
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/* pic.c -- Simulation of OpenRISC 1000 programmable interrupt controller
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* This is functional simulation of OpenRISC 1000 architectural
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/* This is functional simulation of OpenRISC 1000 architectural
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programmable interrupt controller.
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programmable interrupt controller.
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*/
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*/
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#include <stdlib.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdio.h>
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#include <string.h>
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#include <string.h>
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#include "pic.h"
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#include "pic.h"
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#include "spr_defs.h"
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#include "spr_defs.h"
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#include "except.h"
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#include "except.h"
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#include "sprs.h"
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#include "sprs.h"
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extern int cont_run;
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extern int cont_run;
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/* Reset. It initializes PIC registers. */
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/* Reset. It initializes PIC registers. */
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void pic_reset()
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void pic_reset()
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{
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{
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printf("Resetting PIC.\n");
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printf("Resetting PIC.\n");
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mtspr(SPR_PICMR, 0);
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mtspr(SPR_PICMR, 0);
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mtspr(SPR_PICPR, 0);
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mtspr(SPR_PICPR, 0);
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mtspr(SPR_PICSR, 0);
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mtspr(SPR_PICSR, 0);
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}
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}
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/* Simulation hook. Must be called every clock cycle to simulate PIC
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/* Simulation hook. Must be called every clock cycle to simulate PIC
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It does internal functional PIC simulation. */
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It does internal functional PIC simulation. */
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inline void pic_clock()
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inline void pic_clock()
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{
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{
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unsigned long picsr;
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unsigned long picsr;
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unsigned long picpr;
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unsigned long picpr;
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unsigned long sr;
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unsigned long sr;
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/* CZ 020901: Someone had previously noted that this routine was
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/* CZ 020901: Someone had previously noted that this routine was
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wrong, and there were 2 sets of code, one commented out, and
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wrong, and there were 2 sets of code, one commented out, and
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both were broken. I have rewritten this so it works as I think
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both were broken. I have rewritten this so it works as I think
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it should. Someone needs to correct this if there is something
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it should. Someone needs to correct this if there is something
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I am missing... */
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I am missing... */
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/* From Sections 16.3 & 16.4, bits 0 & 1 are reserved */
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picsr = mfspr(SPR_PICSR) & 0xFFFFFFFC;
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picpr = mfspr(SPR_PICPR) & 0xFFFFFFFC;
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sr = mfspr(SPR_SR);
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sr = mfspr(SPR_SR);
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/* Don't do anything if interrupts not currently enabled */
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/* Don't do anything if interrupts not currently enabled */
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if((sr & (SPR_SR_EIR | SPR_SR_EXR)) != (SPR_SR_EIR | SPR_SR_EXR))
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if((sr & (SPR_SR_EIR | SPR_SR_EXR)) != (SPR_SR_EIR | SPR_SR_EXR))
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return;
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return;
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/* From Sections 16.3 & 16.4, bits 0 & 1 are reserved */
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picsr = mfspr(SPR_PICSR) & 0xFFFFFFFC;
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picpr = mfspr(SPR_PICPR) & 0xFFFFFFFC;
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if(picsr & picpr) /* Report High Priority Interrupts first */
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if(picsr & picpr) /* Report High Priority Interrupts first */
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except_handle(EXCEPT_HPINT, 0);
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except_handle(EXCEPT_HPINT, 0);
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else if(picsr) /* Report a Low Priority Interrupt otherwise */
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else if(picsr) /* Report a Low Priority Interrupt otherwise */
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except_handle(EXCEPT_LPINT, 0);
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except_handle(EXCEPT_LPINT, 0);
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#if 0 /* CZ -- both of these routines are broken */
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#if 0 /* CZ -- both of these routines are broken */
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/* SIMON: This is a bug */
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/* SIMON: This is a bug */
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/* if (picsr & picpr) {
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/* if (picsr & picpr) {
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if ((mfspr(SPR_SR) & (SPR_SR_EIR | SPR_SR_EXR)) == (SPR_SR_EIR | SPR_SR_EXR)
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if ((mfspr(SPR_SR) & (SPR_SR_EIR | SPR_SR_EXR)) == (SPR_SR_EIR | SPR_SR_EXR)
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)
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)
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except_handle(EXCEPT_HPINT, 0);
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except_handle(EXCEPT_HPINT, 0);
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} else
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} else
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if ((mfspr(SPR_SR) & (SPR_SR_EIR | SPR_SR_EXR)) == (SPR_SR_EIR | SPR_SR_EXR)
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if ((mfspr(SPR_SR) & (SPR_SR_EIR | SPR_SR_EXR)) == (SPR_SR_EIR | SPR_SR_EXR)
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)
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)
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except_handle(EXCEPT_LPINT, 0);
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except_handle(EXCEPT_LPINT, 0);
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*/
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*/
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if ((picsr & (SPR_SR_EIR | SPR_SR_EXR)) == (SPR_SR_EIR | SPR_SR_EXR)) {
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if ((picsr & (SPR_SR_EIR | SPR_SR_EXR)) == (SPR_SR_EIR | SPR_SR_EXR)) {
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if (picsr & picpr) {
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if (picsr & picpr) {
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except_handle(EXCEPT_HPINT, 0);
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except_handle(EXCEPT_HPINT, 0);
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} else if(picsr) {
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} else if(picsr) {
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except_handle(EXCEPT_LPINT, 0);
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except_handle(EXCEPT_LPINT, 0);
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}
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}
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}
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}
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#endif
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#endif
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}
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}
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/* Asserts interrupt to the PIC. */
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/* Asserts interrupt to the PIC. */
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void report_interrupt(int line)
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void report_interrupt(int line)
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{
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{
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setsprbits(SPR_PMR, SPR_PMR_DME, 0); /* Disable doze mode */
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setsprbits(SPR_PMR, SPR_PMR_DME, 0); /* Disable doze mode */
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setsprbits(SPR_PMR, SPR_PMR_SME, 0); /* Disable sleep mode */
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setsprbits(SPR_PMR, SPR_PMR_SME, 0); /* Disable sleep mode */
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debug(4, "Asserting interrupt %d.\n", line);
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debug(4, "Asserting interrupt %d.\n", line);
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if (getsprbit(SPR_PICMR, line) || line < 2)
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if (getsprbit(SPR_PICMR, line) || line < 2)
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setsprbit(SPR_PICSR, line, 1);
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setsprbit(SPR_PICSR, line, 1);
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}
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}
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