/* mc.c -- Simulation of Memory Controller
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/* mc.c -- Simulation of Memory Controller
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Copyright (C) 2001 by Marko Mlinar, markom@opencores.org
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Copyright (C) 2001 by Marko Mlinar, markom@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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*/
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/* Enable memory controller, via:
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/* Enable memory controller, via:
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section mc
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section mc
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enable = 1
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enable = 1
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POC = 0x13243545
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POC = 0x13243545
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end
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end
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Limitations:
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Limitations:
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- memory refresh is not simulated
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- memory refresh is not simulated
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*/
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*/
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#include <string.h>
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#include <string.h>
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#include "config.h"
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#include "config.h"
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#ifdef HAVE_INTTYPES_H
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#ifdef HAVE_INTTYPES_H
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#include <inttypes.h>
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#include <inttypes.h>
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#endif
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#endif
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#include "port.h"
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#include "port.h"
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#include "arch.h"
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#include "arch.h"
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#include "mc.h"
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#include "mc.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "debug.h"
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#include "debug.h"
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extern struct dev_memarea *dev_list;
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extern struct dev_memarea *dev_list;
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void set_csc_tms (int cs, unsigned long csc, unsigned long tms, struct mc *mc) {
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void set_csc_tms (int cs, unsigned long csc, unsigned long tms, struct mc *mc) {
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struct dev_memarea *mem_dev = dev_list;
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struct dev_memarea *mem_dev = dev_list;
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while (mem_dev) {
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while (mem_dev) {
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if (mem_dev->chip_select == cs) {
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if (mem_dev->chip_select == cs) {
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mem_dev->addr_mask = mc->ba_mask << 22;
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mem_dev->addr_mask = mc->ba_mask << 22;
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mem_dev->addr_compare = ((csc >> MC_CSC_SEL_OFFSET) /* & 0xff*/) << 22;
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mem_dev->addr_compare = ((csc >> MC_CSC_SEL_OFFSET) /* & 0xff*/) << 22;
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mem_dev->valid = (csc >> MC_CSC_EN_OFFSET) & 0x01;
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mem_dev->valid = (csc >> MC_CSC_EN_OFFSET) & 0x01;
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if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_ASYNC) {
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if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_ASYNC) {
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mem_dev->delayr = (tms & 0xff) + ((tms >> 8) & 0x0f);
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mem_dev->delayr = (tms & 0xff) + ((tms >> 8) & 0x0f);
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mem_dev->delayw = ((tms >> 12) & 0x0f) + ((tms >> 16) & 0x0f) + ((tms >> 20) & 0x3f);
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mem_dev->delayw = ((tms >> 12) & 0x0f) + ((tms >> 16) & 0x0f) + ((tms >> 20) & 0x3f);
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} else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SDRAM) {
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} else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SDRAM) {
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mem_dev->delayr = 3 + ((tms >> 4) & 0x03);
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mem_dev->delayr = 3 + ((tms >> 4) & 0x03);
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mem_dev->delayw = 3 + ((tms >> 4) & 0x03);
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mem_dev->delayw = 3 + ((tms >> 4) & 0x03);
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} else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SSRAM) {
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} else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SSRAM) {
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mem_dev->delayr = 2;
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mem_dev->delayr = 2;
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mem_dev->delayw = 2;
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mem_dev->delayw = 2;
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} else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SYNC) {
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} else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SYNC) {
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mem_dev->delayr = 2;
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mem_dev->delayr = 2;
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mem_dev->delayw = 2;
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mem_dev->delayw = 2;
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}
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}
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return;
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return;
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}
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}
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mem_dev = mem_dev->next;
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mem_dev = mem_dev->next;
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}
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}
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}
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}
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/* Set a specific MC register with value. */
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/* Set a specific MC register with value. */
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void mc_write_word(oraddr_t addr, uint32_t value, void *dat)
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void mc_write_word(oraddr_t addr, uint32_t value, void *dat)
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{
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{
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struct mc *mc = dat;
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struct mc *mc = dat;
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int chipsel;
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int chipsel;
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debug(5, "mc_write_word(%"PRIxADDR",%08"PRIx32")\n", addr, value);
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debug(5, "mc_write_word(%"PRIxADDR",%08"PRIx32")\n", addr, value);
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addr -= mc->baseaddr;
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addr -= mc->baseaddr;
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switch (addr) {
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switch (addr) {
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case MC_CSR:
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case MC_CSR:
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mc->csr = value;
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mc->csr = value;
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break;
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break;
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case MC_POC:
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case MC_POC:
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fprintf (stderr, "warning: write to MC's POC register!");
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fprintf (stderr, "warning: write to MC's POC register!");
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break;
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break;
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case MC_BA_MASK:
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case MC_BA_MASK:
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mc->ba_mask = value & MC_BA_MASK_VALID;
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mc->ba_mask = value & MC_BA_MASK_VALID;
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for (chipsel = 0; chipsel < N_CE; chipsel++)
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for (chipsel = 0; chipsel < N_CE; chipsel++)
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set_csc_tms (chipsel, mc->csc[chipsel], mc->tms[chipsel], mc);
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set_csc_tms (chipsel, mc->csc[chipsel], mc->tms[chipsel], mc);
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break;
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break;
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default:
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default:
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if (addr >= MC_CSC(0) && addr <= MC_TMS(N_CE - 1)) {
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if (addr >= MC_CSC(0) && addr <= MC_TMS(N_CE - 1)) {
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addr -= MC_CSC(0);
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addr -= MC_CSC(0);
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if ((addr >> 2) & 1)
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if ((addr >> 2) & 1)
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mc->tms[addr >> 3] = value;
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mc->tms[addr >> 3] = value;
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else
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else
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mc->csc[addr >> 3] = value;
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mc->csc[addr >> 3] = value;
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set_csc_tms (addr >> 3, mc->csc[addr >> 3], mc->tms[addr >> 3], mc);
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set_csc_tms (addr >> 3, mc->csc[addr >> 3], mc->tms[addr >> 3], mc);
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break;
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break;
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} else
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} else
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debug(1, "write out of range (addr %"PRIxADDR")\n", addr + mc->baseaddr);
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debug(1, "write out of range (addr %"PRIxADDR")\n", addr + mc->baseaddr);
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}
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}
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}
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}
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/* Read a specific MC register. */
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/* Read a specific MC register. */
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uint32_t mc_read_word(oraddr_t addr, void *dat)
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uint32_t mc_read_word(oraddr_t addr, void *dat)
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{
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{
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struct mc *mc = dat;
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struct mc *mc = dat;
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uint32_t value = 0;
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uint32_t value = 0;
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debug(5, "mc_read_word(%"PRIxADDR")", addr);
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debug(5, "mc_read_word(%"PRIxADDR")", addr);
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addr -= mc->baseaddr;
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addr -= mc->baseaddr;
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switch (addr) {
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switch (addr) {
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case MC_CSR:
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case MC_CSR:
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value = mc->csr;
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value = mc->csr;
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break;
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break;
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case MC_POC:
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case MC_POC:
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value = mc->poc;
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value = mc->poc;
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break;
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break;
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case MC_BA_MASK:
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case MC_BA_MASK:
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value = mc->ba_mask;
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value = mc->ba_mask;
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break;
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break;
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default:
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default:
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if (addr >= MC_CSC(0) && addr <= MC_TMS(N_CE - 1)) {
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if (addr >= MC_CSC(0) && addr <= MC_TMS(N_CE - 1)) {
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addr -= MC_CSC(0);
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addr -= MC_CSC(0);
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if ((addr >> 2) & 1)
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if ((addr >> 2) & 1)
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value = mc->tms[addr >> 3];
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value = mc->tms[addr >> 3];
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else
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else
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value = mc->csc[addr >> 3];
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value = mc->csc[addr >> 3];
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} else
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} else
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debug(1, " read out of range (addr %"PRIxADDR")\n", addr + mc->baseaddr);
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debug(1, " read out of range (addr %"PRIxADDR")\n", addr + mc->baseaddr);
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break;
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break;
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}
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}
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debug(5, " value(%"PRIx32")\n", value);
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debug(5, " value(%"PRIx32")\n", value);
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return value;
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return value;
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}
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}
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/* Read POC register and init memory controler regs. */
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/* Read POC register and init memory controler regs. */
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void mc_reset(void *dat)
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void mc_reset(void *dat)
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{
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{
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struct mc *mc = dat;
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struct mc *mc = dat;
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struct dev_memarea *mem_dev = dev_list;
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struct dev_memarea *mem_dev = dev_list;
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PRINTF("Resetting memory controller.\n");
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PRINTF("Resetting memory controller.\n");
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memset(mc->csc, 0, sizeof(mc->csc));
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memset(mc->csc, 0, sizeof(mc->csc));
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memset(mc->tms, 0, sizeof(mc->tms));
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memset(mc->tms, 0, sizeof(mc->tms));
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mc->csr = 0;
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mc->csr = 0;
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mc->ba_mask = 0;
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mc->ba_mask = 0;
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/* Set CS0 */
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/* Set CS0 */
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mc->csc[0] = (((mc->poc & 0x0c) >> 2) << MC_CSC_MEMTYPE_OFFSET) | ((mc->poc & 0x03) << MC_CSC_BW_OFFSET) | 1;
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mc->csc[0] = (((mc->poc & 0x0c) >> 2) << MC_CSC_MEMTYPE_OFFSET) | ((mc->poc & 0x03) << MC_CSC_BW_OFFSET) | 1;
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if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_ASYNC) {
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if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_ASYNC) {
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mc->tms[0] = MC_TMS_ASYNC_VALID;
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mc->tms[0] = MC_TMS_ASYNC_VALID;
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} else if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SDRAM) {
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} else if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SDRAM) {
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mc->tms[0] = MC_TMS_SDRAM_VALID;
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mc->tms[0] = MC_TMS_SDRAM_VALID;
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} else if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SSRAM) {
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} else if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SSRAM) {
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mc->tms[0] = MC_TMS_SSRAM_VALID;
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mc->tms[0] = MC_TMS_SSRAM_VALID;
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} else if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SYNC) {
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} else if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SYNC) {
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mc->tms[0] = MC_TMS_SYNC_VALID;
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mc->tms[0] = MC_TMS_SYNC_VALID;
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}
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}
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while (mem_dev) {
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while (mem_dev) {
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mem_dev->valid = 0;
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mem_dev->valid = 0;
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mem_dev = mem_dev->next;
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mem_dev = mem_dev->next;
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}
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}
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set_csc_tms (0, mc->csc[0], mc->tms[0], mc);
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set_csc_tms (0, mc->csc[0], mc->tms[0], mc);
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}
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}
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void mc_status(void *dat)
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void mc_status(void *dat)
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{
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{
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struct mc *mc = dat;
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struct mc *mc = dat;
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int i;
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int i;
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PRINTF( "\nMemory Controller at 0x%"PRIxADDR":\n", mc->baseaddr );
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PRINTF( "\nMemory Controller at 0x%"PRIxADDR":\n", mc->baseaddr );
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PRINTF( "POC: 0x%08lX\n", mc->poc );
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PRINTF( "POC: 0x%08lX\n", mc->poc );
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PRINTF( "BAS: 0x%08lX\n", mc->ba_mask );
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PRINTF( "BAS: 0x%08lX\n", mc->ba_mask );
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PRINTF( "CSR: 0x%08lX\n", mc->csr );
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PRINTF( "CSR: 0x%08lX\n", mc->csr );
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for (i=0; i<N_CE; i++) {
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for (i=0; i<N_CE; i++) {
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PRINTF( "CE %02d - CSC: 0x%08lX TMS: 0x%08lX\n", i, mc->csc[i],
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PRINTF( "CE %02d - CSC: 0x%08lX TMS: 0x%08lX\n", i, mc->csc[i],
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mc->tms[i]);
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mc->tms[i]);
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}
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}
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}
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}
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/*-----------------------------------------------------[ MC configuration }---*/
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/*-----------------------------------------------------[ MC configuration }---*/
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void mc_enabled(union param_val val, void *dat)
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void mc_enabled(union param_val val, void *dat)
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{
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{
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struct mc *mc = dat;
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struct mc *mc = dat;
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mc->enabled = val.int_val;
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mc->enabled = val.int_val;
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}
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}
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void mc_baseaddr(union param_val val, void *dat)
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void mc_baseaddr(union param_val val, void *dat)
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{
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{
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struct mc *mc = dat;
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struct mc *mc = dat;
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mc->baseaddr = val.addr_val;
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mc->baseaddr = val.addr_val;
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}
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}
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void mc_POC(union param_val val, void *dat)
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void mc_POC(union param_val val, void *dat)
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{
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{
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struct mc *mc = dat;
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struct mc *mc = dat;
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mc->poc = val.int_val;
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mc->poc = val.int_val;
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}
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}
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void *mc_sec_start(void)
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void *mc_sec_start(void)
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{
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{
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struct mc *new = malloc(sizeof(struct mc));
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struct mc *new = malloc(sizeof(struct mc));
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if(!new) {
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if(!new) {
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fprintf(stderr, "Peripheral MC: Run out of memory\n");
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fprintf(stderr, "Peripheral MC: Run out of memory\n");
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exit(-1);
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exit(-1);
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}
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}
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new->enabled = 0;
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new->enabled = 0;
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return new;
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return new;
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}
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}
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void mc_sec_end(void *dat)
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void mc_sec_end(void *dat)
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{
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{
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struct mc *mc = dat;
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struct mc *mc = dat;
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if(!mc->enabled) {
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if(!mc->enabled) {
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free(dat);
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free(dat);
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return;
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return;
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}
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}
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register_memoryarea(mc->baseaddr, MC_ADDR_SPACE, 4, 1, mc_read_word,
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register_memoryarea(mc->baseaddr, MC_ADDR_SPACE, 4, 1, mc_read_word,
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mc_write_word, dat);
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mc_write_word, dat);
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reg_sim_reset(mc_reset, dat);
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reg_sim_reset(mc_reset, dat);
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reg_sim_stat(mc_status, dat);
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reg_sim_stat(mc_status, dat);
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}
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}
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void reg_mc_sec(void)
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void reg_mc_sec(void)
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{
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{
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struct config_section *sec = reg_config_sec("mc", mc_sec_start, mc_sec_end);
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struct config_section *sec = reg_config_sec("mc", mc_sec_start, mc_sec_end);
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reg_config_param(sec, "enabled", paramt_int, mc_enabled);
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reg_config_param(sec, "enabled", paramt_int, mc_enabled);
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reg_config_param(sec, "baseaddr", paramt_addr, mc_baseaddr);
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reg_config_param(sec, "baseaddr", paramt_addr, mc_baseaddr);
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reg_config_param(sec, "POC", paramt_int, mc_POC);
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reg_config_param(sec, "POC", paramt_int, mc_POC);
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}
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}
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