/* mc_dram.h - Memory Controller testbench SDRAM defines
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/* mc_dram.h - Memory Controller testbench SDRAM defines
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Copyright (C) 2001 by Ivan Guzvinec, ivang@opencores.org
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Copyright (C) 2001 by Ivan Guzvinec, ivang@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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*/
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#ifndef __MC_DRAM_H
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#ifndef __MC_DRAM_H
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#define __MC_DRAM_H
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#define __MC_DRAM_H
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/* should configuration be read from MC? */
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/* should configuration be read from MC? */
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#define MC_READ_CONF
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#define MC_READ_CONF
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/* TEMPLATE SELECTION */
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/* TEMPLATE SELECTION */
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/* change #undef to #define */
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/* change #undef to #define */
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#undef _MC_TEST_TEMPLATE1
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#undef _MC_TEST_TEMPLATE1
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#define _MC_TEST_TEMPLATE2
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#define _MC_TEST_TEMPLATE2
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#undef _MC_TEST_TEMPLATE3
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#undef _MC_TEST_TEMPLATE3
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/* ------------------------ */
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/* ------------------------ */
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/* memory configuration that must reflect sim.cfg */
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/* memory configuration that must reflect sim.cfg */
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#define MC_SDRAM_CSMASK 0x02 /* 8 bit mask for 8 chip selects. 1 SDRAM at CS, 0 something else at CS */
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#define MC_SDRAM_CSMASK 0x02 /* 8 bit mask for 8 chip selects. 1 SDRAM at CS, 0 something else at CS */
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/* bits: CS7|CS6|CS5|CS4|CS3|CS2|CS1|CS0 */
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/* bits: CS7|CS6|CS5|CS4|CS3|CS2|CS1|CS0 */
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typedef struct MC_SDRAM_CS
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typedef struct MC_SDRAM_CS
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{
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{
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unsigned long BW;
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unsigned long BW;
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unsigned long MS;
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unsigned long MS;
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unsigned long M;
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unsigned long M;
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} MC_SDRAM_CS;
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} MC_SDRAM_CS;
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MC_SDRAM_CS mc_sdram_cs[8] = {
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MC_SDRAM_CS mc_sdram_cs[8] = {
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{ 2, /* Bus Width : 0 - 8bit, 1 - 16bit, 2 - 32bit */
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{ 2, /* Bus Width : 0 - 8bit, 1 - 16bit, 2 - 32bit */
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2, /* Memory Size : 0 - 64Mbit, 1 - 128Mbit, 2 - 256Mbit */
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2, /* Memory Size : 0 - 64Mbit, 1 - 128Mbit, 2 - 256Mbit */
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0x20 /* SELect mask */
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0x20 /* SELect mask */
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},
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},
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{ 1, 0, 0x20 },
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{ 1, 0, 0x20 },
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{ 2, 0, 0x06 },
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{ 2, 0, 0x06 },
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{ 2, 0, 0x08 },
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{ 2, 0, 0x08 },
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{ 2, 0, 0x0A },
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{ 2, 0, 0x0A },
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{ 2, 0, 0x0C },
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{ 2, 0, 0x0C },
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{ 2, 0, 0x0E },
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{ 2, 0, 0x0E },
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{ 2, 0, 0x10 } };
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{ 2, 0, 0x10 } };
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/* SDRAM configuration tests flag defines */
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/* SDRAM configuration tests flag defines */
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#define MC_SDRAM_TEST0 0x00000001LU /*no parity, close row, BankAfterCol, R/W, single loc, seq. burst 1 */
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#define MC_SDRAM_TEST0 0x00000001LU /*no parity, close row, BankAfterCol, R/W, single loc, seq. burst 1 */
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#define MC_SDRAM_TEST1 0x00000002LU /*parity enabled*/
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#define MC_SDRAM_TEST1 0x00000002LU /*parity enabled*/
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#define MC_SDRAM_TEST2 0x00000004LU /*keep row*/
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#define MC_SDRAM_TEST2 0x00000004LU /*keep row*/
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#define MC_SDRAM_TEST3 0x00000008LU /*BankAfterRow*/
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#define MC_SDRAM_TEST3 0x00000008LU /*BankAfterRow*/
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#define MC_SDRAM_TEST4 0x00000010LU /*RO*/
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#define MC_SDRAM_TEST4 0x00000010LU /*RO*/
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#define MC_SDRAM_TEST5 0x00000020LU /*prog. burst 1*/
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#define MC_SDRAM_TEST5 0x00000020LU /*prog. burst 1*/
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#define MC_SDRAM_TEST6 0x00000040LU /* -||- 2*/
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#define MC_SDRAM_TEST6 0x00000040LU /* -||- 2*/
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#define MC_SDRAM_TEST7 0x00000080LU /* -||- 4*/
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#define MC_SDRAM_TEST7 0x00000080LU /* -||- 4*/
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#define MC_SDRAM_TEST8 0x00000100LU /* -||- 8*/
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#define MC_SDRAM_TEST8 0x00000100LU /* -||- 8*/
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#define MC_SDRAM_TEST9 0x00000200LU /* -||- fullpage*/
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#define MC_SDRAM_TEST9 0x00000200LU /* -||- fullpage*/
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#define MC_SDRAM_TEST10 0x00000400LU /*prog. burst int. 1*/
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#define MC_SDRAM_TEST10 0x00000400LU /*prog. burst int. 1*/
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#define MC_SDRAM_TEST11 0x00000800LU /* -||- 2*/
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#define MC_SDRAM_TEST11 0x00000800LU /* -||- 2*/
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#define MC_SDRAM_TEST12 0x00001000LU /* -||- 4*/
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#define MC_SDRAM_TEST12 0x00001000LU /* -||- 4*/
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#define MC_SDRAM_TEST13 0x00002000LU /* -||- 8*/
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#define MC_SDRAM_TEST13 0x00002000LU /* -||- 8*/
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#define MC_SDRAM_TEST14 0x00004000LU /* -||- fullpage*/
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#define MC_SDRAM_TEST14 0x00004000LU /* -||- fullpage*/
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#define MC_SDRAM_TEST15 0x00008000LU /*prog. burst int. fullpage, keep row*/
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#define MC_SDRAM_TEST15 0x00008000LU /*prog. burst int. fullpage, keep row*/
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#define MC_SDRAM_TEST16 0x00010000LU /* NOT DEFINED */
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#define MC_SDRAM_TEST16 0x00010000LU /* NOT DEFINED */
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/* test type flag defines */
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/* test type flag defines */
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#define MC_SDRAM_SROW 0x00000001LU /* perform sequential row access test */
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#define MC_SDRAM_SROW 0x00000001LU /* perform sequential row access test */
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#define MC_SDRAM_RROW 0x00000010LU /* perform random row access test */
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#define MC_SDRAM_RROW 0x00000010LU /* perform random row access test */
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#define MC_SDRAM_SGRP 0x00000100LU /* perform sequential row-group access test */
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#define MC_SDRAM_SGRP 0x00000100LU /* perform sequential row-group access test */
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#define MC_SDRAM_RGRP 0x00001000LU /* perform random row-group access test */
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#define MC_SDRAM_RGRP 0x00001000LU /* perform random row-group access test */
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#define MC_SDRAM_ROWSH_0 16
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#define MC_SDRAM_ROWSH_0 16
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#define MC_SDRAM_ROWSH_1 16
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#define MC_SDRAM_ROWSH_1 16
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#define MC_SDRAM_ROWSH_2 15
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#define MC_SDRAM_ROWSH_2 15
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#define MC_SDRAM_ROWSH_3 16
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#define MC_SDRAM_ROWSH_3 16
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#define MC_SDRAM_ROWSH_4 16
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#define MC_SDRAM_ROWSH_4 16
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#define MC_SDRAM_ROWSH_5 16
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#define MC_SDRAM_ROWSH_5 16
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#define MC_SDRAM_ROWSH_6 17
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#define MC_SDRAM_ROWSH_6 17
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#define MC_SDRAM_ROWSH_7 17
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#define MC_SDRAM_ROWSH_7 17
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#define MC_SDRAM_ROWSH_8 17
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#define MC_SDRAM_ROWSH_8 17
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/* TEMPLATE 1 */
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/* TEMPLATE 1 */
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#ifdef _MC_TEST_TEMPLATE1
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#ifdef _MC_TEST_TEMPLATE1
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#define MC_SDRAM_FLAGS 0x000004A8LU /* MC_TEST_ flags... see mc_common.h */
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#define MC_SDRAM_FLAGS 0x000004A8LU /* MC_TEST_ flags... see mc_common.h */
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#define MC_SDRAM_TESTS 0x00000001LU /* mask for SDRAM configuration, see conf. test flag defines */
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#define MC_SDRAM_TESTS 0x00000001LU /* mask for SDRAM configuration, see conf. test flag defines */
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#define MC_SDRAM_ACC 0x00001010LU /* mask for test types */
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#define MC_SDRAM_ACC 0x00001010LU /* mask for test types */
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/* memory sizes*/
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/* memory sizes*/
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#define MC_SDRAM_GROUPSIZE 5
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#define MC_SDRAM_GROUPSIZE 5
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/* MAX */
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/* MAX */
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#define MC_SDRAM_ROWSIZE_0 8/* 16 * 1024 * 4 */
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#define MC_SDRAM_ROWSIZE_0 8/* 16 * 1024 * 4 */
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#define MC_SDRAM_ROWSIZE_1 8/* 16 * 1024 * 4 */
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#define MC_SDRAM_ROWSIZE_1 8/* 16 * 1024 * 4 */
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#define MC_SDRAM_ROWSIZE_2 8/* 8 * 1024 * 4 */
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#define MC_SDRAM_ROWSIZE_2 8/* 8 * 1024 * 4 */
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#define MC_SDRAM_ROWSIZE_3 8/* 16 * 1024 * 4 */
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#define MC_SDRAM_ROWSIZE_3 8/* 16 * 1024 * 4 */
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#define MC_SDRAM_ROWSIZE_4 8/* 16 * 1024 * 4 */
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#define MC_SDRAM_ROWSIZE_4 8/* 16 * 1024 * 4 */
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#define MC_SDRAM_ROWSIZE_5 8/* 16 * 1024 * 4 */
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#define MC_SDRAM_ROWSIZE_5 8/* 16 * 1024 * 4 */
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#define MC_SDRAM_ROWSIZE_6 8/* 32 * 1024 * 4 */
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#define MC_SDRAM_ROWSIZE_6 8/* 32 * 1024 * 4 */
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#define MC_SDRAM_ROWSIZE_7 8/* 32 * 1024 * 4 */
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#define MC_SDRAM_ROWSIZE_7 8/* 32 * 1024 * 4 */
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#define MC_SDRAM_ROWSIZE_8 8/* 32 * 1024 * 4 */
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#define MC_SDRAM_ROWSIZE_8 8/* 32 * 1024 * 4 */
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/* MAX */
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/* MAX */
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#define MC_SDRAM_ROWS_0 25/* 512 */
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#define MC_SDRAM_ROWS_0 25/* 512 */
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#define MC_SDRAM_ROWS_1 25/* 256 */
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#define MC_SDRAM_ROWS_1 25/* 256 */
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#define MC_SDRAM_ROWS_2 25/* 256 */
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#define MC_SDRAM_ROWS_2 25/* 256 */
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#define MC_SDRAM_ROWS_3 25/* 1024 */
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#define MC_SDRAM_ROWS_3 25/* 1024 */
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#define MC_SDRAM_ROWS_4 25/* 512 */
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#define MC_SDRAM_ROWS_4 25/* 512 */
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#define MC_SDRAM_ROWS_5 25/* 256 */
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#define MC_SDRAM_ROWS_5 25/* 256 */
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#define MC_SDRAM_ROWS_6 25/* 1024 */
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#define MC_SDRAM_ROWS_6 25/* 1024 */
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#define MC_SDRAM_ROWS_7 25/* 512 */
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#define MC_SDRAM_ROWS_7 25/* 512 */
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#define MC_SDRAM_ROWS_8 25/* 256 */
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#define MC_SDRAM_ROWS_8 25/* 256 */
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#define MC_SDRAM_ROW_OFF 5
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#define MC_SDRAM_ROW_OFF 5
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#endif /*_MC_TEST_TEMPLATE1*/
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#endif /*_MC_TEST_TEMPLATE1*/
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/* TEMPLATE 2 */
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/* TEMPLATE 2 */
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#ifdef _MC_TEST_TEMPLATE2
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#ifdef _MC_TEST_TEMPLATE2
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#define MC_SDRAM_FLAGS 0x000004A8LU /* MC_TEST_ flags... see mc_common.h */
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#define MC_SDRAM_FLAGS 0x000004A8LU /* MC_TEST_ flags... see mc_common.h */
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#define MC_SDRAM_TESTS 0x00000001LU /* mask for SDRAM configuration, see conf. test flag defines */
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#define MC_SDRAM_TESTS 0x00000001LU /* mask for SDRAM configuration, see conf. test flag defines */
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#define MC_SDRAM_ACC 0x00001010LU /* mask for test types */
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#define MC_SDRAM_ACC 0x00001010LU /* mask for test types */
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/* memory sizes*/
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/* memory sizes*/
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#define MC_SDRAM_GROUPSIZE 5
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#define MC_SDRAM_GROUPSIZE 5
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#define MC_SDRAM_ROWSIZE_0 16 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_0 16 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_1 16 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_1 16 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_2 8 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_2 8 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_3 16 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_3 16 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_4 16 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_4 16 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_5 16 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_5 16 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_6 32 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_6 32 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_7 32 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_7 32 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_8 32 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_8 32 * 1024 * 4
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#define MC_SDRAM_ROWS_0 512
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#define MC_SDRAM_ROWS_0 512
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#define MC_SDRAM_ROWS_1 256
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#define MC_SDRAM_ROWS_1 256
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#define MC_SDRAM_ROWS_2 256
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#define MC_SDRAM_ROWS_2 256
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#define MC_SDRAM_ROWS_3 1024
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#define MC_SDRAM_ROWS_3 1024
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#define MC_SDRAM_ROWS_4 512
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#define MC_SDRAM_ROWS_4 512
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#define MC_SDRAM_ROWS_5 256
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#define MC_SDRAM_ROWS_5 256
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#define MC_SDRAM_ROWS_6 1024
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#define MC_SDRAM_ROWS_6 1024
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#define MC_SDRAM_ROWS_7 512
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#define MC_SDRAM_ROWS_7 512
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#define MC_SDRAM_ROWS_8 256
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#define MC_SDRAM_ROWS_8 256
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#endif /*_MC_TEST_TEMPLATE2*/
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#endif /*_MC_TEST_TEMPLATE2*/
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/* TEMPLATE 3 */
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/* TEMPLATE 3 */
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#ifdef _MC_TEST_TEMPLATE3
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#ifdef _MC_TEST_TEMPLATE3
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#define MC_SDRAM_FLAGS 0x000004A8LU /* MC_TEST_ flags... see mc_common.h */
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#define MC_SDRAM_FLAGS 0x000004A8LU /* MC_TEST_ flags... see mc_common.h */
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#define MC_SDRAM_TESTS 0x00000001LU /* mask for SDRAM configuration, see conf. test flag defines */
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#define MC_SDRAM_TESTS 0x00000001LU /* mask for SDRAM configuration, see conf. test flag defines */
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#define MC_SDRAM_ACC 0x00001010LU /* mask for test types */
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#define MC_SDRAM_ACC 0x00001010LU /* mask for test types */
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/* memory sizes*/
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/* memory sizes*/
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#define MC_SDRAM_GROUPSIZE 5
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#define MC_SDRAM_GROUPSIZE 5
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/* MAX */
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/* MAX */
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#define MC_SDRAM_ROWSIZE_0 16 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_0 16 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_1 16 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_1 16 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_2 8 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_2 8 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_3 16 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_3 16 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_4 16 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_4 16 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_5 16 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_5 16 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_6 32 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_6 32 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_7 32 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_7 32 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_8 32 * 1024 * 4
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#define MC_SDRAM_ROWSIZE_8 32 * 1024 * 4
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/* MAX */
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/* MAX */
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#define MC_SDRAM_ROWS_0 10/* 512 */
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#define MC_SDRAM_ROWS_0 10/* 512 */
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#define MC_SDRAM_ROWS_1 10/* 256 */
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#define MC_SDRAM_ROWS_1 10/* 256 */
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#define MC_SDRAM_ROWS_2 10/* 256 */
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#define MC_SDRAM_ROWS_2 10/* 256 */
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#define MC_SDRAM_ROWS_3 10/* 1024 */
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#define MC_SDRAM_ROWS_3 10/* 1024 */
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#define MC_SDRAM_ROWS_4 10/* 512 */
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#define MC_SDRAM_ROWS_4 10/* 512 */
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#define MC_SDRAM_ROWS_5 10/* 256 */
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#define MC_SDRAM_ROWS_5 10/* 256 */
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#define MC_SDRAM_ROWS_6 10/* 1024 */
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#define MC_SDRAM_ROWS_6 10/* 1024 */
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#define MC_SDRAM_ROWS_7 10/* 512 */
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#define MC_SDRAM_ROWS_7 10/* 512 */
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#define MC_SDRAM_ROWS_8 10/* 256 */
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#define MC_SDRAM_ROWS_8 10/* 256 */
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#endif /*_MC_TEST_TEMPLATE3*/
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#endif /*_MC_TEST_TEMPLATE3*/
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#endif
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#endif
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