//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's Data Cache top level ////
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//// OR1200's Data Cache top level ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Instantiation of all DC blocks. ////
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//// Instantiation of all DC blocks. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// - make it smaller and faster ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
|
// CVS Revision History
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//
|
//
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// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/01/28 01:16:00 lampret
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// Revision 1.3 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
|
//
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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//
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// Revision 1.10 2001/10/21 17:57:16 lampret
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// Revision 1.10 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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//
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// Revision 1.9 2001/10/14 13:12:09 lampret
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// Revision 1.9 2001/10/14 13:12:09 lampret
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// MP3 version.
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// MP3 version.
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//
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//
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// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
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// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
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// no message
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// no message
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//
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//
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// Revision 1.4 2001/08/13 03:36:20 lampret
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// Revision 1.4 2001/08/13 03:36:20 lampret
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// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
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// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
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//
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//
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// Revision 1.3 2001/08/09 13:39:33 lampret
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// Revision 1.3 2001/08/09 13:39:33 lampret
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// Major clean-up.
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// Major clean-up.
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//
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//
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// Revision 1.2 2001/07/22 03:31:53 lampret
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// Revision 1.2 2001/07/22 03:31:53 lampret
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// Fixed RAM's oen bug. Cache bypass under development.
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// Fixed RAM's oen bug. Cache bypass under development.
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//
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//
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Development version of RTL. Libraries are missing.
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// Development version of RTL. Libraries are missing.
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//
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//
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//
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//
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|
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
|
`include "or1200_defines.v"
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`include "or1200_defines.v"
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|
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//
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//
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// Data cache
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// Data cache
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//
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//
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module or1200_dc_top(
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module or1200_dc_top(
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// Rst, clk and clock control
|
// Rst, clk and clock control
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clk, rst,
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clk, rst,
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|
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// External i/f
|
// External i/f
|
dcbiu_dat_o, dcbiu_adr_o, dcbiu_cyc_o, dcbiu_stb_o, dcbiu_we_o, dcbiu_sel_o, dcbiu_cab_o,
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dcbiu_dat_o, dcbiu_adr_o, dcbiu_cyc_o, dcbiu_stb_o, dcbiu_we_o, dcbiu_sel_o, dcbiu_cab_o,
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dcbiu_dat_i, dcbiu_ack_i, dcbiu_err_i,
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dcbiu_dat_i, dcbiu_ack_i, dcbiu_err_i,
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|
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// Internal i/f
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// Internal i/f
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dc_en,
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dc_en,
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dcdmmu_adr_i, dcdmmu_cycstb_i, dcdmmu_ci_i,
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dcdmmu_adr_i, dcdmmu_cycstb_i, dcdmmu_ci_i,
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dcpu_we_i, dcpu_sel_i, dcpu_tag_i, dcpu_dat_i,
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dcpu_we_i, dcpu_sel_i, dcpu_tag_i, dcpu_dat_i,
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dcpu_dat_o, dcpu_ack_o, dcpu_rty_o, dcdmmu_err_o, dcdmmu_tag_o,
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dcpu_dat_o, dcpu_ack_o, dcpu_rty_o, dcdmmu_err_o, dcdmmu_tag_o,
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|
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// SPRs
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// SPRs
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spr_cs, spr_write, spr_dat_i
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spr_cs, spr_write, spr_dat_i
|
);
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);
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|
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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|
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//
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//
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// I/O
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// I/O
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//
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//
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|
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//
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//
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// Clock and reset
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// Clock and reset
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//
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//
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input clk;
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input clk;
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input rst;
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input rst;
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|
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//
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//
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// External I/F
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// External I/F
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//
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//
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output [dw-1:0] dcbiu_dat_o;
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output [dw-1:0] dcbiu_dat_o;
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output [31:0] dcbiu_adr_o;
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output [31:0] dcbiu_adr_o;
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output dcbiu_cyc_o;
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output dcbiu_cyc_o;
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output dcbiu_stb_o;
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output dcbiu_stb_o;
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output dcbiu_we_o;
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output dcbiu_we_o;
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output [3:0] dcbiu_sel_o;
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output [3:0] dcbiu_sel_o;
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output dcbiu_cab_o;
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output dcbiu_cab_o;
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input [dw-1:0] dcbiu_dat_i;
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input [dw-1:0] dcbiu_dat_i;
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input dcbiu_ack_i;
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input dcbiu_ack_i;
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input dcbiu_err_i;
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input dcbiu_err_i;
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|
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//
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//
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// Internal I/F
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// Internal I/F
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//
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//
|
input dc_en;
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input dc_en;
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input [31:0] dcdmmu_adr_i;
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input [31:0] dcdmmu_adr_i;
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input dcdmmu_cycstb_i;
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input dcdmmu_cycstb_i;
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input dcdmmu_ci_i;
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input dcdmmu_ci_i;
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input dcpu_we_i;
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input dcpu_we_i;
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input [3:0] dcpu_sel_i;
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input [3:0] dcpu_sel_i;
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input [3:0] dcpu_tag_i;
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input [3:0] dcpu_tag_i;
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input [dw-1:0] dcpu_dat_i;
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input [dw-1:0] dcpu_dat_i;
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output [dw-1:0] dcpu_dat_o;
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output [dw-1:0] dcpu_dat_o;
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output dcpu_ack_o;
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output dcpu_ack_o;
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output dcpu_rty_o;
|
output dcpu_rty_o;
|
output dcdmmu_err_o;
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output dcdmmu_err_o;
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output [3:0] dcdmmu_tag_o;
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output [3:0] dcdmmu_tag_o;
|
|
|
//
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//
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// SPR access
|
// SPR access
|
//
|
//
|
input spr_cs;
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input spr_cs;
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input spr_write;
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input spr_write;
|
input [31:0] spr_dat_i;
|
input [31:0] spr_dat_i;
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|
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//
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//
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// Internal wires and regs
|
// Internal wires and regs
|
//
|
//
|
wire tag_v;
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wire tag_v;
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wire [`OR1200_DCTAG_W-2:0] tag;
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wire [`OR1200_DCTAG_W-2:0] tag;
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wire [dw-1:0] to_dcram;
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wire [dw-1:0] to_dcram;
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wire [dw-1:0] from_dcram;
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wire [dw-1:0] from_dcram;
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wire [31:0] saved_addr;
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wire [31:0] saved_addr;
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wire [3:0] dcram_we;
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wire [3:0] dcram_we;
|
wire dctag_we;
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wire dctag_we;
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wire [31:0] dc_addr;
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wire [31:0] dc_addr;
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wire dcfsm_biu_read;
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wire dcfsm_biu_read;
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wire dcfsm_biu_write;
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wire dcfsm_biu_write;
|
reg tagcomp_miss;
|
reg tagcomp_miss;
|
wire [`OR1200_DCINDXH:`OR1200_DCLS] dctag_addr;
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wire [`OR1200_DCINDXH:`OR1200_DCLS] dctag_addr;
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wire dctag_en;
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wire dctag_en;
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wire dctag_v;
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wire dctag_v;
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wire dc_inv;
|
wire dc_inv;
|
wire dcfsm_first_hit_ack;
|
wire dcfsm_first_hit_ack;
|
wire dcfsm_first_miss_ack;
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wire dcfsm_first_miss_ack;
|
wire dcfsm_first_miss_err;
|
wire dcfsm_first_miss_err;
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wire dcfsm_burst;
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wire dcfsm_burst;
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wire dcfsm_tag_we;
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wire dcfsm_tag_we;
|
|
|
//
|
//
|
// Simple assignments
|
// Simple assignments
|
//
|
//
|
assign dcbiu_adr_o = dc_addr;
|
assign dcbiu_adr_o = dc_addr;
|
assign dc_inv = spr_cs & spr_write;
|
assign dc_inv = spr_cs & spr_write;
|
assign dctag_we = dcfsm_tag_we | dc_inv;
|
assign dctag_we = dcfsm_tag_we | dc_inv;
|
assign dctag_addr = dc_inv ? spr_dat_i[`OR1200_DCINDXH:`OR1200_DCLS] : dc_addr[`OR1200_DCINDXH:`OR1200_DCLS];
|
assign dctag_addr = dc_inv ? spr_dat_i[`OR1200_DCINDXH:`OR1200_DCLS] : dc_addr[`OR1200_DCINDXH:`OR1200_DCLS];
|
assign dctag_en = dc_inv | dc_en;
|
assign dctag_en = dc_inv | dc_en;
|
assign dctag_v = ~dc_inv;
|
assign dctag_v = ~dc_inv;
|
|
|
//
|
//
|
// Data to BIU is from DCRAM when DC is enabled or from LSU when
|
// Data to BIU is from DCRAM when DC is enabled or from LSU when
|
// DC is disabled
|
// DC is disabled
|
//
|
//
|
assign dcbiu_dat_o = dcpu_dat_i;
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assign dcbiu_dat_o = dcpu_dat_i;
|
|
|
//
|
//
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// Bypases of the DC when DC is disabled
|
// Bypases of the DC when DC is disabled
|
//
|
//
|
assign dcbiu_cyc_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcdmmu_cycstb_i;
|
assign dcbiu_cyc_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcdmmu_cycstb_i;
|
assign dcbiu_stb_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcdmmu_cycstb_i;
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assign dcbiu_stb_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcdmmu_cycstb_i;
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assign dcbiu_we_o = (dc_en) ? dcfsm_biu_write : dcpu_we_i;
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assign dcbiu_we_o = (dc_en) ? dcfsm_biu_write : dcpu_we_i;
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assign dcbiu_sel_o = (dc_en & dcfsm_biu_read & !dcfsm_biu_write & !dcdmmu_ci_i) ? 4'b1111 : dcpu_sel_i;
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assign dcbiu_sel_o = (dc_en & dcfsm_biu_read & !dcfsm_biu_write & !dcdmmu_ci_i) ? 4'b1111 : dcpu_sel_i;
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assign dcbiu_cab_o = (dc_en) ? dcfsm_burst : 1'b0;
|
assign dcbiu_cab_o = (dc_en) ? dcfsm_burst : 1'b0;
|
assign dcpu_rty_o = ~dcpu_ack_o;
|
assign dcpu_rty_o = ~dcpu_ack_o;
|
assign dcdmmu_tag_o = dcdmmu_err_o ? `OR1200_DTAG_BE : dcpu_tag_i;
|
assign dcdmmu_tag_o = dcdmmu_err_o ? `OR1200_DTAG_BE : dcpu_tag_i;
|
|
|
//
|
//
|
// DC/LSU normal and error termination
|
// DC/LSU normal and error termination
|
//
|
//
|
assign dcpu_ack_o = dc_en ? dcfsm_first_hit_ack | dcfsm_first_miss_ack : dcbiu_ack_i;
|
assign dcpu_ack_o = dc_en ? dcfsm_first_hit_ack | dcfsm_first_miss_ack : dcbiu_ack_i;
|
assign dcdmmu_err_o = dc_en ? dcfsm_first_miss_err : dcbiu_err_i;
|
assign dcdmmu_err_o = dc_en ? dcfsm_first_miss_err : dcbiu_err_i;
|
|
|
//
|
//
|
// Select between claddr generated by DC FSM and addr[3:2] generated by LSU
|
// Select between claddr generated by DC FSM and addr[3:2] generated by LSU
|
//
|
//
|
//assign dc_addr = (dcfsm_biu_read | dcfsm_biu_write) ? saved_addr : dcdmmu_adr_i;
|
//assign dc_addr = (dcfsm_biu_read | dcfsm_biu_write) ? saved_addr : dcdmmu_adr_i;
|
|
|
//
|
//
|
// Select between input data generated by LSU or by BIU
|
// Select between input data generated by LSU or by BIU
|
//
|
//
|
assign to_dcram = (dcfsm_biu_read) ? dcbiu_dat_i : dcpu_dat_i;
|
assign to_dcram = (dcfsm_biu_read) ? dcbiu_dat_i : dcpu_dat_i;
|
|
|
//
|
//
|
// Select between data generated by DCRAM or passed by BIU
|
// Select between data generated by DCRAM or passed by BIU
|
//
|
//
|
assign dcpu_dat_o = dcfsm_first_miss_ack | !dc_en ? dcbiu_dat_i : from_dcram;
|
assign dcpu_dat_o = dcfsm_first_miss_ack | !dc_en ? dcbiu_dat_i : from_dcram;
|
|
|
//
|
//
|
// Tag comparison
|
// Tag comparison
|
//
|
//
|
always @(tag or saved_addr or tag_v) begin
|
always @(tag or saved_addr or tag_v) begin
|
if ((tag != saved_addr[31:`OR1200_DCTAGL]) || !tag_v)
|
if ((tag != saved_addr[31:`OR1200_DCTAGL]) || !tag_v)
|
tagcomp_miss = 1'b1;
|
tagcomp_miss = 1'b1;
|
else
|
else
|
tagcomp_miss = 1'b0;
|
tagcomp_miss = 1'b0;
|
end
|
end
|
|
|
//
|
//
|
// Instantiation of DC Finite State Machine
|
// Instantiation of DC Finite State Machine
|
//
|
//
|
or1200_dc_fsm or1200_dc_fsm(
|
or1200_dc_fsm or1200_dc_fsm(
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
.dc_en(dc_en),
|
.dc_en(dc_en),
|
.dcdmmu_cycstb_i(dcdmmu_cycstb_i),
|
.dcdmmu_cycstb_i(dcdmmu_cycstb_i),
|
.dcdmmu_ci_i(dcdmmu_ci_i),
|
.dcdmmu_ci_i(dcdmmu_ci_i),
|
.dcpu_we_i(dcpu_we_i),
|
.dcpu_we_i(dcpu_we_i),
|
.dcpu_sel_i(dcpu_sel_i),
|
.dcpu_sel_i(dcpu_sel_i),
|
.tagcomp_miss(tagcomp_miss),
|
.tagcomp_miss(tagcomp_miss),
|
.biudata_valid(dcbiu_ack_i),
|
.biudata_valid(dcbiu_ack_i),
|
.biudata_error(dcbiu_err_i),
|
.biudata_error(dcbiu_err_i),
|
.start_addr(dcdmmu_adr_i),
|
.start_addr(dcdmmu_adr_i),
|
.saved_addr(saved_addr),
|
.saved_addr(saved_addr),
|
.dcram_we(dcram_we),
|
.dcram_we(dcram_we),
|
.biu_read(dcfsm_biu_read),
|
.biu_read(dcfsm_biu_read),
|
.biu_write(dcfsm_biu_write),
|
.biu_write(dcfsm_biu_write),
|
.first_hit_ack(dcfsm_first_hit_ack),
|
.first_hit_ack(dcfsm_first_hit_ack),
|
.first_miss_ack(dcfsm_first_miss_ack),
|
.first_miss_ack(dcfsm_first_miss_ack),
|
.first_miss_err(dcfsm_first_miss_err),
|
.first_miss_err(dcfsm_first_miss_err),
|
.burst(dcfsm_burst),
|
.burst(dcfsm_burst),
|
.tag_we(dcfsm_tag_we),
|
.tag_we(dcfsm_tag_we),
|
.dc_addr(dc_addr)
|
.dc_addr(dc_addr)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of DC main memory
|
// Instantiation of DC main memory
|
//
|
//
|
or1200_dc_ram or1200_dc_ram(
|
or1200_dc_ram or1200_dc_ram(
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
.addr(dc_addr[`OR1200_DCINDXH:2]),
|
.addr(dc_addr[`OR1200_DCINDXH:2]),
|
.en(dc_en),
|
.en(dc_en),
|
.we(dcram_we),
|
.we(dcram_we),
|
.datain(to_dcram),
|
.datain(to_dcram),
|
.dataout(from_dcram)
|
.dataout(from_dcram)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of DC TAG memory
|
// Instantiation of DC TAG memory
|
//
|
//
|
or1200_dc_tag or1200_dc_tag(
|
or1200_dc_tag or1200_dc_tag(
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
.addr(dctag_addr),
|
.addr(dctag_addr),
|
.en(dctag_en),
|
.en(dctag_en),
|
.we(dctag_we),
|
.we(dctag_we),
|
.datain({dc_addr[31:`OR1200_DCTAGL], dctag_v}),
|
.datain({dc_addr[31:`OR1200_DCTAGL], dctag_v}),
|
.tag_v(tag_v),
|
.tag_v(tag_v),
|
.tag(tag)
|
.tag(tag)
|
);
|
);
|
|
|
endmodule
|
endmodule
|
|
|
