//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's register file generic memory ////
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//// OR1200's register file generic memory ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Generic (flip-flop based) register file memory ////
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//// Generic (flip-flop based) register file memory ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - nothing ////
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//// - nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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module or1200_rfram_generic(
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module or1200_rfram_generic(
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// Clock and reset
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// Clock and reset
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clk, rst,
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clk, rst,
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// Port A
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// Port A
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ce_a, addr_a, do_a,
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ce_a, addr_a, do_a,
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|
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// Port B
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// Port B
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ce_b, addr_b, do_b,
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ce_b, addr_b, do_b,
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|
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// Port W
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// Port W
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ce_w, we_w, addr_w, di_w
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ce_w, we_w, addr_w, di_w
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);
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
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parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
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//
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//
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// I/O
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// I/O
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//
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//
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|
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//
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//
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// Clock and reset
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// Clock and reset
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//
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//
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input clk;
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input clk;
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input rst;
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input rst;
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//
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//
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// Port A
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// Port A
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//
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//
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input ce_a;
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input ce_a;
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input [aw-1:0] addr_a;
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input [aw-1:0] addr_a;
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output [dw-1:0] do_a;
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output [dw-1:0] do_a;
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//
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//
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// Port B
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// Port B
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//
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//
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input ce_b;
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input ce_b;
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input [aw-1:0] addr_b;
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input [aw-1:0] addr_b;
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output [dw-1:0] do_b;
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output [dw-1:0] do_b;
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|
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//
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//
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// Port W
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// Port W
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//
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//
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input ce_w;
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input ce_w;
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input we_w;
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input we_w;
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input [aw-1:0] addr_w;
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input [aw-1:0] addr_w;
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input [dw-1:0] di_w;
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input [dw-1:0] di_w;
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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reg [aw-1:0] intaddr_a;
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reg [aw-1:0] intaddr_a;
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reg [aw-1:0] intaddr_b;
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reg [aw-1:0] intaddr_b;
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reg [32*dw-1:0] mem;
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reg [32*dw-1:0] mem;
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reg [dw-1:0] do_a;
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reg [dw-1:0] do_a;
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reg [dw-1:0] do_b;
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reg [dw-1:0] do_b;
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//
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//
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// Write port
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// Write port
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst) begin
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if (rst) begin
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mem <= #1 1024'h0;
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mem <= #1 1024'h0;
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end
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end
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else if (ce_w & we_w)
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else if (ce_w & we_w)
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case (addr_w) // synopsys parallel_case full_case
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case (addr_w) // synopsys parallel_case full_case
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5'd00: mem[32*0+31:32*0] <= #1 di_w;
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5'd00: mem[32*0+31:32*0] <= #1 di_w;
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5'd01: mem[32*1+31:32*1] <= #1 di_w;
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5'd01: mem[32*1+31:32*1] <= #1 di_w;
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5'd02: mem[32*2+31:32*2] <= #1 di_w;
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5'd02: mem[32*2+31:32*2] <= #1 di_w;
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5'd03: mem[32*3+31:32*3] <= #1 di_w;
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5'd03: mem[32*3+31:32*3] <= #1 di_w;
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5'd04: mem[32*4+31:32*4] <= #1 di_w;
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5'd04: mem[32*4+31:32*4] <= #1 di_w;
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5'd05: mem[32*5+31:32*5] <= #1 di_w;
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5'd05: mem[32*5+31:32*5] <= #1 di_w;
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5'd06: mem[32*6+31:32*6] <= #1 di_w;
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5'd06: mem[32*6+31:32*6] <= #1 di_w;
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5'd07: mem[32*7+31:32*7] <= #1 di_w;
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5'd07: mem[32*7+31:32*7] <= #1 di_w;
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5'd08: mem[32*8+31:32*8] <= #1 di_w;
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5'd08: mem[32*8+31:32*8] <= #1 di_w;
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5'd09: mem[32*9+31:32*9] <= #1 di_w;
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5'd09: mem[32*9+31:32*9] <= #1 di_w;
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5'd10: mem[32*10+31:32*10] <= #1 di_w;
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5'd10: mem[32*10+31:32*10] <= #1 di_w;
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5'd11: mem[32*11+31:32*11] <= #1 di_w;
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5'd11: mem[32*11+31:32*11] <= #1 di_w;
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5'd12: mem[32*12+31:32*12] <= #1 di_w;
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5'd12: mem[32*12+31:32*12] <= #1 di_w;
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5'd13: mem[32*13+31:32*13] <= #1 di_w;
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5'd13: mem[32*13+31:32*13] <= #1 di_w;
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5'd14: mem[32*14+31:32*14] <= #1 di_w;
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5'd14: mem[32*14+31:32*14] <= #1 di_w;
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5'd15: mem[32*15+31:32*15] <= #1 di_w;
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5'd15: mem[32*15+31:32*15] <= #1 di_w;
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5'd16: mem[32*16+31:32*16] <= #1 di_w;
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5'd16: mem[32*16+31:32*16] <= #1 di_w;
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5'd17: mem[32*17+31:32*17] <= #1 di_w;
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5'd17: mem[32*17+31:32*17] <= #1 di_w;
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5'd18: mem[32*18+31:32*18] <= #1 di_w;
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5'd18: mem[32*18+31:32*18] <= #1 di_w;
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5'd19: mem[32*19+31:32*19] <= #1 di_w;
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5'd19: mem[32*19+31:32*19] <= #1 di_w;
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5'd20: mem[32*20+31:32*20] <= #1 di_w;
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5'd20: mem[32*20+31:32*20] <= #1 di_w;
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5'd21: mem[32*21+31:32*21] <= #1 di_w;
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5'd21: mem[32*21+31:32*21] <= #1 di_w;
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5'd22: mem[32*22+31:32*22] <= #1 di_w;
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5'd22: mem[32*22+31:32*22] <= #1 di_w;
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5'd23: mem[32*23+31:32*23] <= #1 di_w;
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5'd23: mem[32*23+31:32*23] <= #1 di_w;
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5'd24: mem[32*24+31:32*24] <= #1 di_w;
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5'd24: mem[32*24+31:32*24] <= #1 di_w;
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5'd25: mem[32*25+31:32*25] <= #1 di_w;
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5'd25: mem[32*25+31:32*25] <= #1 di_w;
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5'd26: mem[32*26+31:32*26] <= #1 di_w;
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5'd26: mem[32*26+31:32*26] <= #1 di_w;
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5'd27: mem[32*27+31:32*27] <= #1 di_w;
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5'd27: mem[32*27+31:32*27] <= #1 di_w;
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5'd28: mem[32*28+31:32*28] <= #1 di_w;
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5'd28: mem[32*28+31:32*28] <= #1 di_w;
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5'd29: mem[32*29+31:32*29] <= #1 di_w;
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5'd29: mem[32*29+31:32*29] <= #1 di_w;
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5'd30: mem[32*30+31:32*30] <= #1 di_w;
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5'd30: mem[32*30+31:32*30] <= #1 di_w;
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5'd31: mem[32*31+31:32*31] <= #1 di_w;
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5'd31: mem[32*31+31:32*31] <= #1 di_w;
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endcase
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endcase
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//
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//
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// Read port A
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// Read port A
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst) begin
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if (rst) begin
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intaddr_a <= #1 5'h00;
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intaddr_a <= #1 5'h00;
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end
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end
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else if (ce_a)
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else if (ce_a)
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intaddr_a <= #1 addr_a;
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intaddr_a <= #1 addr_a;
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always @(mem or intaddr_a)
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always @(mem or intaddr_a)
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case (intaddr_a) // synopsys parallel_case full_case
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case (intaddr_a) // synopsys parallel_case full_case
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5'd00: do_a = mem[32*0+31:32*0];
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5'd00: do_a = mem[32*0+31:32*0];
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5'd01: do_a = mem[32*1+31:32*1];
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5'd01: do_a = mem[32*1+31:32*1];
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5'd02: do_a = mem[32*2+31:32*2];
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5'd02: do_a = mem[32*2+31:32*2];
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5'd03: do_a = mem[32*3+31:32*3];
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5'd03: do_a = mem[32*3+31:32*3];
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5'd04: do_a = mem[32*4+31:32*4];
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5'd04: do_a = mem[32*4+31:32*4];
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5'd05: do_a = mem[32*5+31:32*5];
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5'd05: do_a = mem[32*5+31:32*5];
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5'd06: do_a = mem[32*6+31:32*6];
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5'd06: do_a = mem[32*6+31:32*6];
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5'd07: do_a = mem[32*7+31:32*7];
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5'd07: do_a = mem[32*7+31:32*7];
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5'd08: do_a = mem[32*8+31:32*8];
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5'd08: do_a = mem[32*8+31:32*8];
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5'd09: do_a = mem[32*9+31:32*9];
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5'd09: do_a = mem[32*9+31:32*9];
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5'd10: do_a = mem[32*10+31:32*10];
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5'd10: do_a = mem[32*10+31:32*10];
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5'd11: do_a = mem[32*11+31:32*11];
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5'd11: do_a = mem[32*11+31:32*11];
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5'd12: do_a = mem[32*12+31:32*12];
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5'd12: do_a = mem[32*12+31:32*12];
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5'd13: do_a = mem[32*13+31:32*13];
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5'd13: do_a = mem[32*13+31:32*13];
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5'd14: do_a = mem[32*14+31:32*14];
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5'd14: do_a = mem[32*14+31:32*14];
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5'd15: do_a = mem[32*15+31:32*15];
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5'd15: do_a = mem[32*15+31:32*15];
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5'd16: do_a = mem[32*16+31:32*16];
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5'd16: do_a = mem[32*16+31:32*16];
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5'd17: do_a = mem[32*17+31:32*17];
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5'd17: do_a = mem[32*17+31:32*17];
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5'd18: do_a = mem[32*18+31:32*18];
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5'd18: do_a = mem[32*18+31:32*18];
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5'd19: do_a = mem[32*19+31:32*19];
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5'd19: do_a = mem[32*19+31:32*19];
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5'd20: do_a = mem[32*20+31:32*20];
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5'd20: do_a = mem[32*20+31:32*20];
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5'd21: do_a = mem[32*21+31:32*21];
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5'd21: do_a = mem[32*21+31:32*21];
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5'd22: do_a = mem[32*22+31:32*22];
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5'd22: do_a = mem[32*22+31:32*22];
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5'd23: do_a = mem[32*23+31:32*23];
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5'd23: do_a = mem[32*23+31:32*23];
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5'd24: do_a = mem[32*24+31:32*24];
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5'd24: do_a = mem[32*24+31:32*24];
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5'd25: do_a = mem[32*25+31:32*25];
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5'd25: do_a = mem[32*25+31:32*25];
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5'd26: do_a = mem[32*26+31:32*26];
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5'd26: do_a = mem[32*26+31:32*26];
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5'd27: do_a = mem[32*27+31:32*27];
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5'd27: do_a = mem[32*27+31:32*27];
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5'd28: do_a = mem[32*28+31:32*28];
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5'd28: do_a = mem[32*28+31:32*28];
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5'd29: do_a = mem[32*29+31:32*29];
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5'd29: do_a = mem[32*29+31:32*29];
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5'd30: do_a = mem[32*30+31:32*30];
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5'd30: do_a = mem[32*30+31:32*30];
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5'd31: do_a = mem[32*31+31:32*31];
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5'd31: do_a = mem[32*31+31:32*31];
|
endcase
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endcase
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|
|
//
|
//
|
// Read port B
|
// Read port B
|
//
|
//
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst) begin
|
if (rst) begin
|
intaddr_b <= #1 5'h00;
|
intaddr_b <= #1 5'h00;
|
end
|
end
|
else if (ce_b)
|
else if (ce_b)
|
intaddr_b <= #1 addr_b;
|
intaddr_b <= #1 addr_b;
|
|
|
always @(mem or intaddr_b)
|
always @(mem or intaddr_b)
|
case (intaddr_b) // synopsys parallel_case full_case
|
case (intaddr_b) // synopsys parallel_case full_case
|
5'd00: do_b = mem[32*0+31:32*0];
|
5'd00: do_b = mem[32*0+31:32*0];
|
5'd01: do_b = mem[32*1+31:32*1];
|
5'd01: do_b = mem[32*1+31:32*1];
|
5'd02: do_b = mem[32*2+31:32*2];
|
5'd02: do_b = mem[32*2+31:32*2];
|
5'd03: do_b = mem[32*3+31:32*3];
|
5'd03: do_b = mem[32*3+31:32*3];
|
5'd04: do_b = mem[32*4+31:32*4];
|
5'd04: do_b = mem[32*4+31:32*4];
|
5'd05: do_b = mem[32*5+31:32*5];
|
5'd05: do_b = mem[32*5+31:32*5];
|
5'd06: do_b = mem[32*6+31:32*6];
|
5'd06: do_b = mem[32*6+31:32*6];
|
5'd07: do_b = mem[32*7+31:32*7];
|
5'd07: do_b = mem[32*7+31:32*7];
|
5'd08: do_b = mem[32*8+31:32*8];
|
5'd08: do_b = mem[32*8+31:32*8];
|
5'd09: do_b = mem[32*9+31:32*9];
|
5'd09: do_b = mem[32*9+31:32*9];
|
5'd10: do_b = mem[32*10+31:32*10];
|
5'd10: do_b = mem[32*10+31:32*10];
|
5'd11: do_b = mem[32*11+31:32*11];
|
5'd11: do_b = mem[32*11+31:32*11];
|
5'd12: do_b = mem[32*12+31:32*12];
|
5'd12: do_b = mem[32*12+31:32*12];
|
5'd13: do_b = mem[32*13+31:32*13];
|
5'd13: do_b = mem[32*13+31:32*13];
|
5'd14: do_b = mem[32*14+31:32*14];
|
5'd14: do_b = mem[32*14+31:32*14];
|
5'd15: do_b = mem[32*15+31:32*15];
|
5'd15: do_b = mem[32*15+31:32*15];
|
5'd16: do_b = mem[32*16+31:32*16];
|
5'd16: do_b = mem[32*16+31:32*16];
|
5'd17: do_b = mem[32*17+31:32*17];
|
5'd17: do_b = mem[32*17+31:32*17];
|
5'd18: do_b = mem[32*18+31:32*18];
|
5'd18: do_b = mem[32*18+31:32*18];
|
5'd19: do_b = mem[32*19+31:32*19];
|
5'd19: do_b = mem[32*19+31:32*19];
|
5'd20: do_b = mem[32*20+31:32*20];
|
5'd20: do_b = mem[32*20+31:32*20];
|
5'd21: do_b = mem[32*21+31:32*21];
|
5'd21: do_b = mem[32*21+31:32*21];
|
5'd22: do_b = mem[32*22+31:32*22];
|
5'd22: do_b = mem[32*22+31:32*22];
|
5'd23: do_b = mem[32*23+31:32*23];
|
5'd23: do_b = mem[32*23+31:32*23];
|
5'd24: do_b = mem[32*24+31:32*24];
|
5'd24: do_b = mem[32*24+31:32*24];
|
5'd25: do_b = mem[32*25+31:32*25];
|
5'd25: do_b = mem[32*25+31:32*25];
|
5'd26: do_b = mem[32*26+31:32*26];
|
5'd26: do_b = mem[32*26+31:32*26];
|
5'd27: do_b = mem[32*27+31:32*27];
|
5'd27: do_b = mem[32*27+31:32*27];
|
5'd28: do_b = mem[32*28+31:32*28];
|
5'd28: do_b = mem[32*28+31:32*28];
|
5'd29: do_b = mem[32*29+31:32*29];
|
5'd29: do_b = mem[32*29+31:32*29];
|
5'd30: do_b = mem[32*30+31:32*30];
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5'd30: do_b = mem[32*30+31:32*30];
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5'd31: do_b = mem[32*31+31:32*31];
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5'd31: do_b = mem[32*31+31:32*31];
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endcase
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endcase
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|
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endmodule
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endmodule
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