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[/] [or1k/] [tags/] [rel_1/] [or1200/] [syn/] [scr/] [top_multp2_32x32.scr] - Diff between revs 896 and 1765

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Rev 896 Rev 1765
/*
/*
 * User defines for synthesizing multiplier
 * User defines for synthesizing multiplier
 *
 *
 */
 */
TOPLEVEL = multp2_32x32
TOPLEVEL = multp2_32x32
include select_tech.inc
include select_tech.inc
CLK = CLK
CLK = CLK
RST = rst
RST = rst
CLK_PERIOD = 2          /* 500 MHz */
CLK_PERIOD = 2          /* 500 MHz */
MAX_AREA = 0            /* Push hard */
MAX_AREA = 0            /* Push hard */
DO_UNGROUP = yes        /* yes, no */
DO_UNGROUP = yes        /* yes, no */
DO_VERIFY = no          /* yes, no */
DO_VERIFY = no          /* yes, no */
 
 
/* Starting timestamp */
/* Starting timestamp */
sh date
sh date
 
 
/* Set some basic variables related to environment */
/* Set some basic variables related to environment */
include set_env.inc
include set_env.inc
STAGE = initial
STAGE = initial
 
 
/* Load libraries */
/* Load libraries */
include tech_ + TECH + .inc
include tech_ + TECH + .inc
 
 
/* Load HDL source files */
/* Load HDL source files */
include read_design.inc         > LOG_PATH + read_design_ + TOPLEVEL + .log
include read_design.inc         > LOG_PATH + read_design_ + TOPLEVEL + .log
 
 
/* Set design top */
/* Set design top */
current_design TOPLEVEL
current_design TOPLEVEL
 
 
/* Link all blocks and uniquify them */
/* Link all blocks and uniquify them */
link
link
uniquify
uniquify
check_design                    > LOG_PATH + check_design_ + TOPLEVEL + .log
check_design                    > LOG_PATH + check_design_ + TOPLEVEL + .log
 
 
/* Apply constraints */
/* Apply constraints */
if (TECH == "vs_umc18") {
if (TECH == "vs_umc18") {
        include cons_vs_umc18.inc
        include cons_vs_umc18.inc
} else if (TECH == "art_umc18") {
} else if (TECH == "art_umc18") {
        include cons_art_umc18.inc
        include cons_art_umc18.inc
} else {
} else {
        echo "Error: Unsupported technology"
        echo "Error: Unsupported technology"
        exit
        exit
}
}
 
 
/* Transform arithmetics */
/* Transform arithmetics */
transform_csa -group
transform_csa -group
 
 
/* Lets do basic synthesis */
/* Lets do basic synthesis */
if (DO_UNGROUP == "yes") {
if (DO_UNGROUP == "yes") {
        ungroup -all -flatten
        ungroup -all -flatten
}
}
compile -boundary_optimization -map_effort low
compile -boundary_optimization -map_effort low
 
 
/* Generate reports for basic synthesis */
/* Generate reports for basic synthesis */
include reports.inc
include reports.inc
 
 
/* Dump gate-level from basic synthesis */
/* Dump gate-level from basic synthesis */
include save_design.inc
include save_design.inc
 
 
/* Advance to incremental synthesis, push hard */
/* Advance to incremental synthesis, push hard */
STAGE = incremental
STAGE = incremental
compile -incremental -boundary_optimization -auto_ungroup -map_effort medium
compile -incremental -boundary_optimization -auto_ungroup -map_effort medium
 
 
/* Optimize registers */
/* Optimize registers */
optimize_registers
optimize_registers
 
 
/* Dump gate-level from incremental synthesis */
/* Dump gate-level from incremental synthesis */
include save_design.inc
include save_design.inc
 
 
/* Generate reports for incremental synthesis */
/* Generate reports for incremental synthesis */
include reports.inc
include reports.inc
 
 
/* Set area constraint */
/* Set area constraint */
STAGE = final
STAGE = final
set_max_area MAX_AREA
set_max_area MAX_AREA
compile -incremental -boundary_optimization -auto_ungroup -map_effort medium
compile -incremental -boundary_optimization -auto_ungroup -map_effort medium
 
 
/* Dump gate-level from final synthesis */
/* Dump gate-level from final synthesis */
include save_design.inc
include save_design.inc
 
 
/* Generate reports for final synthesis */
/* Generate reports for final synthesis */
include reports.inc
include reports.inc
 
 
/* Verify design */
/* Verify design */
if (DO_VERIFY == "yes") {
if (DO_VERIFY == "yes") {
        compile -no_map -verify         > LOG_PATH + verify_ + TOPLEVEL + .log
        compile -no_map -verify         > LOG_PATH + verify_ + TOPLEVEL + .log
}
}
 
 
/* Finish */
/* Finish */
sh date
sh date
exit
exit
 
 
 
 
 
 
 
 
 
 

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