//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's Debug Unit ////
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//// OR1200's Debug Unit ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Basic OR1200 debug unit. ////
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//// Basic OR1200 debug unit. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// - make it smaller and faster ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.8 2002/09/08 19:31:52 lampret
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// Revision 1.8 2002/09/08 19:31:52 lampret
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// Fixed a typo, reported by Taylor Su.
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// Fixed a typo, reported by Taylor Su.
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//
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//
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// Revision 1.7 2002/07/14 22:17:17 lampret
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// Revision 1.7 2002/07/14 22:17:17 lampret
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// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
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// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
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//
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//
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// Revision 1.6 2002/03/14 00:30:24 lampret
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// Revision 1.6 2002/03/14 00:30:24 lampret
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// Added alternative for critical path in DU.
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// Added alternative for critical path in DU.
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//
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//
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// Revision 1.5 2002/02/11 04:33:17 lampret
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// Revision 1.5 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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//
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// Revision 1.4 2002/01/28 01:16:00 lampret
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// Revision 1.4 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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//
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// Revision 1.3 2002/01/18 07:56:00 lampret
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// Revision 1.3 2002/01/18 07:56:00 lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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//
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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//
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// Revision 1.12 2001/11/30 18:58:00 simons
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// Revision 1.12 2001/11/30 18:58:00 simons
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// Trap insn couses break after exits ex_insn.
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// Trap insn couses break after exits ex_insn.
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//
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//
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// Revision 1.11 2001/11/23 08:38:51 lampret
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// Revision 1.11 2001/11/23 08:38:51 lampret
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// Changed DSR/DRR behavior and exception detection.
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// Changed DSR/DRR behavior and exception detection.
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//
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//
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// Revision 1.10 2001/11/20 21:25:44 lampret
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// Revision 1.10 2001/11/20 21:25:44 lampret
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// Fixed dbg_is_o assignment width.
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// Fixed dbg_is_o assignment width.
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//
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//
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// Revision 1.9 2001/11/20 18:46:14 simons
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// Revision 1.9 2001/11/20 18:46:14 simons
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// Break point bug fixed
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// Break point bug fixed
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//
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//
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// Revision 1.8 2001/11/18 08:36:28 lampret
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// Revision 1.8 2001/11/18 08:36:28 lampret
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// For GDB changed single stepping and disabled trap exception.
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// For GDB changed single stepping and disabled trap exception.
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//
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//
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// Revision 1.7 2001/10/21 18:09:53 lampret
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// Revision 1.7 2001/10/21 18:09:53 lampret
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// Fixed sensitivity list.
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// Fixed sensitivity list.
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//
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//
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// Revision 1.6 2001/10/14 13:12:09 lampret
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// Revision 1.6 2001/10/14 13:12:09 lampret
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// MP3 version.
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// MP3 version.
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//
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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//
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//
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// Debug unit
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// Debug unit
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//
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//
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module or1200_du(
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module or1200_du(
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// RISC Internal Interface
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// RISC Internal Interface
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clk, rst,
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clk, rst,
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dcpu_cycstb_i, dcpu_we_i, icpu_cycstb_i,
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dcpu_cycstb_i, dcpu_we_i, icpu_cycstb_i,
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ex_freeze, branch_op, ex_insn,
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ex_freeze, branch_op, ex_insn,
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spr_dat_npc, rf_dataw,
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spr_dat_npc, rf_dataw,
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du_dsr, du_stall, du_addr, du_dat_i, du_dat_o,
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du_dsr, du_stall, du_addr, du_dat_i, du_dat_o,
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du_read, du_write, du_except,
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du_read, du_write, du_except,
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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// External Debug Interface
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// External Debug Interface
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dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
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dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
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dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o
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dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o
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);
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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//
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//
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// I/O
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// I/O
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//
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//
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//
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//
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// RISC Internal Interface
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// RISC Internal Interface
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//
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//
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input clk; // Clock
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input clk; // Clock
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input rst; // Reset
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input rst; // Reset
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input dcpu_cycstb_i; // LSU status
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input dcpu_cycstb_i; // LSU status
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input dcpu_we_i; // LSU status
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input dcpu_we_i; // LSU status
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input [`OR1200_FETCHOP_WIDTH-1:0] icpu_cycstb_i; // IFETCH unit status
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input [`OR1200_FETCHOP_WIDTH-1:0] icpu_cycstb_i; // IFETCH unit status
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input ex_freeze; // EX stage freeze
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input ex_freeze; // EX stage freeze
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input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch op
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input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch op
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input [dw-1:0] ex_insn; // EX insn
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input [dw-1:0] ex_insn; // EX insn
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input [31:0] spr_dat_npc; // Next PC (for trace)
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input [31:0] spr_dat_npc; // Next PC (for trace)
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input [31:0] rf_dataw; // ALU result (for trace)
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input [31:0] rf_dataw; // ALU result (for trace)
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output [`OR1200_DU_DSR_WIDTH-1:0] du_dsr; // DSR
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output [`OR1200_DU_DSR_WIDTH-1:0] du_dsr; // DSR
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output du_stall; // Debug Unit Stall
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output du_stall; // Debug Unit Stall
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output [aw-1:0] du_addr; // Debug Unit Address
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output [aw-1:0] du_addr; // Debug Unit Address
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input [dw-1:0] du_dat_i; // Debug Unit Data In
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input [dw-1:0] du_dat_i; // Debug Unit Data In
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output [dw-1:0] du_dat_o; // Debug Unit Data Out
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output [dw-1:0] du_dat_o; // Debug Unit Data Out
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output du_read; // Debug Unit Read Enable
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output du_read; // Debug Unit Read Enable
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output du_write; // Debug Unit Write Enable
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output du_write; // Debug Unit Write Enable
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input [12:0] du_except; // Exception masked by DSR
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input [12:0] du_except; // Exception masked by DSR
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input spr_cs; // SPR Chip Select
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input spr_cs; // SPR Chip Select
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input spr_write; // SPR Read/Write
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input spr_write; // SPR Read/Write
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input [aw-1:0] spr_addr; // SPR Address
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input [aw-1:0] spr_addr; // SPR Address
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input [dw-1:0] spr_dat_i; // SPR Data Input
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input [dw-1:0] spr_dat_i; // SPR Data Input
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output [dw-1:0] spr_dat_o; // SPR Data Output
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output [dw-1:0] spr_dat_o; // SPR Data Output
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//
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//
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// External Debug Interface
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// External Debug Interface
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//
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//
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input dbg_stall_i; // External Stall Input
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input dbg_stall_i; // External Stall Input
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input [dw-1:0] dbg_dat_i; // External Data Input
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input [dw-1:0] dbg_dat_i; // External Data Input
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input [aw-1:0] dbg_adr_i; // External Address Input
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input [aw-1:0] dbg_adr_i; // External Address Input
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input [2:0] dbg_op_i; // External Operation Select Input
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input [2:0] dbg_op_i; // External Operation Select Input
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input dbg_ewt_i; // External Watchpoint Trigger Input
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input dbg_ewt_i; // External Watchpoint Trigger Input
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output [3:0] dbg_lss_o; // External Load/Store Unit Status
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output [3:0] dbg_lss_o; // External Load/Store Unit Status
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output [1:0] dbg_is_o; // External Insn Fetch Status
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output [1:0] dbg_is_o; // External Insn Fetch Status
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output [10:0] dbg_wp_o; // Watchpoints Outputs
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output [10:0] dbg_wp_o; // Watchpoints Outputs
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output dbg_bp_o; // Breakpoint Output
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output dbg_bp_o; // Breakpoint Output
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output [dw-1:0] dbg_dat_o; // External Data Output
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output [dw-1:0] dbg_dat_o; // External Data Output
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//
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//
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// Some connections go directly from the CPU through DU to Debug I/F
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// Some connections go directly from the CPU through DU to Debug I/F
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//
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//
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`ifdef OR1200_DU_STATUS_UNIMPLEMENTED
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`ifdef OR1200_DU_STATUS_UNIMPLEMENTED
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assign dbg_lss_o = 4'b0000;
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assign dbg_lss_o = 4'b0000;
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reg [1:0] dbg_is_o;
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reg [1:0] dbg_is_o;
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//
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//
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// Show insn activity (temp, must be removed)
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// Show insn activity (temp, must be removed)
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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dbg_is_o <= #1 2'b00;
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dbg_is_o <= #1 2'b00;
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else if (!ex_freeze &
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else if (!ex_freeze &
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~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]))
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~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]))
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dbg_is_o <= #1 ~dbg_is_o;
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dbg_is_o <= #1 ~dbg_is_o;
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`ifdef UNUSED
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`ifdef UNUSED
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assign dbg_is_o = 2'b00;
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assign dbg_is_o = 2'b00;
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`endif
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`endif
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`else
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`else
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assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000;
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assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000;
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assign dbg_is_o = {1'b0, icpu_cycstb_i};
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assign dbg_is_o = {1'b0, icpu_cycstb_i};
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`endif
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`endif
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assign dbg_wp_o = 11'b000_0000_0000;
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assign dbg_wp_o = 11'b000_0000_0000;
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assign dbg_dat_o = du_dat_i;
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assign dbg_dat_o = du_dat_i;
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//
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//
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// Some connections go directly from Debug I/F through DU to the CPU
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// Some connections go directly from Debug I/F through DU to the CPU
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//
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//
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assign du_stall = dbg_stall_i;
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assign du_stall = dbg_stall_i;
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assign du_addr = dbg_adr_i;
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assign du_addr = dbg_adr_i;
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assign du_dat_o = dbg_dat_i;
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assign du_dat_o = dbg_dat_i;
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assign du_read = (dbg_op_i == `OR1200_DU_OP_READSPR);
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assign du_read = (dbg_op_i == `OR1200_DU_OP_READSPR);
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assign du_write = (dbg_op_i == `OR1200_DU_OP_WRITESPR);
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assign du_write = (dbg_op_i == `OR1200_DU_OP_WRITESPR);
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`ifdef OR1200_DU_IMPLEMENTED
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`ifdef OR1200_DU_IMPLEMENTED
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//
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//
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// Debug Mode Register 1 (only ST and BT implemented)
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// Debug Mode Register 1 (only ST and BT implemented)
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//
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//
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`ifdef OR1200_DU_DMR1
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`ifdef OR1200_DU_DMR1
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reg [23:22] dmr1; // DMR1 implemented (ST & BT)
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reg [23:22] dmr1; // DMR1 implemented (ST & BT)
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`else
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`else
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wire [23:22] dmr1; // DMR1 not implemented
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wire [23:22] dmr1; // DMR1 not implemented
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`endif
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`endif
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//
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//
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// Debug Mode Register 2 (not implemented)
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// Debug Mode Register 2 (not implemented)
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//
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//
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`ifdef OR1200_DU_DMR2
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`ifdef OR1200_DU_DMR2
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wire [31:0] dmr2; // DMR not implemented
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wire [31:0] dmr2; // DMR not implemented
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`endif
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`endif
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//
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//
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// Debug Stop Register
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// Debug Stop Register
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//
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//
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`ifdef OR1200_DU_DSR
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`ifdef OR1200_DU_DSR
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reg [`OR1200_DU_DSR_WIDTH-1:0] dsr; // DSR implemented
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reg [`OR1200_DU_DSR_WIDTH-1:0] dsr; // DSR implemented
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`else
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`else
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wire [`OR1200_DU_DSR_WIDTH-1:0] dsr; // DSR not implemented
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wire [`OR1200_DU_DSR_WIDTH-1:0] dsr; // DSR not implemented
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`endif
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`endif
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//
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//
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// Debug Reason Register
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// Debug Reason Register
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//
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//
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`ifdef OR1200_DU_DRR
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`ifdef OR1200_DU_DRR
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reg [13:0] drr; // DRR implemented
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reg [13:0] drr; // DRR implemented
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`else
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`else
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wire [13:0] drr; // DRR not implemented
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wire [13:0] drr; // DRR not implemented
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`endif
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`endif
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//
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//
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// Internal wires
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// Internal wires
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//
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//
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wire dmr1_sel; // DMR1 select
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wire dmr1_sel; // DMR1 select
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wire dsr_sel; // DSR select
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wire dsr_sel; // DSR select
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wire drr_sel; // DRR select
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wire drr_sel; // DRR select
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reg dbg_bp_r;
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reg dbg_bp_r;
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`ifdef OR1200_DU_READREGS
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`ifdef OR1200_DU_READREGS
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reg [31:0] spr_dat_o;
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reg [31:0] spr_dat_o;
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`endif
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`endif
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reg [13:0] except_stop; // Exceptions that stop because of DSR
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reg [13:0] except_stop; // Exceptions that stop because of DSR
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`ifdef OR1200_DU_TB_IMPLEMENTED
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`ifdef OR1200_DU_TB_IMPLEMENTED
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wire tb_enw;
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wire tb_enw;
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reg [7:0] tb_wadr;
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reg [7:0] tb_wadr;
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reg [31:0] tb_timstmp;
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reg [31:0] tb_timstmp;
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`endif
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`endif
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wire [31:0] tbia_dat_o;
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wire [31:0] tbia_dat_o;
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wire [31:0] tbim_dat_o;
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wire [31:0] tbim_dat_o;
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wire [31:0] tbar_dat_o;
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wire [31:0] tbar_dat_o;
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wire [31:0] tbts_dat_o;
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wire [31:0] tbts_dat_o;
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//
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//
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// DU registers address decoder
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// DU registers address decoder
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//
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//
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`ifdef OR1200_DU_DMR1
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`ifdef OR1200_DU_DMR1
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assign dmr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_OFS_DMR1));
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assign dmr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_OFS_DMR1));
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`endif
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`endif
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`ifdef OR1200_DU_DSR
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`ifdef OR1200_DU_DSR
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assign dsr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_OFS_DSR));
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assign dsr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_OFS_DSR));
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`endif
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`endif
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`ifdef OR1200_DU_DRR
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`ifdef OR1200_DU_DRR
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assign drr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_OFS_DRR));
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assign drr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_OFS_DRR));
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`endif
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`endif
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|
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//
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//
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// Decode started exception
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// Decode started exception
|
//
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//
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always @(du_except) begin
|
always @(du_except) begin
|
except_stop = 14'b0000_0000_0000;
|
except_stop = 14'b0000_0000_0000;
|
casex (du_except)
|
casex (du_except)
|
13'b1_xxxx_xxxx_xxxx:
|
13'b1_xxxx_xxxx_xxxx:
|
except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
|
13'b0_1xxx_xxxx_xxxx: begin
|
13'b0_1xxx_xxxx_xxxx: begin
|
except_stop[`OR1200_DU_DRR_IE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_IE] = 1'b1;
|
end
|
end
|
13'b0_01xx_xxxx_xxxx: begin
|
13'b0_01xx_xxxx_xxxx: begin
|
except_stop[`OR1200_DU_DRR_IME] = 1'b1;
|
except_stop[`OR1200_DU_DRR_IME] = 1'b1;
|
end
|
end
|
13'b0_001x_xxxx_xxxx:
|
13'b0_001x_xxxx_xxxx:
|
except_stop[`OR1200_DU_DRR_IPFE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_IPFE] = 1'b1;
|
13'b0_0001_xxxx_xxxx: begin
|
13'b0_0001_xxxx_xxxx: begin
|
except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
|
end
|
end
|
13'b0_0000_1xxx_xxxx:
|
13'b0_0000_1xxx_xxxx:
|
except_stop[`OR1200_DU_DRR_IIE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_IIE] = 1'b1;
|
13'b0_0000_01xx_xxxx: begin
|
13'b0_0000_01xx_xxxx: begin
|
except_stop[`OR1200_DU_DRR_AE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_AE] = 1'b1;
|
end
|
end
|
13'b0_0000_001x_xxxx: begin
|
13'b0_0000_001x_xxxx: begin
|
except_stop[`OR1200_DU_DRR_DME] = 1'b1;
|
except_stop[`OR1200_DU_DRR_DME] = 1'b1;
|
end
|
end
|
13'b0_0000_0001_xxxx:
|
13'b0_0000_0001_xxxx:
|
except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
|
13'b0_0000_0000_1xxx:
|
13'b0_0000_0000_1xxx:
|
except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
|
13'b0_0000_0000_01xx: begin
|
13'b0_0000_0000_01xx: begin
|
except_stop[`OR1200_DU_DRR_RE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_RE] = 1'b1;
|
end
|
end
|
13'b0_0000_0000_001x: begin
|
13'b0_0000_0000_001x: begin
|
except_stop[`OR1200_DU_DRR_TE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_TE] = 1'b1;
|
end
|
end
|
13'b0_0000_0000_0001:
|
13'b0_0000_0000_0001:
|
except_stop[`OR1200_DU_DRR_SCE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_SCE] = 1'b1;
|
default:
|
default:
|
except_stop = 14'b0000_0000_0000;
|
except_stop = 14'b0000_0000_0000;
|
endcase
|
endcase
|
end
|
end
|
|
|
//
|
//
|
// dbg_bp_o is registered
|
// dbg_bp_o is registered
|
//
|
//
|
assign dbg_bp_o = dbg_bp_r;
|
assign dbg_bp_o = dbg_bp_r;
|
|
|
//
|
//
|
// Breakpoint activation register
|
// Breakpoint activation register
|
//
|
//
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
dbg_bp_r <= #1 1'b0;
|
dbg_bp_r <= #1 1'b0;
|
else if (!ex_freeze)
|
else if (!ex_freeze)
|
dbg_bp_r <= #1 |except_stop
|
dbg_bp_r <= #1 |except_stop
|
`ifdef OR1200_DU_DMR1_ST
|
`ifdef OR1200_DU_DMR1_ST
|
| ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]) & dmr1[`OR1200_DU_DMR1_ST]
|
| ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]) & dmr1[`OR1200_DU_DMR1_ST]
|
`endif
|
`endif
|
`ifdef OR1200_DU_DMR1_BT
|
`ifdef OR1200_DU_DMR1_BT
|
| (branch_op != `OR1200_BRANCHOP_NOP) & dmr1[`OR1200_DU_DMR1_BT]
|
| (branch_op != `OR1200_BRANCHOP_NOP) & dmr1[`OR1200_DU_DMR1_BT]
|
`endif
|
`endif
|
;
|
;
|
else
|
else
|
dbg_bp_r <= #1 |except_stop;
|
dbg_bp_r <= #1 |except_stop;
|
|
|
//
|
//
|
// Write to DMR1
|
// Write to DMR1
|
//
|
//
|
`ifdef OR1200_DU_DMR1
|
`ifdef OR1200_DU_DMR1
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
dmr1 <= 2'b00;
|
dmr1 <= 2'b00;
|
else if (dmr1_sel && spr_write)
|
else if (dmr1_sel && spr_write)
|
dmr1 <= #1 spr_dat_i[23:22];
|
dmr1 <= #1 spr_dat_i[23:22];
|
`else
|
`else
|
assign dmr1 = 2'b00;
|
assign dmr1 = 2'b00;
|
`endif
|
`endif
|
|
|
//
|
//
|
// DMR2 bits tied to zero
|
// DMR2 bits tied to zero
|
//
|
//
|
`ifdef OR1200_DU_DMR2
|
`ifdef OR1200_DU_DMR2
|
assign dmr2 = 32'h0000_0000;
|
assign dmr2 = 32'h0000_0000;
|
`endif
|
`endif
|
|
|
//
|
//
|
// Write to DSR
|
// Write to DSR
|
//
|
//
|
`ifdef OR1200_DU_DSR
|
`ifdef OR1200_DU_DSR
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};
|
dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};
|
else if (dsr_sel && spr_write)
|
else if (dsr_sel && spr_write)
|
dsr <= #1 spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0];
|
dsr <= #1 spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0];
|
`else
|
`else
|
assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
|
assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
|
`endif
|
`endif
|
|
|
//
|
//
|
// Write to DRR
|
// Write to DRR
|
//
|
//
|
`ifdef OR1200_DU_DRR
|
`ifdef OR1200_DU_DRR
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
drr <= 14'b0;
|
drr <= 14'b0;
|
else if (drr_sel && spr_write)
|
else if (drr_sel && spr_write)
|
drr <= #1 spr_dat_i[13:0];
|
drr <= #1 spr_dat_i[13:0];
|
else
|
else
|
drr <= #1 drr | except_stop;
|
drr <= #1 drr | except_stop;
|
`else
|
`else
|
assign drr = 14'b0;
|
assign drr = 14'b0;
|
`endif
|
`endif
|
|
|
//
|
//
|
// Read DU registers
|
// Read DU registers
|
//
|
//
|
`ifdef OR1200_DU_READREGS
|
`ifdef OR1200_DU_READREGS
|
always @(spr_addr or dsr or drr or dmr1 or dmr2
|
always @(spr_addr or dsr or drr or dmr1 or dmr2
|
`ifdef OR1200_DU_TB_IMPLEMENTED
|
`ifdef OR1200_DU_TB_IMPLEMENTED
|
or tb_wadr or tbia_dat_o or tbim_dat_o
|
or tb_wadr or tbia_dat_o or tbim_dat_o
|
or tbar_dat_o or tbts_dat_o
|
or tbar_dat_o or tbts_dat_o
|
`endif
|
`endif
|
)
|
)
|
casex (spr_addr[`OR1200_DUOFS_BITS]) // synopsys parallel_case
|
casex (spr_addr[`OR1200_DUOFS_BITS]) // synopsys parallel_case
|
`ifdef OR1200_DU_DMR1
|
`ifdef OR1200_DU_DMR1
|
`OR1200_DU_OFS_DMR1:
|
`OR1200_DU_OFS_DMR1:
|
spr_dat_o = {8'b0, dmr1, 22'b0};
|
spr_dat_o = {8'b0, dmr1, 22'b0};
|
`endif
|
`endif
|
`ifdef OR1200_DU_DMR2
|
`ifdef OR1200_DU_DMR2
|
`OR1200_DU_OFS_DMR2:
|
`OR1200_DU_OFS_DMR2:
|
spr_dat_o = dmr2;
|
spr_dat_o = dmr2;
|
`endif
|
`endif
|
`ifdef OR1200_DU_DSR
|
`ifdef OR1200_DU_DSR
|
`OR1200_DU_OFS_DSR:
|
`OR1200_DU_OFS_DSR:
|
spr_dat_o = {18'b0, dsr};
|
spr_dat_o = {18'b0, dsr};
|
`endif
|
`endif
|
`ifdef OR1200_DU_DRR
|
`ifdef OR1200_DU_DRR
|
`OR1200_DU_OFS_DRR:
|
`OR1200_DU_OFS_DRR:
|
spr_dat_o = {18'b0, drr};
|
spr_dat_o = {18'b0, drr};
|
`endif
|
`endif
|
`ifdef OR1200_DU_TB_IMPLEMENTED
|
`ifdef OR1200_DU_TB_IMPLEMENTED
|
`OR1200_DU_OFS_TBADR:
|
`OR1200_DU_OFS_TBADR:
|
spr_dat_o = {24'h000000, tb_wadr};
|
spr_dat_o = {24'h000000, tb_wadr};
|
`OR1200_DU_OFS_TBIA:
|
`OR1200_DU_OFS_TBIA:
|
spr_dat_o = tbia_dat_o;
|
spr_dat_o = tbia_dat_o;
|
`OR1200_DU_OFS_TBIM:
|
`OR1200_DU_OFS_TBIM:
|
spr_dat_o = tbim_dat_o;
|
spr_dat_o = tbim_dat_o;
|
`OR1200_DU_OFS_TBAR:
|
`OR1200_DU_OFS_TBAR:
|
spr_dat_o = tbar_dat_o;
|
spr_dat_o = tbar_dat_o;
|
`OR1200_DU_OFS_TBTS:
|
`OR1200_DU_OFS_TBTS:
|
spr_dat_o = tbts_dat_o;
|
spr_dat_o = tbts_dat_o;
|
`endif
|
`endif
|
default:
|
default:
|
spr_dat_o = 32'h0000_0000;
|
spr_dat_o = 32'h0000_0000;
|
endcase
|
endcase
|
`endif
|
`endif
|
|
|
//
|
//
|
// DSR alias
|
// DSR alias
|
//
|
//
|
assign du_dsr = dsr;
|
assign du_dsr = dsr;
|
|
|
`ifdef OR1200_DU_TB_IMPLEMENTED
|
`ifdef OR1200_DU_TB_IMPLEMENTED
|
//
|
//
|
// Simple trace buffer
|
// Simple trace buffer
|
// (right now hardcoded for Xilinx Virtex FPGAs)
|
// (right now hardcoded for Xilinx Virtex FPGAs)
|
//
|
//
|
// Stores last 256 instruction addresses, instruction
|
// Stores last 256 instruction addresses, instruction
|
// machine words and ALU results
|
// machine words and ALU results
|
//
|
//
|
|
|
//
|
//
|
// Trace buffer write enable
|
// Trace buffer write enable
|
//
|
//
|
assign tb_enw = ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]);
|
assign tb_enw = ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]);
|
|
|
//
|
//
|
// Trace buffer write address pointer
|
// Trace buffer write address pointer
|
//
|
//
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
tb_wadr <= #1 8'h00;
|
tb_wadr <= #1 8'h00;
|
else if (tb_enw)
|
else if (tb_enw)
|
tb_wadr <= #1 tb_wadr + 8'd1;
|
tb_wadr <= #1 tb_wadr + 8'd1;
|
|
|
//
|
//
|
// Free running counter (time stamp)
|
// Free running counter (time stamp)
|
//
|
//
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
tb_timstmp <= #1 32'h00000000;
|
tb_timstmp <= #1 32'h00000000;
|
else if (!dbg_bp_r)
|
else if (!dbg_bp_r)
|
tb_timstmp <= #1 tb_timstmp + 32'd1;
|
tb_timstmp <= #1 tb_timstmp + 32'd1;
|
|
|
//
|
//
|
// Trace buffer RAMs
|
// Trace buffer RAMs
|
//
|
//
|
RAMB4_S16_S16 tbia_ramb4_s16_0(
|
RAMB4_S16_S16 tbia_ramb4_s16_0(
|
.CLKA(clk),
|
.CLKA(clk),
|
.RSTA(rst),
|
.RSTA(rst),
|
.ADDRA(tb_wadr),
|
.ADDRA(tb_wadr),
|
.DIA(spr_dat_npc[15:0]),
|
.DIA(spr_dat_npc[15:0]),
|
.ENA(1'b1),
|
.ENA(1'b1),
|
.WEA(tb_enw),
|
.WEA(tb_enw),
|
.DOA(),
|
.DOA(),
|
|
|
.CLKB(clk),
|
.CLKB(clk),
|
.RSTB(rst),
|
.RSTB(rst),
|
.ADDRB(spr_addr[7:0]),
|
.ADDRB(spr_addr[7:0]),
|
.DIB(16'h0000),
|
.DIB(16'h0000),
|
.ENB(1'b1),
|
.ENB(1'b1),
|
.WEB(1'b0),
|
.WEB(1'b0),
|
.DOB(tbia_dat_o[15:0])
|
.DOB(tbia_dat_o[15:0])
|
);
|
);
|
|
|
RAMB4_S16_S16 tbia_ramb4_s16_1(
|
RAMB4_S16_S16 tbia_ramb4_s16_1(
|
.CLKA(clk),
|
.CLKA(clk),
|
.RSTA(rst),
|
.RSTA(rst),
|
.ADDRA(tb_wadr),
|
.ADDRA(tb_wadr),
|
.DIA(spr_dat_npc[31:16]),
|
.DIA(spr_dat_npc[31:16]),
|
.ENA(1'b1),
|
.ENA(1'b1),
|
.WEA(tb_enw),
|
.WEA(tb_enw),
|
.DOA(),
|
.DOA(),
|
|
|
.CLKB(clk),
|
.CLKB(clk),
|
.RSTB(rst),
|
.RSTB(rst),
|
.ADDRB(spr_addr[7:0]),
|
.ADDRB(spr_addr[7:0]),
|
.DIB(16'h0000),
|
.DIB(16'h0000),
|
.ENB(1'b1),
|
.ENB(1'b1),
|
.WEB(1'b0),
|
.WEB(1'b0),
|
.DOB(tbia_dat_o[31:16])
|
.DOB(tbia_dat_o[31:16])
|
);
|
);
|
|
|
RAMB4_S16_S16 tbim_ramb4_s16_0(
|
RAMB4_S16_S16 tbim_ramb4_s16_0(
|
.CLKA(clk),
|
.CLKA(clk),
|
.RSTA(rst),
|
.RSTA(rst),
|
.ADDRA(tb_wadr),
|
.ADDRA(tb_wadr),
|
.DIA(ex_insn[15:0]),
|
.DIA(ex_insn[15:0]),
|
.ENA(1'b1),
|
.ENA(1'b1),
|
.WEA(tb_enw),
|
.WEA(tb_enw),
|
.DOA(),
|
.DOA(),
|
|
|
.CLKB(clk),
|
.CLKB(clk),
|
.RSTB(rst),
|
.RSTB(rst),
|
.ADDRB(spr_addr[7:0]),
|
.ADDRB(spr_addr[7:0]),
|
.DIB(16'h0000),
|
.DIB(16'h0000),
|
.ENB(1'b1),
|
.ENB(1'b1),
|
.WEB(1'b0),
|
.WEB(1'b0),
|
.DOB(tbim_dat_o[15:0])
|
.DOB(tbim_dat_o[15:0])
|
);
|
);
|
|
|
RAMB4_S16_S16 tbim_ramb4_s16_1(
|
RAMB4_S16_S16 tbim_ramb4_s16_1(
|
.CLKA(clk),
|
.CLKA(clk),
|
.RSTA(rst),
|
.RSTA(rst),
|
.ADDRA(tb_wadr),
|
.ADDRA(tb_wadr),
|
.DIA(ex_insn[31:16]),
|
.DIA(ex_insn[31:16]),
|
.ENA(1'b1),
|
.ENA(1'b1),
|
.WEA(tb_enw),
|
.WEA(tb_enw),
|
.DOA(),
|
.DOA(),
|
|
|
.CLKB(clk),
|
.CLKB(clk),
|
.RSTB(rst),
|
.RSTB(rst),
|
.ADDRB(spr_addr[7:0]),
|
.ADDRB(spr_addr[7:0]),
|
.DIB(16'h0000),
|
.DIB(16'h0000),
|
.ENB(1'b1),
|
.ENB(1'b1),
|
.WEB(1'b0),
|
.WEB(1'b0),
|
.DOB(tbim_dat_o[31:16])
|
.DOB(tbim_dat_o[31:16])
|
);
|
);
|
|
|
RAMB4_S16_S16 tbar_ramb4_s16_0(
|
RAMB4_S16_S16 tbar_ramb4_s16_0(
|
.CLKA(clk),
|
.CLKA(clk),
|
.RSTA(rst),
|
.RSTA(rst),
|
.ADDRA(tb_wadr),
|
.ADDRA(tb_wadr),
|
.DIA(rf_dataw[15:0]),
|
.DIA(rf_dataw[15:0]),
|
.ENA(1'b1),
|
.ENA(1'b1),
|
.WEA(tb_enw),
|
.WEA(tb_enw),
|
.DOA(),
|
.DOA(),
|
|
|
.CLKB(clk),
|
.CLKB(clk),
|
.RSTB(rst),
|
.RSTB(rst),
|
.ADDRB(spr_addr[7:0]),
|
.ADDRB(spr_addr[7:0]),
|
.DIB(16'h0000),
|
.DIB(16'h0000),
|
.ENB(1'b1),
|
.ENB(1'b1),
|
.WEB(1'b0),
|
.WEB(1'b0),
|
.DOB(tbar_dat_o[15:0])
|
.DOB(tbar_dat_o[15:0])
|
);
|
);
|
|
|
RAMB4_S16_S16 tbar_ramb4_s16_1(
|
RAMB4_S16_S16 tbar_ramb4_s16_1(
|
.CLKA(clk),
|
.CLKA(clk),
|
.RSTA(rst),
|
.RSTA(rst),
|
.ADDRA(tb_wadr),
|
.ADDRA(tb_wadr),
|
.DIA(rf_dataw[31:16]),
|
.DIA(rf_dataw[31:16]),
|
.ENA(1'b1),
|
.ENA(1'b1),
|
.WEA(tb_enw),
|
.WEA(tb_enw),
|
.DOA(),
|
.DOA(),
|
|
|
.CLKB(clk),
|
.CLKB(clk),
|
.RSTB(rst),
|
.RSTB(rst),
|
.ADDRB(spr_addr[7:0]),
|
.ADDRB(spr_addr[7:0]),
|
.DIB(16'h0000),
|
.DIB(16'h0000),
|
.ENB(1'b1),
|
.ENB(1'b1),
|
.WEB(1'b0),
|
.WEB(1'b0),
|
.DOB(tbar_dat_o[31:16])
|
.DOB(tbar_dat_o[31:16])
|
);
|
);
|
|
|
RAMB4_S16_S16 tbts_ramb4_s16_0(
|
RAMB4_S16_S16 tbts_ramb4_s16_0(
|
.CLKA(clk),
|
.CLKA(clk),
|
.RSTA(rst),
|
.RSTA(rst),
|
.ADDRA(tb_wadr),
|
.ADDRA(tb_wadr),
|
.DIA(tb_timstmp[15:0]),
|
.DIA(tb_timstmp[15:0]),
|
.ENA(1'b1),
|
.ENA(1'b1),
|
.WEA(tb_enw),
|
.WEA(tb_enw),
|
.DOA(),
|
.DOA(),
|
|
|
.CLKB(clk),
|
.CLKB(clk),
|
.RSTB(rst),
|
.RSTB(rst),
|
.ADDRB(spr_addr[7:0]),
|
.ADDRB(spr_addr[7:0]),
|
.DIB(16'h0000),
|
.DIB(16'h0000),
|
.ENB(1'b1),
|
.ENB(1'b1),
|
.WEB(1'b0),
|
.WEB(1'b0),
|
.DOB(tbts_dat_o[15:0])
|
.DOB(tbts_dat_o[15:0])
|
);
|
);
|
|
|
RAMB4_S16_S16 tbts_ramb4_s16_1(
|
RAMB4_S16_S16 tbts_ramb4_s16_1(
|
.CLKA(clk),
|
.CLKA(clk),
|
.RSTA(rst),
|
.RSTA(rst),
|
.ADDRA(tb_wadr),
|
.ADDRA(tb_wadr),
|
.DIA(tb_timstmp[31:16]),
|
.DIA(tb_timstmp[31:16]),
|
.ENA(1'b1),
|
.ENA(1'b1),
|
.WEA(tb_enw),
|
.WEA(tb_enw),
|
.DOA(),
|
.DOA(),
|
|
|
.CLKB(clk),
|
.CLKB(clk),
|
.RSTB(rst),
|
.RSTB(rst),
|
.ADDRB(spr_addr[7:0]),
|
.ADDRB(spr_addr[7:0]),
|
.DIB(16'h0000),
|
.DIB(16'h0000),
|
.ENB(1'b1),
|
.ENB(1'b1),
|
.WEB(1'b0),
|
.WEB(1'b0),
|
.DOB(tbts_dat_o[31:16])
|
.DOB(tbts_dat_o[31:16])
|
);
|
);
|
|
|
`else
|
`else
|
assign tbia_dat_o = 32'h0000_0000;
|
assign tbia_dat_o = 32'h0000_0000;
|
assign tbim_dat_o = 32'h0000_0000;
|
assign tbim_dat_o = 32'h0000_0000;
|
assign tbar_dat_o = 32'h0000_0000;
|
assign tbar_dat_o = 32'h0000_0000;
|
assign tbts_dat_o = 32'h0000_0000;
|
assign tbts_dat_o = 32'h0000_0000;
|
|
|
`endif // OR1200_DU_TB_IMPLEMENTED
|
`endif // OR1200_DU_TB_IMPLEMENTED
|
|
|
`else // OR1200_DU_IMPLEMENTED
|
`else // OR1200_DU_IMPLEMENTED
|
|
|
//
|
//
|
// When DU is not implemented, drive all outputs as would when DU is disabled
|
// When DU is not implemented, drive all outputs as would when DU is disabled
|
//
|
//
|
assign dbg_bp_o = 1'b0;
|
assign dbg_bp_o = 1'b0;
|
assign du_dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
|
assign du_dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
|
|
|
//
|
//
|
// Read DU registers
|
// Read DU registers
|
//
|
//
|
`ifdef OR1200_DU_READREGS
|
`ifdef OR1200_DU_READREGS
|
assign spr_dat_o = 32'h0000_0000;
|
assign spr_dat_o = 32'h0000_0000;
|
`ifdef OR1200_DU_UNUSED_ZERO
|
`ifdef OR1200_DU_UNUSED_ZERO
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
`endif
|
`endif
|
|
|
endmodule
|
endmodule
|
|
|
