//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's DC FSM ////
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//// OR1200's DC FSM ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Data cache state machine ////
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//// Data cache state machine ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// - make it smaller and faster ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2002/03/29 15:16:55 lampret
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// Revision 1.7 2002/03/29 15:16:55 lampret
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// Some of the warnings fixed.
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// Some of the warnings fixed.
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//
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//
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// Revision 1.6 2002/03/28 19:10:40 lampret
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// Revision 1.6 2002/03/28 19:10:40 lampret
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// Optimized cache controller FSM.
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// Optimized cache controller FSM.
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//
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//
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// Revision 1.1.1.1 2002/03/21 16:55:45 lampret
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// Revision 1.1.1.1 2002/03/21 16:55:45 lampret
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// First import of the "new" XESS XSV environment.
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// First import of the "new" XESS XSV environment.
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//
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//
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//
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//
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// Revision 1.5 2002/02/11 04:33:17 lampret
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// Revision 1.5 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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//
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// Revision 1.4 2002/02/01 19:56:54 lampret
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// Revision 1.4 2002/02/01 19:56:54 lampret
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// Fixed combinational loops.
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// Fixed combinational loops.
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//
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//
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// Revision 1.3 2002/01/28 01:15:59 lampret
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// Revision 1.3 2002/01/28 01:15:59 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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//
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// Revision 1.9 2001/10/21 17:57:16 lampret
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// Revision 1.9 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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//
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// Revision 1.8 2001/10/19 23:28:46 lampret
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// Revision 1.8 2001/10/19 23:28:46 lampret
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// Fixed some synthesis warnings. Configured with caches and MMUs.
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// Fixed some synthesis warnings. Configured with caches and MMUs.
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//
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//
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// Revision 1.7 2001/10/14 13:12:09 lampret
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// Revision 1.7 2001/10/14 13:12:09 lampret
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// MP3 version.
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// MP3 version.
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//
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//
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// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
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// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
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// no message
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// no message
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//
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//
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// Revision 1.2 2001/08/09 13:39:33 lampret
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// Revision 1.2 2001/08/09 13:39:33 lampret
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// Major clean-up.
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// Major clean-up.
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//
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//
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Development version of RTL. Libraries are missing.
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// Development version of RTL. Libraries are missing.
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//
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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|
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`define OR1200_DCFSM_IDLE 3'd0
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`define OR1200_DCFSM_IDLE 3'd0
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`define OR1200_DCFSM_CLOAD 3'd1
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`define OR1200_DCFSM_CLOAD 3'd1
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`define OR1200_DCFSM_LREFILL3 3'd2
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`define OR1200_DCFSM_LREFILL3 3'd2
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`define OR1200_DCFSM_CSTORE 3'd3
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`define OR1200_DCFSM_CSTORE 3'd3
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`define OR1200_DCFSM_SREFILL4 3'd4
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`define OR1200_DCFSM_SREFILL4 3'd4
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//
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//
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// Data cache FSM for cache line of 16 bytes (4x singleword)
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// Data cache FSM for cache line of 16 bytes (4x singleword)
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//
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//
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module or1200_dc_fsm(
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module or1200_dc_fsm(
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// Clock and reset
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// Clock and reset
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clk, rst,
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clk, rst,
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|
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// Internal i/f to top level DC
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// Internal i/f to top level DC
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dc_en, dcqmem_cycstb_i, dcqmem_ci_i, dcqmem_we_i, dcqmem_sel_i,
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dc_en, dcqmem_cycstb_i, dcqmem_ci_i, dcqmem_we_i, dcqmem_sel_i,
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tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
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tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
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dcram_we, biu_read, biu_write, first_hit_ack, first_miss_ack, first_miss_err,
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dcram_we, biu_read, biu_write, first_hit_ack, first_miss_ack, first_miss_err,
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burst, tag_we, dc_addr
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burst, tag_we, dc_addr
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);
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);
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//
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//
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// I/O
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// I/O
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//
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//
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input clk;
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input clk;
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input rst;
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input rst;
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input dc_en;
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input dc_en;
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input dcqmem_cycstb_i;
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input dcqmem_cycstb_i;
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input dcqmem_ci_i;
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input dcqmem_ci_i;
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input dcqmem_we_i;
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input dcqmem_we_i;
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input [3:0] dcqmem_sel_i;
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input [3:0] dcqmem_sel_i;
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input tagcomp_miss;
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input tagcomp_miss;
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input biudata_valid;
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input biudata_valid;
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input biudata_error;
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input biudata_error;
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input [31:0] start_addr;
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input [31:0] start_addr;
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output [31:0] saved_addr;
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output [31:0] saved_addr;
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output [3:0] dcram_we;
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output [3:0] dcram_we;
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output biu_read;
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output biu_read;
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output biu_write;
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output biu_write;
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output first_hit_ack;
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output first_hit_ack;
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output first_miss_ack;
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output first_miss_ack;
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output first_miss_err;
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output first_miss_err;
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output burst;
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output burst;
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output tag_we;
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output tag_we;
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output [31:0] dc_addr;
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output [31:0] dc_addr;
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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reg [31:0] saved_addr_r;
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reg [31:0] saved_addr_r;
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reg [2:0] state;
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reg [2:0] state;
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reg [2:0] cnt;
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reg [2:0] cnt;
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reg hitmiss_eval;
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reg hitmiss_eval;
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reg store;
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reg store;
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reg load;
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reg load;
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reg cache_inhibit;
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reg cache_inhibit;
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wire first_store_hit_ack;
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wire first_store_hit_ack;
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//
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//
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// Generate of DCRAM write enables
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// Generate of DCRAM write enables
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//
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//
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assign dcram_we = {4{load & biudata_valid & !cache_inhibit}} | {4{first_store_hit_ack}} & dcqmem_sel_i;
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assign dcram_we = {4{load & biudata_valid & !cache_inhibit}} | {4{first_store_hit_ack}} & dcqmem_sel_i;
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assign tag_we = biu_read & biudata_valid & !cache_inhibit;
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assign tag_we = biu_read & biudata_valid & !cache_inhibit;
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|
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//
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//
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// BIU read and write
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// BIU read and write
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//
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//
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assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
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assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
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assign biu_write = store;
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assign biu_write = store;
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|
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assign dc_addr = (biu_read | biu_write) & !hitmiss_eval ? saved_addr : start_addr;
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assign dc_addr = (biu_read | biu_write) & !hitmiss_eval ? saved_addr : start_addr;
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assign saved_addr = saved_addr_r;
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assign saved_addr = saved_addr_r;
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|
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//
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//
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// Assert for cache hit first word ready
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// Assert for cache hit first word ready
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// Assert for store cache hit first word ready
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// Assert for store cache hit first word ready
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// Assert for cache miss first word stored/loaded OK
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// Assert for cache miss first word stored/loaded OK
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// Assert for cache miss first word stored/loaded with an error
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// Assert for cache miss first word stored/loaded with an error
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//
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//
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assign first_hit_ack = (state == `OR1200_DCFSM_CLOAD) & !tagcomp_miss & !cache_inhibit & !dcqmem_ci_i | first_store_hit_ack;
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assign first_hit_ack = (state == `OR1200_DCFSM_CLOAD) & !tagcomp_miss & !cache_inhibit & !dcqmem_ci_i | first_store_hit_ack;
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assign first_store_hit_ack = (state == `OR1200_DCFSM_CSTORE) & !tagcomp_miss & biudata_valid & !cache_inhibit & !dcqmem_ci_i;
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assign first_store_hit_ack = (state == `OR1200_DCFSM_CSTORE) & !tagcomp_miss & biudata_valid & !cache_inhibit & !dcqmem_ci_i;
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assign first_miss_ack = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_valid;
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assign first_miss_ack = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_valid;
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assign first_miss_err = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_error;
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assign first_miss_err = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_error;
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|
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//
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//
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// Assert burst when doing reload of complete cache line
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// Assert burst when doing reload of complete cache line
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//
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//
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assign burst = (state == `OR1200_DCFSM_CLOAD) & tagcomp_miss & !cache_inhibit
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assign burst = (state == `OR1200_DCFSM_CLOAD) & tagcomp_miss & !cache_inhibit
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| (state == `OR1200_DCFSM_LREFILL3)
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| (state == `OR1200_DCFSM_LREFILL3)
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`ifdef OR1200_DC_STORE_REFILL
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`ifdef OR1200_DC_STORE_REFILL
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| (state == `OR1200_DCFSM_SREFILL4)
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| (state == `OR1200_DCFSM_SREFILL4)
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`endif
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`endif
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;
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;
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//
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//
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// Main DC FSM
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// Main DC FSM
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//
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//
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always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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if (rst) begin
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state <= #1 `OR1200_DCFSM_IDLE;
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state <= #1 `OR1200_DCFSM_IDLE;
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saved_addr_r <= #1 32'b0;
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saved_addr_r <= #1 32'b0;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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store <= #1 1'b0;
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store <= #1 1'b0;
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load <= #1 1'b0;
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load <= #1 1'b0;
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cnt <= #1 3'b000;
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cnt <= #1 3'b000;
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cache_inhibit <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
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end
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else
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else
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case (state) // synopsys parallel_case
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case (state) // synopsys parallel_case
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`OR1200_DCFSM_IDLE :
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`OR1200_DCFSM_IDLE :
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if (dc_en & dcqmem_cycstb_i & dcqmem_we_i) begin // store
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if (dc_en & dcqmem_cycstb_i & dcqmem_we_i) begin // store
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state <= #1 `OR1200_DCFSM_CSTORE;
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state <= #1 `OR1200_DCFSM_CSTORE;
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saved_addr_r <= #1 start_addr;
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saved_addr_r <= #1 start_addr;
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hitmiss_eval <= #1 1'b1;
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hitmiss_eval <= #1 1'b1;
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store <= #1 1'b1;
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store <= #1 1'b1;
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load <= #1 1'b0;
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load <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
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end
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else if (dc_en & dcqmem_cycstb_i) begin // load
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else if (dc_en & dcqmem_cycstb_i) begin // load
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state <= #1 `OR1200_DCFSM_CLOAD;
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state <= #1 `OR1200_DCFSM_CLOAD;
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saved_addr_r <= #1 start_addr;
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saved_addr_r <= #1 start_addr;
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hitmiss_eval <= #1 1'b1;
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hitmiss_eval <= #1 1'b1;
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store <= #1 1'b0;
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store <= #1 1'b0;
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load <= #1 1'b1;
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load <= #1 1'b1;
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cache_inhibit <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
|
end
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else begin // idle
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else begin // idle
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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store <= #1 1'b0;
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store <= #1 1'b0;
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load <= #1 1'b0;
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load <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
|
end
|
end
|
`OR1200_DCFSM_CLOAD: begin // load
|
`OR1200_DCFSM_CLOAD: begin // load
|
if (dcqmem_cycstb_i & dcqmem_ci_i)
|
if (dcqmem_cycstb_i & dcqmem_ci_i)
|
cache_inhibit <= #1 1'b1;
|
cache_inhibit <= #1 1'b1;
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if (hitmiss_eval)
|
if (hitmiss_eval)
|
saved_addr_r[31:13] <= #1 start_addr[31:13];
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saved_addr_r[31:13] <= #1 start_addr[31:13];
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if ((hitmiss_eval & !dcqmem_cycstb_i) || // load aborted (usually caused by DMMU)
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if ((hitmiss_eval & !dcqmem_cycstb_i) || // load aborted (usually caused by DMMU)
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(biudata_error) || // load terminated with an error
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(biudata_error) || // load terminated with an error
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((cache_inhibit | dcqmem_ci_i) & biudata_valid)) begin // load from cache-inhibited area
|
((cache_inhibit | dcqmem_ci_i) & biudata_valid)) begin // load from cache-inhibited area
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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load <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
|
end
|
end
|
else if (tagcomp_miss & biudata_valid) begin // load missed, finish current external load and refill
|
else if (tagcomp_miss & biudata_valid) begin // load missed, finish current external load and refill
|
state <= #1 `OR1200_DCFSM_LREFILL3;
|
state <= #1 `OR1200_DCFSM_LREFILL3;
|
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
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saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
|
hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
|
cnt <= #1 `OR1200_DCLS-2;
|
cnt <= #1 `OR1200_DCLS-2;
|
cache_inhibit <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
end
|
end
|
else if (!tagcomp_miss & !dcqmem_ci_i) begin // load hit, finish immediately
|
else if (!tagcomp_miss & !dcqmem_ci_i) begin // load hit, finish immediately
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
|
load <= #1 1'b0;
|
load <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
end
|
end
|
else // load in-progress
|
else // load in-progress
|
hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
|
end
|
end
|
`OR1200_DCFSM_LREFILL3 : begin
|
`OR1200_DCFSM_LREFILL3 : begin
|
if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
|
if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
|
cnt <= #1 cnt - 1'd1;
|
cnt <= #1 cnt - 1'd1;
|
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
|
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
|
end
|
end
|
else if (biudata_valid) begin // last load of line refill
|
else if (biudata_valid) begin // last load of line refill
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
load <= #1 1'b0;
|
load <= #1 1'b0;
|
end
|
end
|
end
|
end
|
`OR1200_DCFSM_CSTORE: begin // store
|
`OR1200_DCFSM_CSTORE: begin // store
|
if (dcqmem_cycstb_i & dcqmem_ci_i)
|
if (dcqmem_cycstb_i & dcqmem_ci_i)
|
cache_inhibit <= #1 1'b1;
|
cache_inhibit <= #1 1'b1;
|
if (hitmiss_eval)
|
if (hitmiss_eval)
|
saved_addr_r[31:13] <= #1 start_addr[31:13];
|
saved_addr_r[31:13] <= #1 start_addr[31:13];
|
if ((hitmiss_eval & !dcqmem_cycstb_i) || // store aborted (usually caused by DMMU)
|
if ((hitmiss_eval & !dcqmem_cycstb_i) || // store aborted (usually caused by DMMU)
|
(biudata_error) || // store terminated with an error
|
(biudata_error) || // store terminated with an error
|
((cache_inhibit | dcqmem_ci_i) & biudata_valid)) begin // store to cache-inhibited area
|
((cache_inhibit | dcqmem_ci_i) & biudata_valid)) begin // store to cache-inhibited area
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
|
store <= #1 1'b0;
|
store <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
end
|
end
|
`ifdef OR1200_DC_STORE_REFILL
|
`ifdef OR1200_DC_STORE_REFILL
|
else if (tagcomp_miss & biudata_valid) begin // store missed, finish write-through and do load refill
|
else if (tagcomp_miss & biudata_valid) begin // store missed, finish write-through and do load refill
|
state <= #1 `OR1200_DCFSM_SREFILL4;
|
state <= #1 `OR1200_DCFSM_SREFILL4;
|
hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
|
store <= #1 1'b0;
|
store <= #1 1'b0;
|
load <= #1 1'b1;
|
load <= #1 1'b1;
|
cnt <= #1 `OR1200_DCLS-1;
|
cnt <= #1 `OR1200_DCLS-1;
|
cache_inhibit <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
end
|
end
|
`endif
|
`endif
|
else if (biudata_valid) begin // store hit, finish write-through
|
else if (biudata_valid) begin // store hit, finish write-through
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
|
store <= #1 1'b0;
|
store <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
end
|
end
|
else // store write-through in-progress
|
else // store write-through in-progress
|
hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
|
end
|
end
|
`ifdef OR1200_DC_STORE_REFILL
|
`ifdef OR1200_DC_STORE_REFILL
|
`OR1200_DCFSM_SREFILL4 : begin
|
`OR1200_DCFSM_SREFILL4 : begin
|
if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
|
if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
|
cnt <= #1 cnt - 1'd1;
|
cnt <= #1 cnt - 1'd1;
|
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
|
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
|
end
|
end
|
else if (biudata_valid) begin // last load of line refill
|
else if (biudata_valid) begin // last load of line refill
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
load <= #1 1'b0;
|
load <= #1 1'b0;
|
end
|
end
|
end
|
end
|
`endif
|
`endif
|
default:
|
default:
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
endcase
|
endcase
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
