//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Generic Double-Port Synchronous RAM ////
|
//// Generic Double-Port Synchronous RAM ////
|
//// ////
|
//// ////
|
//// This file is part of memory library available from ////
|
//// This file is part of memory library available from ////
|
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
|
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// This block is a wrapper with common double-port ////
|
//// This block is a wrapper with common double-port ////
|
//// synchronous memory interface for different ////
|
//// synchronous memory interface for different ////
|
//// types of ASIC and FPGA RAMs. Beside universal memory ////
|
//// types of ASIC and FPGA RAMs. Beside universal memory ////
|
//// interface it also provides behavioral model of generic ////
|
//// interface it also provides behavioral model of generic ////
|
//// double-port synchronous RAM. ////
|
//// double-port synchronous RAM. ////
|
//// It should be used in all OPENCORES designs that want to be ////
|
//// It should be used in all OPENCORES designs that want to be ////
|
//// portable accross different target technologies and ////
|
//// portable accross different target technologies and ////
|
//// independent of target memory. ////
|
//// independent of target memory. ////
|
//// ////
|
//// ////
|
//// Supported ASIC RAMs are: ////
|
//// Supported ASIC RAMs are: ////
|
//// - Artisan Double-Port Sync RAM ////
|
//// - Artisan Double-Port Sync RAM ////
|
//// - Avant! Two-Port Sync RAM (*) ////
|
//// - Avant! Two-Port Sync RAM (*) ////
|
//// - Virage 2-port Sync RAM ////
|
//// - Virage 2-port Sync RAM ////
|
//// ////
|
//// ////
|
//// Supported FPGA RAMs are: ////
|
//// Supported FPGA RAMs are: ////
|
//// - Xilinx Virtex RAMB4_S16_S16 ////
|
//// - Xilinx Virtex RAMB4_S16_S16 ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - fix Avant! ////
|
//// - fix Avant! ////
|
//// - xilinx rams need external tri-state logic ////
|
//// - xilinx rams need external tri-state logic ////
|
//// - add additional RAMs (Altera, VS etc) ////
|
//// - add additional RAMs (Altera, VS etc) ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Damjan Lampret, lampret@opencores.org ////
|
//// - Damjan Lampret, lampret@opencores.org ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.1 2002/01/03 08:16:15 lampret
|
|
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
|
|
//
|
// Revision 1.10 2001/11/05 14:48:00 lampret
|
// Revision 1.10 2001/11/05 14:48:00 lampret
|
// Added missing endif
|
// Added missing endif
|
//
|
//
|
// Revision 1.9 2001/11/02 18:57:14 lampret
|
// Revision 1.9 2001/11/02 18:57:14 lampret
|
// Modified virtual silicon instantiations.
|
// Modified virtual silicon instantiations.
|
//
|
//
|
// Revision 1.8 2001/10/22 19:39:56 lampret
|
// Revision 1.8 2001/10/22 19:39:56 lampret
|
// Fixed parameters in generic sprams.
|
// Fixed parameters in generic sprams.
|
//
|
//
|
// Revision 1.7 2001/10/21 17:57:16 lampret
|
// Revision 1.7 2001/10/21 17:57:16 lampret
|
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
|
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
|
//
|
//
|
// Revision 1.6 2001/10/14 13:12:09 lampret
|
// Revision 1.6 2001/10/14 13:12:09 lampret
|
// MP3 version.
|
// MP3 version.
|
//
|
//
|
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
|
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
|
// no message
|
// no message
|
//
|
//
|
// Revision 1.1 2001/08/09 13:39:33 lampret
|
// Revision 1.1 2001/08/09 13:39:33 lampret
|
// Major clean-up.
|
// Major clean-up.
|
//
|
//
|
// Revision 1.2 2001/07/30 05:38:02 lampret
|
// Revision 1.2 2001/07/30 05:38:02 lampret
|
// Adding empty directories required by HDL coding guidelines
|
// Adding empty directories required by HDL coding guidelines
|
//
|
//
|
//
|
//
|
|
|
// synopsys translate_off
|
// synopsys translate_off
|
`include "timescale.v"
|
`include "timescale.v"
|
// synopsys translate_on
|
// synopsys translate_on
|
`include "or1200_defines.v"
|
`include "or1200_defines.v"
|
|
|
module or1200_dpram_32x32(
|
module or1200_dpram_32x32(
|
// Generic synchronous double-port RAM interface
|
// Generic synchronous double-port RAM interface
|
clk_a, rst_a, ce_a, oe_a, addr_a, do_a,
|
clk_a, rst_a, ce_a, oe_a, addr_a, do_a,
|
clk_b, rst_b, ce_b, we_b, addr_b, di_b
|
clk_b, rst_b, ce_b, we_b, addr_b, di_b
|
);
|
);
|
|
|
//
|
//
|
// Default address and data buses width
|
// Default address and data buses width
|
//
|
//
|
parameter aw = 5;
|
parameter aw = 5;
|
parameter dw = 32;
|
parameter dw = 32;
|
|
|
//
|
//
|
// Generic synchronous double-port RAM interface
|
// Generic synchronous double-port RAM interface
|
//
|
//
|
input clk_a; // Clock
|
input clk_a; // Clock
|
input rst_a; // Reset
|
input rst_a; // Reset
|
input ce_a; // Chip enable input
|
input ce_a; // Chip enable input
|
input oe_a; // Output enable input
|
input oe_a; // Output enable input
|
input [aw-1:0] addr_a; // address bus inputs
|
input [aw-1:0] addr_a; // address bus inputs
|
output [dw-1:0] do_a; // output data bus
|
output [dw-1:0] do_a; // output data bus
|
input clk_b; // Clock
|
input clk_b; // Clock
|
input rst_b; // Reset
|
input rst_b; // Reset
|
input ce_b; // Chip enable input
|
input ce_b; // Chip enable input
|
input we_b; // Write enable input
|
input we_b; // Write enable input
|
input [aw-1:0] addr_b; // address bus inputs
|
input [aw-1:0] addr_b; // address bus inputs
|
input [dw-1:0] di_b; // input data bus
|
input [dw-1:0] di_b; // input data bus
|
|
|
//
|
//
|
// Internal wires and registers
|
// Internal wires and registers
|
//
|
//
|
|
|
`ifdef OR1200_ARTISAN_SDP
|
`ifdef OR1200_ARTISAN_SDP
|
|
|
//
|
//
|
// Instantiation of ASIC memory:
|
// Instantiation of ASIC memory:
|
//
|
//
|
// Artisan Synchronous Double-Port RAM (ra2sh)
|
// Artisan Synchronous Double-Port RAM (ra2sh)
|
//
|
//
|
`ifdef UNUSED
|
`ifdef UNUSED
|
art_hsdp_32x32 #(dw, 1<<aw, aw) artisan_sdp(
|
art_hsdp_32x32 #(dw, 1<<aw, aw) artisan_sdp(
|
`else
|
`else
|
art_hsdp_32x32 artisan_sdp(
|
art_hsdp_32x32 artisan_sdp(
|
`endif
|
`endif
|
.qa(do_a),
|
.qa(do_a),
|
.clka(clk_a),
|
.clka(clk_a),
|
.cena(~ce_a),
|
.cena(~ce_a),
|
.wena(1'b1),
|
.wena(1'b1),
|
.aa(addr_a),
|
.aa(addr_a),
|
.da(32'h00000000),
|
.da(32'h00000000),
|
.oena(~oe_a),
|
.oena(~oe_a),
|
.qb(),
|
.qb(),
|
.clkb(clk_b),
|
.clkb(clk_b),
|
.cenb(~ce_b),
|
.cenb(~ce_b),
|
.wenb(~we_b),
|
.wenb(~we_b),
|
.ab(addr_b),
|
.ab(addr_b),
|
.db(di_b),
|
.db(di_b),
|
.oenb(1'b1)
|
.oenb(1'b1)
|
);
|
);
|
|
|
`else
|
`else
|
|
|
`ifdef OR1200_AVANT_ATP
|
`ifdef OR1200_AVANT_ATP
|
|
|
//
|
//
|
// Instantiation of ASIC memory:
|
// Instantiation of ASIC memory:
|
//
|
//
|
// Avant! Asynchronous Two-Port RAM
|
// Avant! Asynchronous Two-Port RAM
|
//
|
//
|
avant_atp avant_atp(
|
avant_atp avant_atp(
|
.web(~we),
|
.web(~we),
|
.reb(),
|
.reb(),
|
.oeb(~oe),
|
.oeb(~oe),
|
.rcsb(),
|
.rcsb(),
|
.wcsb(),
|
.wcsb(),
|
.ra(addr),
|
.ra(addr),
|
.wa(addr),
|
.wa(addr),
|
.di(di),
|
.di(di),
|
.do(do)
|
.do(do)
|
);
|
);
|
|
|
`else
|
`else
|
|
|
`ifdef OR1200_VIRAGE_STP
|
`ifdef OR1200_VIRAGE_STP
|
|
|
//
|
//
|
// Instantiation of ASIC memory:
|
// Instantiation of ASIC memory:
|
//
|
//
|
// Virage Synchronous 2-port R/W RAM
|
// Virage Synchronous 2-port R/W RAM
|
//
|
//
|
virage_stp virage_stp(
|
virage_stp virage_stp(
|
.QA(do_a),
|
.QA(do_a),
|
.QB(),
|
.QB(),
|
|
|
.ADRA(addr_a),
|
.ADRA(addr_a),
|
.DA(32'h00000000),
|
.DA(32'h00000000),
|
.WEA(1'b0),
|
.WEA(1'b0),
|
.OEA(oe_a),
|
.OEA(oe_a),
|
.MEA(ce_a),
|
.MEA(ce_a),
|
.CLKA(clk_a),
|
.CLKA(clk_a),
|
|
|
.ADRB(addr_b),
|
.ADRB(addr_b),
|
.DB(di_b),
|
.DB(di_b),
|
.WEB(we_b),
|
.WEB(we_b),
|
.OEB(1'b1),
|
.OEB(1'b1),
|
.MEB(ce_b),
|
.MEB(ce_b),
|
.CLKB(clk_b)
|
.CLKB(clk_b)
|
);
|
);
|
|
|
`else
|
`else
|
|
|
`ifdef OR1200_VIRTUALSILICON_STP
|
`ifdef OR1200_VIRTUALSILICON_STP
|
|
|
//
|
//
|
// Instantiation of ASIC memory:
|
// Instantiation of ASIC memory:
|
//
|
//
|
// Virtual Silicon Two-port R/W SRAM
|
// Virtual Silicon Two-port R/W SRAM
|
//
|
//
|
`ifdef UNUSED
|
`ifdef UNUSED
|
vs_hdtp_32x32 #(1<<aw, aw-1, dw-1) vs_ssp(
|
vs_hdtp_32x32 #(1<<aw, aw-1, dw-1) vs_ssp(
|
`else
|
`else
|
vs_hdtp_32x32 vs_ssp(
|
vs_hdtp_32x32 vs_ssp(
|
`endif
|
`endif
|
.RCK(clk_a),
|
.RCK(clk_a),
|
.REN(~ce_a),
|
.REN(~ce_a),
|
.OEN(~oe_a),
|
.OEN(~oe_a),
|
.RADR(addr_a),
|
.RADR(addr_a),
|
.DI(di_b),
|
.DI(di_b),
|
.WCK(clk_b),
|
.WCK(clk_b),
|
.WEN(~ce_b),
|
.WEN(~ce_b),
|
.WADR(addr_b),
|
.WADR(addr_b),
|
.DOUT(do_a)
|
.DOUT(do_a)
|
);
|
);
|
|
|
`else
|
`else
|
|
|
`ifdef OR1200_XILINX_RAM32X1D
|
`ifdef OR1200_XILINX_RAM32X1D
|
|
|
//
|
//
|
// Instantiation of FPGA memory:
|
// Instantiation of FPGA memory:
|
//
|
//
|
// Virtex/Spartan2
|
// Virtex/Spartan2
|
//
|
//
|
|
|
//
|
//
|
// Block 0
|
// Block 0
|
//
|
//
|
xcv_ram32x8d xcv_ram32x8d_0 (
|
or1200_xcv_ram32x8d xcv_ram32x8d_0 (
|
.DPO(do_a[7:0]),
|
.DPO(do_a[7:0]),
|
.SPO(),
|
.SPO(),
|
.A(addr_b),
|
.A(addr_b),
|
.D(di_b[7:0]),
|
.D(di_b[7:0]),
|
.DPRA(addr_a),
|
.DPRA(addr_a),
|
.WCLK(clk_b),
|
.WCLK(clk_b),
|
.WE(we_b)
|
.WE(we_b)
|
);
|
);
|
|
|
//
|
//
|
// Block 1
|
// Block 1
|
//
|
//
|
xcv_ram32x8d xcv_ram32x8d_1 (
|
or1200_xcv_ram32x8d xcv_ram32x8d_1 (
|
.DPO(do_a[15:8]),
|
.DPO(do_a[15:8]),
|
.SPO(),
|
.SPO(),
|
.A(addr_b),
|
.A(addr_b),
|
.D(di_b[15:8]),
|
.D(di_b[15:8]),
|
.DPRA(addr_a),
|
.DPRA(addr_a),
|
.WCLK(clk_b),
|
.WCLK(clk_b),
|
.WE(we_b)
|
.WE(we_b)
|
);
|
);
|
|
|
|
|
//
|
//
|
// Block 2
|
// Block 2
|
//
|
//
|
xcv_ram32x8d xcv_ram32x8d_2 (
|
or1200_xcv_ram32x8d xcv_ram32x8d_2 (
|
.DPO(do_a[23:16]),
|
.DPO(do_a[23:16]),
|
.SPO(),
|
.SPO(),
|
.A(addr_b),
|
.A(addr_b),
|
.D(di_b[23:16]),
|
.D(di_b[23:16]),
|
.DPRA(addr_a),
|
.DPRA(addr_a),
|
.WCLK(clk_b),
|
.WCLK(clk_b),
|
.WE(we_b)
|
.WE(we_b)
|
);
|
);
|
|
|
//
|
//
|
// Block 3
|
// Block 3
|
//
|
//
|
xcv_ram32x8d xcv_ram32x8d_3 (
|
or1200_xcv_ram32x8d xcv_ram32x8d_3 (
|
.DPO(do_a[31:24]),
|
.DPO(do_a[31:24]),
|
.SPO(),
|
.SPO(),
|
.A(addr_b),
|
.A(addr_b),
|
.D(di_b[31:24]),
|
.D(di_b[31:24]),
|
.DPRA(addr_a),
|
.DPRA(addr_a),
|
.WCLK(clk_b),
|
.WCLK(clk_b),
|
.WE(we_b)
|
.WE(we_b)
|
);
|
);
|
|
|
`else
|
`else
|
|
|
`ifdef OR1200_XILINX_RAMB4
|
`ifdef OR1200_XILINX_RAMB4
|
|
|
//
|
//
|
// Instantiation of FPGA memory:
|
// Instantiation of FPGA memory:
|
//
|
//
|
// Virtex/Spartan2
|
// Virtex/Spartan2
|
//
|
//
|
|
|
//
|
//
|
// Block 0
|
// Block 0
|
//
|
//
|
RAMB4_S16_S16 ramb4_s16_0(
|
RAMB4_S16_S16 ramb4_s16_0(
|
.CLKA(clk_a),
|
.CLKA(clk_a),
|
.RSTA(rst_a),
|
.RSTA(rst_a),
|
.ADDRA({3'b000, addr_a}),
|
.ADDRA({3'b000, addr_a}),
|
.DIA(16'h0000),
|
.DIA(16'h0000),
|
.ENA(ce_a),
|
.ENA(ce_a),
|
.WEA(1'b0),
|
.WEA(1'b0),
|
.DOA(do_a[15:0]),
|
.DOA(do_a[15:0]),
|
|
|
.CLKB(clk_b),
|
.CLKB(clk_b),
|
.RSTB(rst_b),
|
.RSTB(rst_b),
|
.ADDRB({3'b000, addr_b}),
|
.ADDRB({3'b000, addr_b}),
|
.DIB(di_b[15:0]),
|
.DIB(di_b[15:0]),
|
.ENB(ce_b),
|
.ENB(ce_b),
|
.WEB(we_b),
|
.WEB(we_b),
|
.DOB()
|
.DOB()
|
);
|
);
|
|
|
//
|
//
|
// Block 1
|
// Block 1
|
//
|
//
|
RAMB4_S16_S16 ramb4_s16_1(
|
RAMB4_S16_S16 ramb4_s16_1(
|
.CLKA(clk_a),
|
.CLKA(clk_a),
|
.RSTA(rst_a),
|
.RSTA(rst_a),
|
.ADDRA({3'b000, addr_a}),
|
.ADDRA({3'b000, addr_a}),
|
.DIA(16'h0000),
|
.DIA(16'h0000),
|
.ENA(ce_a),
|
.ENA(ce_a),
|
.WEA(1'b0),
|
.WEA(1'b0),
|
.DOA(do_a[31:16]),
|
.DOA(do_a[31:16]),
|
|
|
.CLKB(clk_b),
|
.CLKB(clk_b),
|
.RSTB(rst_b),
|
.RSTB(rst_b),
|
.ADDRB({3'b000, addr_b}),
|
.ADDRB({3'b000, addr_b}),
|
.DIB(di_b[31:16]),
|
.DIB(di_b[31:16]),
|
.ENB(ce_b),
|
.ENB(ce_b),
|
.WEB(we_b),
|
.WEB(we_b),
|
.DOB()
|
.DOB()
|
);
|
);
|
|
|
`else
|
`else
|
|
|
//
|
//
|
// Generic double-port synchronous RAM model
|
// Generic double-port synchronous RAM model
|
//
|
//
|
|
|
//
|
//
|
// Generic RAM's registers and wires
|
// Generic RAM's registers and wires
|
//
|
//
|
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
|
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
|
reg [dw-1:0] do_reg; // RAM data output register
|
reg [dw-1:0] do_reg; // RAM data output register
|
|
|
//
|
//
|
// Data output drivers
|
// Data output drivers
|
//
|
//
|
assign do_a = (oe_a) ? do_reg : {dw{1'bz}};
|
assign do_a = (oe_a) ? do_reg : {dw{1'bz}};
|
|
|
//
|
//
|
// RAM read
|
// RAM read
|
//
|
//
|
always @(posedge clk_a)
|
always @(posedge clk_a)
|
if (ce_a)
|
if (ce_a)
|
do_reg <= #1 mem[addr_a];
|
do_reg <= #1 mem[addr_a];
|
|
|
//
|
//
|
// RAM write
|
// RAM write
|
//
|
//
|
always @(posedge clk_b)
|
always @(posedge clk_b)
|
if (ce_b && we_b)
|
if (ce_b && we_b)
|
mem[addr_b] <= #1 di_b;
|
mem[addr_b] <= #1 di_b;
|
|
|
`endif // !OR1200_XILINX_RAMB4_S16_S16
|
`endif // !OR1200_XILINX_RAMB4_S16_S16
|
`endif // !OR1200_XILINX_RAM32X1D
|
`endif // !OR1200_XILINX_RAM32X1D
|
`endif // !OR1200_VIRTUALSILICON_SSP
|
`endif // !OR1200_VIRTUALSILICON_SSP
|
`endif // !OR1200_VIRAGE_STP
|
`endif // !OR1200_VIRAGE_STP
|
`endif // !OR1200_AVANT_ATP
|
`endif // !OR1200_AVANT_ATP
|
`endif // !OR1200_ARTISAN_SDP
|
`endif // !OR1200_ARTISAN_SDP
|
|
|
endmodule
|
endmodule
|
|
|
