//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's ALU ////
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//// OR1200's ALU ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// ALU ////
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//// ALU ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// - make it smaller and faster ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
|
// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.10 2002/09/08 05:52:16 lampret
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// Revision 1.10 2002/09/08 05:52:16 lampret
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// Added optional l.div/l.divu insns. By default they are disabled.
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// Added optional l.div/l.divu insns. By default they are disabled.
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//
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//
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// Revision 1.9 2002/09/07 19:16:10 lampret
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// Revision 1.9 2002/09/07 19:16:10 lampret
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// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].
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// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].
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//
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//
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// Revision 1.8 2002/09/07 05:42:02 lampret
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// Revision 1.8 2002/09/07 05:42:02 lampret
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// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
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// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
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//
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//
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// Revision 1.7 2002/09/03 22:28:21 lampret
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// Revision 1.7 2002/09/03 22:28:21 lampret
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// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
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// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
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//
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//
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// Revision 1.6 2002/03/29 16:40:10 lampret
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// Revision 1.6 2002/03/29 16:40:10 lampret
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// Added a directive to ignore signed division variables that are only used in simulation.
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// Added a directive to ignore signed division variables that are only used in simulation.
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//
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//
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// Revision 1.5 2002/03/29 16:33:59 lampret
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// Revision 1.5 2002/03/29 16:33:59 lampret
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// Added again just recently removed full_case directive
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// Added again just recently removed full_case directive
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//
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//
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// Revision 1.4 2002/03/29 15:16:53 lampret
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// Revision 1.4 2002/03/29 15:16:53 lampret
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// Some of the warnings fixed.
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// Some of the warnings fixed.
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//
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//
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// Revision 1.3 2002/01/28 01:15:59 lampret
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// Revision 1.3 2002/01/28 01:15:59 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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//
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// Revision 1.10 2001/11/12 01:45:40 lampret
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// Revision 1.10 2001/11/12 01:45:40 lampret
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// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
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// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
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//
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//
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// Revision 1.9 2001/10/21 17:57:16 lampret
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// Revision 1.9 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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//
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// Revision 1.8 2001/10/19 23:28:45 lampret
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// Revision 1.8 2001/10/19 23:28:45 lampret
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// Fixed some synthesis warnings. Configured with caches and MMUs.
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// Fixed some synthesis warnings. Configured with caches and MMUs.
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//
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//
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// Revision 1.7 2001/10/14 13:12:09 lampret
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// Revision 1.7 2001/10/14 13:12:09 lampret
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// MP3 version.
|
// MP3 version.
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//
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//
|
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
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// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
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// no message
|
// no message
|
//
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//
|
// Revision 1.2 2001/08/09 13:39:33 lampret
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// Revision 1.2 2001/08/09 13:39:33 lampret
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// Major clean-up.
|
// Major clean-up.
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//
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//
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Development version of RTL. Libraries are missing.
|
// Development version of RTL. Libraries are missing.
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//
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//
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//
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//
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|
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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|
|
module or1200_alu(
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module or1200_alu(
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a, b, mult_mac_result, macrc_op,
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a, b, mult_mac_result, macrc_op,
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alu_op, shrot_op, comp_op,
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alu_op, shrot_op, comp_op,
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result, flagforw, flag_we,
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result, flagforw, flag_we,
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cyforw, cy_we, carry
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cyforw, cy_we, carry
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);
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);
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|
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parameter width = `OR1200_OPERAND_WIDTH;
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parameter width = `OR1200_OPERAND_WIDTH;
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|
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//
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//
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// I/O
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// I/O
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//
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//
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input [width-1:0] a;
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input [width-1:0] a;
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input [width-1:0] b;
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input [width-1:0] b;
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input [width-1:0] mult_mac_result;
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input [width-1:0] mult_mac_result;
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input macrc_op;
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input macrc_op;
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input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
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input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
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input [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
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input [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
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input [`OR1200_COMPOP_WIDTH-1:0] comp_op;
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input [`OR1200_COMPOP_WIDTH-1:0] comp_op;
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output [width-1:0] result;
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output [width-1:0] result;
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output flagforw;
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output flagforw;
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output flag_we;
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output flag_we;
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output cyforw;
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output cyforw;
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output cy_we;
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output cy_we;
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input carry;
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input carry;
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|
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//
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//
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// Internal wires and regs
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// Internal wires and regs
|
//
|
//
|
reg [width-1:0] result;
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reg [width-1:0] result;
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reg [width-1:0] shifted_rotated;
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reg [width-1:0] shifted_rotated;
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reg flagforw;
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reg flagforw;
|
reg flagcomp;
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reg flagcomp;
|
reg flag_we;
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reg flag_we;
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reg cy_we;
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reg cy_we;
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wire [width-1:0] comp_a;
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wire [width-1:0] comp_a;
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wire [width-1:0] comp_b;
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wire [width-1:0] comp_b;
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`ifdef OR1200_IMPL_ALU_COMP1
|
`ifdef OR1200_IMPL_ALU_COMP1
|
wire a_eq_b;
|
wire a_eq_b;
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wire a_lt_b;
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wire a_lt_b;
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`endif
|
`endif
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wire [width-1:0] result_sum;
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wire [width-1:0] result_sum;
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`ifdef OR1200_IMPL_ADDC
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`ifdef OR1200_IMPL_ADDC
|
wire [width-1:0] result_csum;
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wire [width-1:0] result_csum;
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wire cy_csum;
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wire cy_csum;
|
`endif
|
`endif
|
wire [width-1:0] result_and;
|
wire [width-1:0] result_and;
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wire cy_sum;
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wire cy_sum;
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reg cyforw;
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reg cyforw;
|
|
|
//
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//
|
// Combinatorial logic
|
// Combinatorial logic
|
//
|
//
|
assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
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assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
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assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
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assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
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`ifdef OR1200_IMPL_ALU_COMP1
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`ifdef OR1200_IMPL_ALU_COMP1
|
assign a_eq_b = (comp_a == comp_b);
|
assign a_eq_b = (comp_a == comp_b);
|
assign a_lt_b = (comp_a < comp_b);
|
assign a_lt_b = (comp_a < comp_b);
|
`endif
|
`endif
|
assign {cy_sum, result_sum} = a + b;
|
assign {cy_sum, result_sum} = a + b;
|
`ifdef OR1200_IMPL_ADDC
|
`ifdef OR1200_IMPL_ADDC
|
assign {cy_csum, result_csum} = a + b + carry;
|
assign {cy_csum, result_csum} = a + b + carry;
|
`endif
|
`endif
|
assign result_and = a & b;
|
assign result_and = a & b;
|
|
|
//
|
//
|
// Simulation check for bad ALU behavior
|
// Simulation check for bad ALU behavior
|
//
|
//
|
`ifdef OR1200_WARNINGS
|
`ifdef OR1200_WARNINGS
|
// synopsys translate_off
|
// synopsys translate_off
|
always @(result) begin
|
always @(result) begin
|
if (result === 32'bx)
|
if (result === 32'bx)
|
$display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
|
$display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
|
end
|
end
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// synopsys translate_on
|
// synopsys translate_on
|
`endif
|
`endif
|
|
|
//
|
//
|
// Central part of the ALU
|
// Central part of the ALU
|
//
|
//
|
always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result) begin
|
always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result) begin
|
`ifdef OR1200_CASE_DEFAULT
|
`ifdef OR1200_CASE_DEFAULT
|
casex (alu_op) // synopsys parallel_case
|
casex (alu_op) // synopsys parallel_case
|
`else
|
`else
|
casex (alu_op) // synopsys full_case parallel_case
|
casex (alu_op) // synopsys full_case parallel_case
|
`endif
|
`endif
|
`OR1200_ALUOP_SHROT : begin
|
`OR1200_ALUOP_SHROT : begin
|
result = shifted_rotated;
|
result = shifted_rotated;
|
end
|
end
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`OR1200_ALUOP_ADD : begin
|
`OR1200_ALUOP_ADD : begin
|
result = result_sum;
|
result = result_sum;
|
end
|
end
|
`ifdef OR1200_IMPL_ADDC
|
`ifdef OR1200_IMPL_ADDC
|
`OR1200_ALUOP_ADDC : begin
|
`OR1200_ALUOP_ADDC : begin
|
result = result_csum;
|
result = result_csum;
|
end
|
end
|
`endif
|
`endif
|
`OR1200_ALUOP_SUB : begin
|
`OR1200_ALUOP_SUB : begin
|
result = a - b;
|
result = a - b;
|
end
|
end
|
`OR1200_ALUOP_XOR : begin
|
`OR1200_ALUOP_XOR : begin
|
result = a ^ b;
|
result = a ^ b;
|
end
|
end
|
`OR1200_ALUOP_OR : begin
|
`OR1200_ALUOP_OR : begin
|
result = a | b;
|
result = a | b;
|
end
|
end
|
`OR1200_ALUOP_IMM : begin
|
`OR1200_ALUOP_IMM : begin
|
result = b;
|
result = b;
|
end
|
end
|
`OR1200_ALUOP_MOVHI : begin
|
`OR1200_ALUOP_MOVHI : begin
|
if (macrc_op) begin
|
if (macrc_op) begin
|
result = mult_mac_result;
|
result = mult_mac_result;
|
end
|
end
|
else begin
|
else begin
|
result = b << 16;
|
result = b << 16;
|
end
|
end
|
end
|
end
|
`ifdef OR1200_MULT_IMPLEMENTED
|
`ifdef OR1200_MULT_IMPLEMENTED
|
`ifdef OR1200_IMPL_DIV
|
`ifdef OR1200_IMPL_DIV
|
`OR1200_ALUOP_DIV,
|
`OR1200_ALUOP_DIV,
|
`OR1200_ALUOP_DIVU,
|
`OR1200_ALUOP_DIVU,
|
`endif
|
`endif
|
`OR1200_ALUOP_MUL : begin
|
`OR1200_ALUOP_MUL : begin
|
result = mult_mac_result;
|
result = mult_mac_result;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_CASE_DEFAULT
|
`ifdef OR1200_CASE_DEFAULT
|
default: begin
|
default: begin
|
`else
|
`else
|
`OR1200_ALUOP_COMP, `OR1200_ALUOP_AND
|
`OR1200_ALUOP_COMP, `OR1200_ALUOP_AND
|
`endif
|
`endif
|
result = result_and;
|
result = result_and;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
//
|
//
|
// Generate flag and flag write enable
|
// Generate flag and flag write enable
|
//
|
//
|
always @(alu_op or result_sum or result_and or flagcomp) begin
|
always @(alu_op or result_sum or result_and or flagcomp) begin
|
casex (alu_op) // synopsys parallel_case
|
casex (alu_op) // synopsys parallel_case
|
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
|
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
|
`OR1200_ALUOP_ADD : begin
|
`OR1200_ALUOP_ADD : begin
|
flagforw = (result_sum == 32'h0000_0000);
|
flagforw = (result_sum == 32'h0000_0000);
|
flag_we = 1'b1;
|
flag_we = 1'b1;
|
end
|
end
|
`ifdef OR1200_IMPL_ADDC
|
`ifdef OR1200_IMPL_ADDC
|
`OR1200_ALUOP_ADDC : begin
|
`OR1200_ALUOP_ADDC : begin
|
flagforw = (result_csum == 32'h0000_0000);
|
flagforw = (result_csum == 32'h0000_0000);
|
flag_we = 1'b1;
|
flag_we = 1'b1;
|
end
|
end
|
`endif
|
`endif
|
`OR1200_ALUOP_AND: begin
|
`OR1200_ALUOP_AND: begin
|
flagforw = (result_and == 32'h0000_0000);
|
flagforw = (result_and == 32'h0000_0000);
|
flag_we = 1'b1;
|
flag_we = 1'b1;
|
end
|
end
|
`endif
|
`endif
|
`OR1200_ALUOP_COMP: begin
|
`OR1200_ALUOP_COMP: begin
|
flagforw = flagcomp;
|
flagforw = flagcomp;
|
flag_we = 1'b1;
|
flag_we = 1'b1;
|
end
|
end
|
default: begin
|
default: begin
|
flagforw = 1'b0;
|
flagforw = 1'b0;
|
flag_we = 1'b0;
|
flag_we = 1'b0;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
//
|
//
|
// Generate SR[CY] write enable
|
// Generate SR[CY] write enable
|
//
|
//
|
always @(alu_op or cy_sum
|
always @(alu_op or cy_sum
|
`ifdef OR1200_IMPL_ADDC
|
`ifdef OR1200_IMPL_ADDC
|
or cy_csum
|
or cy_csum
|
`endif
|
`endif
|
) begin
|
) begin
|
casex (alu_op) // synopsys parallel_case
|
casex (alu_op) // synopsys parallel_case
|
`ifdef OR1200_IMPL_ADDC
|
`ifdef OR1200_IMPL_ADDC
|
`OR1200_ALUOP_ADD : begin
|
`OR1200_ALUOP_ADD : begin
|
cyforw = cy_sum;
|
cyforw = cy_sum;
|
cy_we = 1'b1;
|
cy_we = 1'b1;
|
end
|
end
|
`OR1200_ALUOP_ADDC: begin
|
`OR1200_ALUOP_ADDC: begin
|
cyforw = cy_csum;
|
cyforw = cy_csum;
|
cy_we = 1'b1;
|
cy_we = 1'b1;
|
end
|
end
|
`endif
|
`endif
|
default: begin
|
default: begin
|
cyforw = 1'b0;
|
cyforw = 1'b0;
|
cy_we = 1'b0;
|
cy_we = 1'b0;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
//
|
//
|
// Shifts and rotation
|
// Shifts and rotation
|
//
|
//
|
always @(shrot_op or a or b) begin
|
always @(shrot_op or a or b) begin
|
case (shrot_op) // synopsys parallel_case
|
case (shrot_op) // synopsys parallel_case
|
`OR1200_SHROTOP_SLL :
|
`OR1200_SHROTOP_SLL :
|
shifted_rotated = (a << b[4:0]);
|
shifted_rotated = (a << b[4:0]);
|
`OR1200_SHROTOP_SRL :
|
`OR1200_SHROTOP_SRL :
|
shifted_rotated = (a >> b[4:0]);
|
shifted_rotated = (a >> b[4:0]);
|
|
|
`ifdef OR1200_IMPL_ALU_ROTATE
|
`ifdef OR1200_IMPL_ALU_ROTATE
|
`OR1200_SHROTOP_ROR :
|
`OR1200_SHROTOP_ROR :
|
shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) | (a >> b[4:0]);
|
shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) | (a >> b[4:0]);
|
`endif
|
`endif
|
default:
|
default:
|
shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) | a >> b[4:0];
|
shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) | a >> b[4:0];
|
endcase
|
endcase
|
end
|
end
|
|
|
//
|
//
|
// First type of compare implementation
|
// First type of compare implementation
|
//
|
//
|
`ifdef OR1200_IMPL_ALU_COMP1
|
`ifdef OR1200_IMPL_ALU_COMP1
|
always @(comp_op or a_eq_b or a_lt_b) begin
|
always @(comp_op or a_eq_b or a_lt_b) begin
|
case(comp_op[2:0]) // synopsys parallel_case
|
case(comp_op[2:0]) // synopsys parallel_case
|
`OR1200_COP_SFEQ:
|
`OR1200_COP_SFEQ:
|
flagcomp = a_eq_b;
|
flagcomp = a_eq_b;
|
`OR1200_COP_SFNE:
|
`OR1200_COP_SFNE:
|
flagcomp = ~a_eq_b;
|
flagcomp = ~a_eq_b;
|
`OR1200_COP_SFGT:
|
`OR1200_COP_SFGT:
|
flagcomp = ~(a_eq_b | a_lt_b);
|
flagcomp = ~(a_eq_b | a_lt_b);
|
`OR1200_COP_SFGE:
|
`OR1200_COP_SFGE:
|
flagcomp = ~a_lt_b;
|
flagcomp = ~a_lt_b;
|
`OR1200_COP_SFLT:
|
`OR1200_COP_SFLT:
|
flagcomp = a_lt_b;
|
flagcomp = a_lt_b;
|
`OR1200_COP_SFLE:
|
`OR1200_COP_SFLE:
|
flagcomp = a_eq_b | a_lt_b;
|
flagcomp = a_eq_b | a_lt_b;
|
default:
|
default:
|
flagcomp = 1'b0;
|
flagcomp = 1'b0;
|
endcase
|
endcase
|
end
|
end
|
`endif
|
`endif
|
|
|
//
|
//
|
// Second type of compare implementation
|
// Second type of compare implementation
|
//
|
//
|
`ifdef OR1200_IMPL_ALU_COMP2
|
`ifdef OR1200_IMPL_ALU_COMP2
|
always @(comp_op or comp_a or comp_b) begin
|
always @(comp_op or comp_a or comp_b) begin
|
case(comp_op[2:0]) // synopsys parallel_case
|
case(comp_op[2:0]) // synopsys parallel_case
|
`OR1200_COP_SFEQ:
|
`OR1200_COP_SFEQ:
|
flagcomp = (comp_a == comp_b);
|
flagcomp = (comp_a == comp_b);
|
`OR1200_COP_SFNE:
|
`OR1200_COP_SFNE:
|
flagcomp = (comp_a != comp_b);
|
flagcomp = (comp_a != comp_b);
|
`OR1200_COP_SFGT:
|
`OR1200_COP_SFGT:
|
flagcomp = (comp_a > comp_b);
|
flagcomp = (comp_a > comp_b);
|
`OR1200_COP_SFGE:
|
`OR1200_COP_SFGE:
|
flagcomp = (comp_a >= comp_b);
|
flagcomp = (comp_a >= comp_b);
|
`OR1200_COP_SFLT:
|
`OR1200_COP_SFLT:
|
flagcomp = (comp_a < comp_b);
|
flagcomp = (comp_a < comp_b);
|
`OR1200_COP_SFLE:
|
`OR1200_COP_SFLE:
|
flagcomp = (comp_a <= comp_b);
|
flagcomp = (comp_a <= comp_b);
|
default:
|
default:
|
flagcomp = 1'b0;
|
flagcomp = 1'b0;
|
endcase
|
endcase
|
end
|
end
|
`endif
|
`endif
|
|
|
endmodule
|
endmodule
|
|
|
