//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// OR1200's Debug Unit ////
|
//// OR1200's Debug Unit ////
|
//// ////
|
//// ////
|
//// This file is part of the OpenRISC 1200 project ////
|
//// This file is part of the OpenRISC 1200 project ////
|
//// http://www.opencores.org/cores/or1k/ ////
|
//// http://www.opencores.org/cores/or1k/ ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Basic OR1200 debug unit. ////
|
//// Basic OR1200 debug unit. ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - make it smaller and faster ////
|
//// - make it smaller and faster ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Damjan Lampret, lampret@opencores.org ////
|
//// - Damjan Lampret, lampret@opencores.org ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.3 2002/01/18 07:56:00 lampret
|
|
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
|
|
//
|
// Revision 1.2 2002/01/14 06:18:22 lampret
|
// Revision 1.2 2002/01/14 06:18:22 lampret
|
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
|
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
|
//
|
//
|
// Revision 1.1 2002/01/03 08:16:15 lampret
|
// Revision 1.1 2002/01/03 08:16:15 lampret
|
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
|
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
|
//
|
//
|
// Revision 1.12 2001/11/30 18:58:00 simons
|
// Revision 1.12 2001/11/30 18:58:00 simons
|
// Trap insn couses break after exits ex_insn.
|
// Trap insn couses break after exits ex_insn.
|
//
|
//
|
// Revision 1.11 2001/11/23 08:38:51 lampret
|
// Revision 1.11 2001/11/23 08:38:51 lampret
|
// Changed DSR/DRR behavior and exception detection.
|
// Changed DSR/DRR behavior and exception detection.
|
//
|
//
|
// Revision 1.10 2001/11/20 21:25:44 lampret
|
// Revision 1.10 2001/11/20 21:25:44 lampret
|
// Fixed dbg_is_o assignment width.
|
// Fixed dbg_is_o assignment width.
|
//
|
//
|
// Revision 1.9 2001/11/20 18:46:14 simons
|
// Revision 1.9 2001/11/20 18:46:14 simons
|
// Break point bug fixed
|
// Break point bug fixed
|
//
|
//
|
// Revision 1.8 2001/11/18 08:36:28 lampret
|
// Revision 1.8 2001/11/18 08:36:28 lampret
|
// For GDB changed single stepping and disabled trap exception.
|
// For GDB changed single stepping and disabled trap exception.
|
//
|
//
|
// Revision 1.7 2001/10/21 18:09:53 lampret
|
// Revision 1.7 2001/10/21 18:09:53 lampret
|
// Fixed sensitivity list.
|
// Fixed sensitivity list.
|
//
|
//
|
// Revision 1.6 2001/10/14 13:12:09 lampret
|
// Revision 1.6 2001/10/14 13:12:09 lampret
|
// MP3 version.
|
// MP3 version.
|
//
|
//
|
//
|
//
|
|
|
// synopsys translate_off
|
// synopsys translate_off
|
`include "timescale.v"
|
`include "timescale.v"
|
// synopsys translate_on
|
// synopsys translate_on
|
`include "or1200_defines.v"
|
`include "or1200_defines.v"
|
|
|
//
|
//
|
// Debug unit
|
// Debug unit
|
//
|
//
|
|
|
module or1200_du(
|
module or1200_du(
|
// RISC Internal Interface
|
// RISC Internal Interface
|
clk, rst,
|
clk, rst,
|
dcpu_cyc_i, dcpu_stb_i, dcpu_we_i,
|
dcpu_cyc_i, dcpu_stb_i, dcpu_we_i,
|
icpu_cyc_i, icpu_stb_i, ex_freeze, branch_op, ex_insn, du_dsr,
|
icpu_cyc_i, icpu_stb_i, ex_freeze, branch_op, ex_insn, du_dsr,
|
du_stall, du_addr, du_dat_i, du_dat_o, du_read, du_write, du_except,
|
du_stall, du_addr, du_dat_i, du_dat_o, du_read, du_write, du_except,
|
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
|
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
|
|
|
// External Debug Interface
|
// External Debug Interface
|
dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
|
dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
|
dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o
|
dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o
|
);
|
);
|
|
|
parameter dw = `OR1200_OPERAND_WIDTH;
|
parameter dw = `OR1200_OPERAND_WIDTH;
|
parameter aw = `OR1200_OPERAND_WIDTH;
|
parameter aw = `OR1200_OPERAND_WIDTH;
|
|
|
//
|
//
|
// I/O
|
// I/O
|
//
|
//
|
|
|
//
|
//
|
// RISC Internal Interface
|
// RISC Internal Interface
|
//
|
//
|
input clk; // Clock
|
input clk; // Clock
|
input rst; // Reset
|
input rst; // Reset
|
input dcpu_cyc_i; // LSU status
|
input dcpu_cyc_i; // LSU status
|
input dcpu_stb_i; // LSU status
|
input dcpu_stb_i; // LSU status
|
input dcpu_we_i; // LSU status
|
input dcpu_we_i; // LSU status
|
input [`OR1200_FETCHOP_WIDTH-1:0] icpu_cyc_i; // IFETCH unit status
|
input [`OR1200_FETCHOP_WIDTH-1:0] icpu_cyc_i; // IFETCH unit status
|
input [`OR1200_FETCHOP_WIDTH-1:0] icpu_stb_i; // IFETCH unit status
|
input [`OR1200_FETCHOP_WIDTH-1:0] icpu_stb_i; // IFETCH unit status
|
input ex_freeze; // EX stage freeze
|
input ex_freeze; // EX stage freeze
|
input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch op
|
input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch op
|
input [dw-1:0] ex_insn; // EX insn
|
input [dw-1:0] ex_insn; // EX insn
|
output [`OR1200_DU_DSR_WIDTH-1:0] du_dsr; // DSR
|
output [`OR1200_DU_DSR_WIDTH-1:0] du_dsr; // DSR
|
output du_stall; // Debug Unit Stall
|
output du_stall; // Debug Unit Stall
|
output [aw-1:0] du_addr; // Debug Unit Address
|
output [aw-1:0] du_addr; // Debug Unit Address
|
input [dw-1:0] du_dat_i; // Debug Unit Data In
|
input [dw-1:0] du_dat_i; // Debug Unit Data In
|
output [dw-1:0] du_dat_o; // Debug Unit Data Out
|
output [dw-1:0] du_dat_o; // Debug Unit Data Out
|
output du_read; // Debug Unit Read Enable
|
output du_read; // Debug Unit Read Enable
|
output du_write; // Debug Unit Write Enable
|
output du_write; // Debug Unit Write Enable
|
input [12:0] du_except; // Exception masked by DSR
|
input [12:0] du_except; // Exception masked by DSR
|
input spr_cs; // SPR Chip Select
|
input spr_cs; // SPR Chip Select
|
input spr_write; // SPR Read/Write
|
input spr_write; // SPR Read/Write
|
input [aw-1:0] spr_addr; // SPR Address
|
input [aw-1:0] spr_addr; // SPR Address
|
input [dw-1:0] spr_dat_i; // SPR Data Input
|
input [dw-1:0] spr_dat_i; // SPR Data Input
|
output [dw-1:0] spr_dat_o; // SPR Data Output
|
output [dw-1:0] spr_dat_o; // SPR Data Output
|
|
|
//
|
//
|
// External Debug Interface
|
// External Debug Interface
|
//
|
//
|
input dbg_stall_i; // External Stall Input
|
input dbg_stall_i; // External Stall Input
|
input [dw-1:0] dbg_dat_i; // External Data Input
|
input [dw-1:0] dbg_dat_i; // External Data Input
|
input [aw-1:0] dbg_adr_i; // External Address Input
|
input [aw-1:0] dbg_adr_i; // External Address Input
|
input [2:0] dbg_op_i; // External Operation Select Input
|
input [2:0] dbg_op_i; // External Operation Select Input
|
input dbg_ewt_i; // External Watchpoint Trigger Input
|
input dbg_ewt_i; // External Watchpoint Trigger Input
|
output [3:0] dbg_lss_o; // External Load/Store Unit Status
|
output [3:0] dbg_lss_o; // External Load/Store Unit Status
|
output [1:0] dbg_is_o; // External Insn Fetch Status
|
output [1:0] dbg_is_o; // External Insn Fetch Status
|
output [10:0] dbg_wp_o; // Watchpoints Outputs
|
output [10:0] dbg_wp_o; // Watchpoints Outputs
|
output dbg_bp_o; // Breakpoint Output
|
output dbg_bp_o; // Breakpoint Output
|
output [dw-1:0] dbg_dat_o; // External Data Output
|
output [dw-1:0] dbg_dat_o; // External Data Output
|
|
|
|
|
//
|
//
|
// Some connections go directly from the CPU through DU to Debug I/F
|
// Some connections go directly from the CPU through DU to Debug I/F
|
//
|
//
|
assign dbg_lss_o = dcpu_cyc_i & dcpu_stb_i ? {dcpu_we_i, 3'b000} : 4'b0000;
|
assign dbg_lss_o = dcpu_cyc_i & dcpu_stb_i ? {dcpu_we_i, 3'b000} : 4'b0000;
|
assign dbg_is_o = {1'b0, icpu_cyc_i & icpu_stb_i};
|
assign dbg_is_o = {1'b0, icpu_cyc_i & icpu_stb_i};
|
assign dbg_wp_o = 11'b000_0000_0000;
|
assign dbg_wp_o = 11'b000_0000_0000;
|
assign dbg_dat_o = du_dat_i;
|
assign dbg_dat_o = du_dat_i;
|
|
|
//
|
//
|
// Some connections go directly from Debug I/F through DU to the CPU
|
// Some connections go directly from Debug I/F through DU to the CPU
|
//
|
//
|
assign du_stall = dbg_stall_i;
|
assign du_stall = dbg_stall_i;
|
assign du_addr = dbg_adr_i;
|
assign du_addr = dbg_adr_i;
|
assign du_dat_o = dbg_dat_i;
|
assign du_dat_o = dbg_dat_i;
|
assign du_read = (dbg_op_i == `OR1200_DU_OP_READSPR);
|
assign du_read = (dbg_op_i == `OR1200_DU_OP_READSPR);
|
assign du_write = (dbg_op_i == `OR1200_DU_OP_WRITESPR);
|
assign du_write = (dbg_op_i == `OR1200_DU_OP_WRITESPR);
|
|
|
`ifdef OR1200_DU_IMPLEMENTED
|
`ifdef OR1200_DU_IMPLEMENTED
|
|
|
//
|
//
|
// Debug Mode Register 1 (only ST and BT implemented)
|
// Debug Mode Register 1 (only ST and BT implemented)
|
//
|
//
|
`ifdef OR1200_DU_DMR1
|
`ifdef OR1200_DU_DMR1
|
reg [23:22] dmr1; // DMR1 implemented (ST & BT)
|
reg [23:22] dmr1; // DMR1 implemented (ST & BT)
|
`else
|
`else
|
wire [23:22] dmr1; // DMR1 not implemented
|
wire [23:22] dmr1; // DMR1 not implemented
|
`endif
|
`endif
|
|
|
//
|
//
|
// Debug Mode Register 2 (not implemented)
|
// Debug Mode Register 2 (not implemented)
|
//
|
//
|
`ifdef OR1200_DU_DMR2
|
`ifdef OR1200_DU_DMR2
|
wire [31:0] dmr2; // DMR not implemented
|
wire [31:0] dmr2; // DMR not implemented
|
`endif
|
`endif
|
|
|
//
|
//
|
// Debug Stop Register
|
// Debug Stop Register
|
//
|
//
|
`ifdef OR1200_DU_DSR
|
`ifdef OR1200_DU_DSR
|
reg [`OR1200_DU_DSR_WIDTH-1:0] dsr; // DSR implemented
|
reg [`OR1200_DU_DSR_WIDTH-1:0] dsr; // DSR implemented
|
`else
|
`else
|
wire [`OR1200_DU_DSR_WIDTH-1:0] dsr; // DSR not implemented
|
wire [`OR1200_DU_DSR_WIDTH-1:0] dsr; // DSR not implemented
|
`endif
|
`endif
|
|
|
//
|
//
|
// Debug Reason Register
|
// Debug Reason Register
|
//
|
//
|
`ifdef OR1200_DU_DRR
|
`ifdef OR1200_DU_DRR
|
reg [13:0] drr; // DRR implemented
|
reg [13:0] drr; // DRR implemented
|
`else
|
`else
|
wire [13:0] drr; // DRR not implemented
|
wire [13:0] drr; // DRR not implemented
|
`endif
|
`endif
|
|
|
//
|
//
|
// Internal wires
|
// Internal wires
|
//
|
//
|
wire dmr1_sel; // DMR1 select
|
wire dmr1_sel; // DMR1 select
|
wire dsr_sel; // DSR select
|
wire dsr_sel; // DSR select
|
wire drr_sel; // DRR select
|
wire drr_sel; // DRR select
|
reg dbg_bp_r;
|
reg dbg_bp_r;
|
`ifdef OR1200_DU_READREGS
|
`ifdef OR1200_DU_READREGS
|
reg [31:0] spr_dat_o;
|
reg [31:0] spr_dat_o;
|
`endif
|
`endif
|
reg [13:0] except_stop; // Exceptions that stop because of DSR
|
reg [13:0] except_stop; // Exceptions that stop because of DSR
|
|
|
//
|
//
|
// DU registers address decoder
|
// DU registers address decoder
|
//
|
//
|
`ifdef OR1200_DU_DMR1
|
`ifdef OR1200_DU_DMR1
|
assign dmr1_sel = (spr_cs && (spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_DU_OFS_DMR1));
|
assign dmr1_sel = (spr_cs && (spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_DU_OFS_DMR1));
|
`endif
|
`endif
|
`ifdef OR1200_DU_DSR
|
`ifdef OR1200_DU_DSR
|
assign dsr_sel = (spr_cs && (spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_DU_OFS_DSR));
|
assign dsr_sel = (spr_cs && (spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_DU_OFS_DSR));
|
`endif
|
`endif
|
`ifdef OR1200_DU_DRR
|
`ifdef OR1200_DU_DRR
|
assign drr_sel = (spr_cs && (spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_DU_OFS_DRR));
|
assign drr_sel = (spr_cs && (spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_DU_OFS_DRR));
|
`endif
|
`endif
|
|
|
//
|
//
|
// Decode started exception
|
// Decode started exception
|
//
|
//
|
always @(du_except) begin
|
always @(du_except) begin
|
except_stop = 14'b0000_0000_0000;
|
except_stop = 14'b0000_0000_0000;
|
casex (du_except)
|
casex (du_except)
|
13'b1_xxxx_xxxx_xxxx: begin
|
13'b1_xxxx_xxxx_xxxx:
|
|
except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
|
|
13'b0_1xxx_xxxx_xxxx: begin
|
except_stop[`OR1200_DU_DRR_IE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_IE] = 1'b1;
|
end
|
end
|
13'b0_1xxx_xxxx_xxxx: begin
|
13'b0_01xx_xxxx_xxxx: begin
|
except_stop[`OR1200_DU_DRR_IME] = 1'b1;
|
except_stop[`OR1200_DU_DRR_IME] = 1'b1;
|
end
|
end
|
13'b0_01xx_xxxx_xxxx:
|
13'b0_001x_xxxx_xxxx:
|
except_stop[`OR1200_DU_DRR_IPFE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_IPFE] = 1'b1;
|
13'b0_001x_xxxx_xxxx: begin
|
13'b0_0001_xxxx_xxxx: begin
|
except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
|
end
|
end
|
13'b0_0001_xxxx_xxxx:
|
13'b0_0000_1xxx_xxxx:
|
except_stop[`OR1200_DU_DRR_IIE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_IIE] = 1'b1;
|
13'b0_0000_1xxx_xxxx: begin
|
13'b0_0000_01xx_xxxx: begin
|
except_stop[`OR1200_DU_DRR_AE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_AE] = 1'b1;
|
end
|
end
|
13'b0_0000_01xx_xxxx: begin
|
13'b0_0000_001x_xxxx: begin
|
except_stop[`OR1200_DU_DRR_DME] = 1'b1;
|
except_stop[`OR1200_DU_DRR_DME] = 1'b1;
|
end
|
end
|
13'b0_0000_001x_xxxx:
|
|
except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
|
|
13'b0_0000_0001_xxxx:
|
13'b0_0000_0001_xxxx:
|
except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
|
13'b0_0000_0000_1xxx:
|
13'b0_0000_0000_1xxx:
|
except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
|
13'b0_0000_0000_01xx: begin
|
13'b0_0000_0000_01xx: begin
|
except_stop[`OR1200_DU_DRR_RE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_RE] = 1'b1;
|
end
|
end
|
13'b0_0000_0000_001x: begin
|
13'b0_0000_0000_001x: begin
|
except_stop[`OR1200_DU_DRR_TE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_TE] = 1'b1;
|
end
|
end
|
13'b0_0000_0000_0001:
|
13'b0_0000_0000_0001:
|
except_stop[`OR1200_DU_DRR_SCE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_SCE] = 1'b1;
|
default:
|
default:
|
except_stop = 14'b0000_0000_0000;
|
except_stop = 14'b0000_0000_0000;
|
endcase
|
endcase
|
end
|
end
|
|
|
//
|
//
|
// dbg_bp_o is registered
|
// dbg_bp_o is registered
|
//
|
//
|
assign dbg_bp_o = dbg_bp_r;
|
assign dbg_bp_o = dbg_bp_r;
|
|
|
//
|
//
|
// Breakpoint activation register
|
// Breakpoint activation register
|
//
|
//
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
dbg_bp_r <= #1 1'b0;
|
dbg_bp_r <= #1 1'b0;
|
else if (!ex_freeze)
|
else if (!ex_freeze)
|
dbg_bp_r <= #1 |except_stop
|
dbg_bp_r <= #1 |except_stop
|
`ifdef OR1200_DU_DMR1_ST
|
`ifdef OR1200_DU_DMR1_ST
|
| ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[0]) & dmr1[`OR1200_DU_DMR1_ST]
|
| ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]) & dmr1[`OR1200_DU_DMR1_ST]
|
`endif
|
`endif
|
`ifdef OR1200_DU_DMR1_BT
|
`ifdef OR1200_DU_DMR1_BT
|
| (branch_op != `OR1200_BRANCHOP_NOP) & dmr1[`OR1200_DU_DMR1_BT]
|
| (branch_op != `OR1200_BRANCHOP_NOP) & dmr1[`OR1200_DU_DMR1_BT]
|
`endif
|
`endif
|
;
|
;
|
else
|
else
|
dbg_bp_r <= #1 |except_stop;
|
dbg_bp_r <= #1 |except_stop;
|
|
|
//
|
//
|
// Write to DMR1
|
// Write to DMR1
|
//
|
//
|
`ifdef OR1200_DU_DMR1
|
`ifdef OR1200_DU_DMR1
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
dmr1 <= 2'b00;
|
dmr1 <= 2'b00;
|
else if (dmr1_sel && spr_write)
|
else if (dmr1_sel && spr_write)
|
dmr1 <= #1 spr_dat_i[23:22];
|
dmr1 <= #1 spr_dat_i[23:22];
|
`else
|
`else
|
assign dmr1 = 2'b00;
|
assign dmr1 = 2'b00;
|
`endif
|
`endif
|
|
|
//
|
//
|
// DMR2 bits tied to zero
|
// DMR2 bits tied to zero
|
//
|
//
|
`ifdef OR1200_DU_DMR2
|
`ifdef OR1200_DU_DMR2
|
assign dmr2 = 32'h0000_0000;
|
assign dmr2 = 32'h0000_0000;
|
`endif
|
`endif
|
|
|
//
|
//
|
// Write to DSR
|
// Write to DSR
|
//
|
//
|
`ifdef OR1200_DU_DSR
|
`ifdef OR1200_DU_DSR
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};
|
dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};
|
else if (dsr_sel && spr_write)
|
else if (dsr_sel && spr_write)
|
dsr <= #1 spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0];
|
dsr <= #1 spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0];
|
`else
|
`else
|
assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
|
assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
|
`endif
|
`endif
|
|
|
//
|
//
|
// Write to DRR
|
// Write to DRR
|
//
|
//
|
`ifdef OR1200_DU_DRR
|
`ifdef OR1200_DU_DRR
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
drr <= 14'b0;
|
drr <= 14'b0;
|
else if (drr_sel && spr_write)
|
else if (drr_sel && spr_write)
|
drr <= #1 spr_dat_i[13:0];
|
drr <= #1 spr_dat_i[13:0];
|
else
|
else
|
drr <= #1 drr | except_stop;
|
drr <= #1 drr | except_stop;
|
`else
|
`else
|
assign drr = 14'b0;
|
assign drr = 14'b0;
|
`endif
|
`endif
|
|
|
//
|
//
|
// Read DU registers
|
// Read DU registers
|
//
|
//
|
`ifdef OR1200_DU_READREGS
|
`ifdef OR1200_DU_READREGS
|
always @(spr_addr or dsr or drr or dmr1 or dmr2)
|
always @(spr_addr or dsr or drr or dmr1 or dmr2)
|
case (spr_addr[`OR1200_SPR_OFS_BITS])
|
case (spr_addr[`OR1200_SPR_OFS_BITS])
|
`ifdef OR1200_DU_DMR1
|
`ifdef OR1200_DU_DMR1
|
`OR1200_DU_OFS_DMR1:
|
`OR1200_DU_OFS_DMR1:
|
spr_dat_o = {8'b0, dmr1, 22'b0};
|
spr_dat_o = {8'b0, dmr1, 22'b0};
|
`endif
|
`endif
|
`ifdef OR1200_DU_DMR2
|
`ifdef OR1200_DU_DMR2
|
`OR1200_DU_OFS_DMR2:
|
`OR1200_DU_OFS_DMR2:
|
spr_dat_o = dmr2;
|
spr_dat_o = dmr2;
|
`endif
|
`endif
|
`ifdef OR1200_DU_DSR
|
`ifdef OR1200_DU_DSR
|
`OR1200_DU_OFS_DSR:
|
`OR1200_DU_OFS_DSR:
|
spr_dat_o = {18'b0, dsr};
|
spr_dat_o = {18'b0, dsr};
|
`endif
|
`endif
|
`ifdef OR1200_DU_DRR
|
`ifdef OR1200_DU_DRR
|
`OR1200_DU_OFS_DRR:
|
`OR1200_DU_OFS_DRR:
|
spr_dat_o = {18'b0, drr};
|
spr_dat_o = {18'b0, drr};
|
`endif
|
`endif
|
default:
|
default:
|
spr_dat_o = 32'h0000_0000;
|
spr_dat_o = 32'h0000_0000;
|
endcase
|
endcase
|
`endif
|
`endif
|
|
|
//
|
//
|
// DSR alias
|
// DSR alias
|
//
|
//
|
assign du_dsr = dsr;
|
assign du_dsr = dsr;
|
|
|
`else
|
`else
|
|
|
//
|
//
|
// When DU is not implemented, drive all outputs as would when DU is disabled
|
// When DU is not implemented, drive all outputs as would when DU is disabled
|
//
|
//
|
assign dbg_bp_o = 1'b0;
|
assign dbg_bp_o = 1'b0;
|
assign du_dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
|
assign du_dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
|
|
|
//
|
//
|
// Read DU registers
|
// Read DU registers
|
//
|
//
|
`ifdef OR1200_DU_READREGS
|
`ifdef OR1200_DU_READREGS
|
assign spr_dat_o = 32'h0000_0000;
|
assign spr_dat_o = 32'h0000_0000;
|
`ifdef OR1200_DU_UNUSED_ZERO
|
`ifdef OR1200_DU_UNUSED_ZERO
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
`endif
|
`endif
|
|
|
endmodule
|
endmodule
|
|
|