//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's Exception logic ////
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//// OR1200's Exception logic ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Handles all OR1K exceptions inside CPU block. ////
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//// Handles all OR1K exceptions inside CPU block. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// - make it smaller and faster ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/01/14 06:18:22 lampret
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|
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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//
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// Revision 1.15 2001/11/27 23:13:11 lampret
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// Revision 1.15 2001/11/27 23:13:11 lampret
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// Fixed except_stop width and fixed EX PC for 1400444f no-ops.
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// Fixed except_stop width and fixed EX PC for 1400444f no-ops.
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//
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//
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// Revision 1.14 2001/11/23 08:38:51 lampret
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// Revision 1.14 2001/11/23 08:38:51 lampret
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// Changed DSR/DRR behavior and exception detection.
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// Changed DSR/DRR behavior and exception detection.
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//
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//
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// Revision 1.13 2001/11/20 18:46:15 simons
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// Revision 1.13 2001/11/20 18:46:15 simons
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// Break point bug fixed
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// Break point bug fixed
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//
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//
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// Revision 1.12 2001/11/18 09:58:28 lampret
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// Revision 1.12 2001/11/18 09:58:28 lampret
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// Fixed some l.trap typos.
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// Fixed some l.trap typos.
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//
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//
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// Revision 1.11 2001/11/18 08:36:28 lampret
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// Revision 1.11 2001/11/18 08:36:28 lampret
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// For GDB changed single stepping and disabled trap exception.
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// For GDB changed single stepping and disabled trap exception.
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//
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//
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// Revision 1.10 2001/11/13 10:02:21 lampret
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// Revision 1.10 2001/11/13 10:02:21 lampret
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// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
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// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
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//
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//
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// Revision 1.9 2001/11/10 03:43:57 lampret
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// Revision 1.9 2001/11/10 03:43:57 lampret
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// Fixed exceptions.
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// Fixed exceptions.
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//
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//
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// Revision 1.8 2001/10/21 17:57:16 lampret
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// Revision 1.8 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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//
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// Revision 1.7 2001/10/14 13:12:09 lampret
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// Revision 1.7 2001/10/14 13:12:09 lampret
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// MP3 version.
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// MP3 version.
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//
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//
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// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
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// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
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// no message
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// no message
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//
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//
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// Revision 1.2 2001/08/09 13:39:33 lampret
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// Revision 1.2 2001/08/09 13:39:33 lampret
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// Major clean-up.
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// Major clean-up.
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//
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//
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Development version of RTL. Libraries are missing.
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// Development version of RTL. Libraries are missing.
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//
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//
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//
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//
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|
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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|
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`define OR1200_EXCEPTFSM_WIDTH 3
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`define OR1200_EXCEPTFSM_WIDTH 3
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`define OR1200_EXCEPTFSM_IDLE `OR1200_EXCEPTFSM_WIDTH'd0
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`define OR1200_EXCEPTFSM_IDLE `OR1200_EXCEPTFSM_WIDTH'd0
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`define OR1200_EXCEPTFSM_FLU1 `OR1200_EXCEPTFSM_WIDTH'd1
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`define OR1200_EXCEPTFSM_FLU1 `OR1200_EXCEPTFSM_WIDTH'd1
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`define OR1200_EXCEPTFSM_FLU2 `OR1200_EXCEPTFSM_WIDTH'd2
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`define OR1200_EXCEPTFSM_FLU2 `OR1200_EXCEPTFSM_WIDTH'd2
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`define OR1200_EXCEPTFSM_FLU3 `OR1200_EXCEPTFSM_WIDTH'd3
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`define OR1200_EXCEPTFSM_FLU3 `OR1200_EXCEPTFSM_WIDTH'd3
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`define OR1200_EXCEPTFSM_FLU4 `OR1200_EXCEPTFSM_WIDTH'd4
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`define OR1200_EXCEPTFSM_FLU4 `OR1200_EXCEPTFSM_WIDTH'd4
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`define OR1200_EXCEPTFSM_FLU5 `OR1200_EXCEPTFSM_WIDTH'd5
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`define OR1200_EXCEPTFSM_FLU5 `OR1200_EXCEPTFSM_WIDTH'd5
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|
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//
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//
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// Exception recognition and sequencing
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// Exception recognition and sequencing
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//
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//
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module or1200_except(
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module or1200_except(
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// Clock and reset
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// Clock and reset
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clk, rst,
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clk, rst,
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|
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// Internal i/f
|
// Internal i/f
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sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, sig_dmmufault,
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sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, sig_dmmufault,
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sig_inthigh, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_intlow,
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sig_inthigh, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_intlow,
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branch_taken, id_freeze, ex_freeze, wb_freeze, if_stall,
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branch_taken, id_freeze, ex_freeze, wb_freeze, if_stall,
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if_pc, lr_sav, flushpipe, extend_flush, except_type, except_start,
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if_pc, lr_sav, flushpipe, extend_flush, except_type, except_start,
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except_started, except_stop,
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except_started, except_stop,
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wb_pc, ex_pc, id_pc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
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wb_pc, ex_pc, id_pc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
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esr, sr, lsu_addr
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esr, sr, lsu_addr
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);
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);
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|
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//
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//
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// I/O
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// I/O
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//
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//
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input clk;
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input clk;
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input rst;
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input rst;
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input sig_ibuserr;
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input sig_ibuserr;
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input sig_dbuserr;
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input sig_dbuserr;
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input sig_illegal;
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input sig_illegal;
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input sig_align;
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input sig_align;
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input sig_range;
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input sig_range;
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input sig_dtlbmiss;
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input sig_dtlbmiss;
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input sig_dmmufault;
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input sig_dmmufault;
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input sig_inthigh;
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input sig_inthigh;
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input sig_syscall;
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input sig_syscall;
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input sig_trap;
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input sig_trap;
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input sig_itlbmiss;
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input sig_itlbmiss;
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input sig_immufault;
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input sig_immufault;
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input sig_intlow;
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input sig_intlow;
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input branch_taken;
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input branch_taken;
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input id_freeze;
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input id_freeze;
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input ex_freeze;
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input ex_freeze;
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input wb_freeze;
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input wb_freeze;
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input if_stall;
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input if_stall;
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input [31:0] if_pc;
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input [31:0] if_pc;
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output [31:2] lr_sav;
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output [31:2] lr_sav;
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input [31:0] datain;
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input [31:0] datain;
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input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
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input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
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input epcr_we;
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input epcr_we;
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input eear_we;
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input eear_we;
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input esr_we;
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input esr_we;
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input pc_we;
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input pc_we;
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output [31:0] epcr;
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output [31:0] epcr;
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output [31:0] eear;
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output [31:0] eear;
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output [`OR1200_SR_WIDTH-1:0] esr;
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output [`OR1200_SR_WIDTH-1:0] esr;
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input [`OR1200_SR_WIDTH-1:0] sr;
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input [`OR1200_SR_WIDTH-1:0] sr;
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input [31:0] lsu_addr;
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input [31:0] lsu_addr;
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output flushpipe;
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output flushpipe;
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output extend_flush;
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output extend_flush;
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output [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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output [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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output except_start;
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output except_start;
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output except_started;
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output except_started;
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output [12:0] except_stop;
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output [12:0] except_stop;
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output [31:0] wb_pc;
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output [31:0] wb_pc;
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output [31:0] ex_pc;
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output [31:0] ex_pc;
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output [31:0] id_pc;
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output [31:0] id_pc;
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//
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//
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// Internal regs and wires
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// Internal regs and wires
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//
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//
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reg [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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reg [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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reg [31:0] id_pc;
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reg [31:0] id_pc;
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reg [31:0] ex_pc;
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reg [31:0] ex_pc;
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reg [31:0] wb_pc;
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reg [31:0] wb_pc;
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reg [31:0] epcr;
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reg [31:0] epcr;
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reg [31:0] eear;
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reg [31:0] eear;
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reg [`OR1200_SR_WIDTH-1:0] esr;
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reg [`OR1200_SR_WIDTH-1:0] esr;
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reg [3:0] id_exceptflags;
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reg [3:0] id_exceptflags;
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reg [3:0] ex_exceptflags;
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reg [3:0] ex_exceptflags;
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reg [`OR1200_EXCEPTFSM_WIDTH-1:0] state;
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reg [`OR1200_EXCEPTFSM_WIDTH-1:0] state;
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reg extend_flush;
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reg extend_flush;
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reg extend_flush_last;
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reg extend_flush_last;
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reg ex_dslot;
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reg ex_dslot;
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reg delayed1_ex_dslot;
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reg delayed1_ex_dslot;
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reg delayed2_ex_dslot;
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reg delayed2_ex_dslot;
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wire except_started;
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wire except_started;
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wire [12:0] except_trig;
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wire [12:0] except_trig;
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wire except_flushpipe;
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wire except_flushpipe;
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reg [2:0] delayed_eir;
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reg [2:0] delayed_eir;
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wire inthigh_pending;
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wire inthigh_pending;
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wire intlow_pending;
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wire intlow_pending;
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//
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//
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// Simple combinatorial logic
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// Simple combinatorial logic
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//
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//
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assign except_started = extend_flush & except_start;
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assign except_started = extend_flush & except_start;
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assign lr_sav = ex_pc[31:2];
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assign lr_sav = ex_pc[31:2];
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//assign except_start = (except_type != `OR1200_EXCEPT_NONE); // damjan
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//assign except_start = (except_type != `OR1200_EXCEPT_NONE); // damjan
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assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
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assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
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assign inthigh_pending = sig_inthigh & sr[`OR1200_SR_EIR] & delayed_eir[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
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assign inthigh_pending = sig_inthigh & sr[`OR1200_SR_EIR] & delayed_eir[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
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assign intlow_pending = sig_intlow & sr[`OR1200_SR_EIR] & delayed_eir[2] & ~ex_freeze & ~branch_taken & ~ex_dslot & ~delayed1_ex_dslot & ~delayed2_ex_dslot;
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assign intlow_pending = sig_intlow & sr[`OR1200_SR_EIR] & delayed_eir[2] & ~ex_freeze & ~branch_taken & ~ex_dslot & ~delayed1_ex_dslot & ~delayed2_ex_dslot;
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|
|
//
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//
|
// Order defines exception detection priority
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// Order defines exception detection priority
|
//
|
//
|
assign except_trig = {
|
assign except_trig = {
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inthigh_pending & ~du_dsr[`OR1200_DU_DSR_HPINTE],
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inthigh_pending & ~du_dsr[`OR1200_DU_DSR_HPINTE],
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ex_exceptflags[2] & ~du_dsr[`OR1200_DU_DSR_IME],
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ex_exceptflags[2] & ~du_dsr[`OR1200_DU_DSR_IME],
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ex_exceptflags[1] & ~du_dsr[`OR1200_DU_DSR_IPFE],
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ex_exceptflags[1] & ~du_dsr[`OR1200_DU_DSR_IPFE],
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ex_exceptflags[3] & ~du_dsr[`OR1200_DU_DSR_BUSEE],
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ex_exceptflags[3] & ~du_dsr[`OR1200_DU_DSR_BUSEE],
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sig_illegal & ~du_dsr[`OR1200_DU_DSR_IIE],
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sig_illegal & ~du_dsr[`OR1200_DU_DSR_IIE],
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sig_align & ~du_dsr[`OR1200_DU_DSR_AE],
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sig_align & ~du_dsr[`OR1200_DU_DSR_AE],
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sig_dtlbmiss & ~du_dsr[`OR1200_DU_DSR_DME],
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sig_dtlbmiss & ~du_dsr[`OR1200_DU_DSR_DME],
|
sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE],
|
sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE],
|
sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE],
|
sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE],
|
ex_exceptflags[0] & ~du_dsr[`OR1200_DU_DSR_LPINTE],
|
ex_exceptflags[0] & ~du_dsr[`OR1200_DU_DSR_LPINTE],
|
sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze,
|
sig_range & ~du_dsr[`OR1200_DU_DSR_RE],
|
sig_trap & ~du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
|
sig_trap & ~du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
|
sig_range & ~du_dsr[`OR1200_DU_DSR_RE]
|
sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
|
};
|
};
|
assign except_stop = {
|
assign except_stop = {
|
inthigh_pending & du_dsr[`OR1200_DU_DSR_HPINTE],
|
inthigh_pending & du_dsr[`OR1200_DU_DSR_HPINTE],
|
ex_exceptflags[2] & du_dsr[`OR1200_DU_DSR_IME],
|
ex_exceptflags[2] & du_dsr[`OR1200_DU_DSR_IME],
|
ex_exceptflags[1] & du_dsr[`OR1200_DU_DSR_IPFE],
|
ex_exceptflags[1] & du_dsr[`OR1200_DU_DSR_IPFE],
|
ex_exceptflags[3] & du_dsr[`OR1200_DU_DSR_BUSEE],
|
ex_exceptflags[3] & du_dsr[`OR1200_DU_DSR_BUSEE],
|
sig_illegal & du_dsr[`OR1200_DU_DSR_IIE],
|
sig_illegal & du_dsr[`OR1200_DU_DSR_IIE],
|
sig_align & du_dsr[`OR1200_DU_DSR_AE],
|
sig_align & du_dsr[`OR1200_DU_DSR_AE],
|
sig_dtlbmiss & du_dsr[`OR1200_DU_DSR_DME],
|
sig_dtlbmiss & du_dsr[`OR1200_DU_DSR_DME],
|
sig_dmmufault & du_dsr[`OR1200_DU_DSR_DPFE],
|
sig_dmmufault & du_dsr[`OR1200_DU_DSR_DPFE],
|
sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE],
|
sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE],
|
ex_exceptflags[0] & du_dsr[`OR1200_DU_DSR_LPINTE],
|
ex_exceptflags[0] & du_dsr[`OR1200_DU_DSR_LPINTE],
|
sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze,
|
sig_range & du_dsr[`OR1200_DU_DSR_RE],
|
sig_trap & du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
|
sig_trap & du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
|
sig_range & du_dsr[`OR1200_DU_DSR_RE]
|
sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
|
};
|
};
|
|
|
//
|
//
|
// PC and Exception flags pipelines
|
// PC and Exception flags pipelines
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst) begin
|
if (rst) begin
|
id_pc <= #1 32'd0;
|
id_pc <= #1 32'd0;
|
id_exceptflags <= #1 4'b0000;
|
id_exceptflags <= #1 4'b0000;
|
end
|
end
|
else if (flushpipe) begin
|
else if (flushpipe) begin
|
id_pc <= #1 32'h0000_0000;
|
id_pc <= #1 32'h0000_0000;
|
id_exceptflags <= #1 4'b0000;
|
id_exceptflags <= #1 4'b0000;
|
end
|
end
|
else if (!id_freeze) begin
|
else if (!id_freeze) begin
|
id_pc <= #1 if_pc;
|
id_pc <= #1 if_pc;
|
id_exceptflags <= #1 { sig_ibuserr, sig_itlbmiss, sig_immufault, intlow_pending };
|
id_exceptflags <= #1 { sig_ibuserr, sig_itlbmiss, sig_immufault, intlow_pending };
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
// delayed_eir
|
// delayed_eir
|
//
|
//
|
// SR[EIR] should not enable interrupts right away
|
// SR[EIR] should not enable interrupts right away
|
// when it is restored with l.rfe. Instead delayed_eir
|
// when it is restored with l.rfe. Instead delayed_eir
|
// together with SR[EIR] enables interrupts once
|
// together with SR[EIR] enables interrupts once
|
// pipeline is again ready.
|
// pipeline is again ready.
|
//
|
//
|
always @(posedge rst or posedge clk)
|
always @(posedge rst or posedge clk)
|
if (rst)
|
if (rst)
|
delayed_eir <= #1 3'b000;
|
delayed_eir <= #1 3'b000;
|
else if (!sr[`OR1200_SR_EIR])
|
else if (!sr[`OR1200_SR_EIR])
|
delayed_eir <= #1 3'b000;
|
delayed_eir <= #1 3'b000;
|
else
|
else
|
delayed_eir <= #1 {delayed_eir[1:0], 1'b1};
|
delayed_eir <= #1 {delayed_eir[1:0], 1'b1};
|
|
|
//
|
//
|
// PC and Exception flags pipelines
|
// PC and Exception flags pipelines
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst) begin
|
if (rst) begin
|
ex_dslot <= #1 1'b0;
|
ex_dslot <= #1 1'b0;
|
ex_pc <= #1 32'd0;
|
ex_pc <= #1 32'd0;
|
ex_exceptflags <= #1 4'b0000;
|
ex_exceptflags <= #1 4'b0000;
|
delayed1_ex_dslot <= #1 1'b0;
|
delayed1_ex_dslot <= #1 1'b0;
|
delayed2_ex_dslot <= #1 1'b0;
|
delayed2_ex_dslot <= #1 1'b0;
|
end
|
end
|
else if (flushpipe) begin
|
else if (flushpipe) begin
|
ex_dslot <= #1 1'b0;
|
ex_dslot <= #1 1'b0;
|
ex_pc <= #1 32'h0000_0000;
|
ex_pc <= #1 32'h0000_0000;
|
ex_exceptflags <= #1 4'b0000;
|
ex_exceptflags <= #1 4'b0000;
|
delayed1_ex_dslot <= #1 1'b0;
|
delayed1_ex_dslot <= #1 1'b0;
|
delayed2_ex_dslot <= #1 1'b0;
|
delayed2_ex_dslot <= #1 1'b0;
|
end
|
end
|
else if (!ex_freeze & id_freeze) begin
|
else if (!ex_freeze & id_freeze) begin
|
ex_dslot <= #1 1'b0;
|
ex_dslot <= #1 1'b0;
|
ex_pc <= #1 id_pc;
|
ex_pc <= #1 id_pc;
|
ex_exceptflags <= #1 4'b0000;
|
ex_exceptflags <= #1 4'b0000;
|
delayed1_ex_dslot <= #1 ex_dslot;
|
delayed1_ex_dslot <= #1 ex_dslot;
|
delayed2_ex_dslot <= #1 delayed1_ex_dslot;
|
delayed2_ex_dslot <= #1 delayed1_ex_dslot;
|
end
|
end
|
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
// synopsys translate_off
|
// synopsys translate_off
|
$display("%t: ex_pc <= %h", $time, id_pc);
|
$display("%t: ex_pc <= %h", $time, id_pc);
|
// synopsys translate_on
|
// synopsys translate_on
|
`endif
|
`endif
|
ex_dslot <= #1 branch_taken;
|
ex_dslot <= #1 branch_taken;
|
ex_pc <= #1 id_pc;
|
ex_pc <= #1 id_pc;
|
ex_exceptflags <= #1 id_exceptflags;
|
ex_exceptflags <= #1 id_exceptflags;
|
delayed1_ex_dslot <= #1 ex_dslot;
|
delayed1_ex_dslot <= #1 ex_dslot;
|
delayed2_ex_dslot <= #1 delayed1_ex_dslot;
|
delayed2_ex_dslot <= #1 delayed1_ex_dslot;
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
// PC and Exception flags pipelines
|
// PC and Exception flags pipelines
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst) begin
|
if (rst) begin
|
wb_pc <= #1 32'd0;
|
wb_pc <= #1 32'd0;
|
end
|
end
|
else if (!wb_freeze) begin
|
else if (!wb_freeze) begin
|
wb_pc <= #1 ex_pc;
|
wb_pc <= #1 ex_pc;
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
// Flush pipeline
|
// Flush pipeline
|
//
|
//
|
assign flushpipe = except_flushpipe | pc_we | extend_flush;
|
assign flushpipe = except_flushpipe | pc_we | extend_flush;
|
|
|
//
|
//
|
// We have started execution of exception handler:
|
// We have started execution of exception handler:
|
// 1. Asserted for 3 clock cycles
|
// 1. Asserted for 3 clock cycles
|
// 2. Don't execute any instruction that is still in pipeline and is not part of exception handler
|
// 2. Don't execute any instruction that is still in pipeline and is not part of exception handler
|
//
|
//
|
assign except_flushpipe = |except_trig & !state;
|
assign except_flushpipe = |except_trig & !state;
|
|
|
//
|
//
|
// Exception FSM that sequences execution of exception handler
|
// Exception FSM that sequences execution of exception handler
|
//
|
//
|
// except_type signals which exception handler we start fetching in:
|
// except_type signals which exception handler we start fetching in:
|
// 1. Asserted in next clock cycle after exception is recognized
|
// 1. Asserted in next clock cycle after exception is recognized
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst) begin
|
if (rst) begin
|
state <= #1 `OR1200_EXCEPTFSM_IDLE;
|
state <= #1 `OR1200_EXCEPTFSM_IDLE;
|
except_type <= #1 `OR1200_EXCEPT_NONE;
|
except_type <= #1 `OR1200_EXCEPT_NONE;
|
extend_flush <= #1 1'b0;
|
extend_flush <= #1 1'b0;
|
epcr <= #1 32'b0;
|
epcr <= #1 32'b0;
|
eear <= #1 32'b0;
|
eear <= #1 32'b0;
|
esr <= #1 `OR1200_SR_WIDTH'b010;
|
esr <= #1 `OR1200_SR_WIDTH'b010;
|
extend_flush_last <= #1 1'b0;
|
extend_flush_last <= #1 1'b0;
|
end
|
end
|
else begin
|
else begin
|
case (state) // synopsys full_case parallel_case
|
case (state) // synopsys full_case parallel_case
|
`OR1200_EXCEPTFSM_IDLE:
|
`OR1200_EXCEPTFSM_IDLE:
|
if (except_flushpipe) begin
|
if (except_flushpipe) begin
|
state <= #1 `OR1200_EXCEPTFSM_FLU1;
|
state <= #1 `OR1200_EXCEPTFSM_FLU1;
|
extend_flush <= #1 1'b1;
|
extend_flush <= #1 1'b1;
|
if (ex_dslot) begin
|
if (ex_dslot) begin
|
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
// synopsys translate_off
|
// synopsys translate_off
|
$display(" INFO: Exception during first delay slot instruction.");
|
$display(" INFO: Exception during first delay slot instruction.");
|
// synopsys translate_on
|
// synopsys translate_on
|
`endif
|
`endif
|
end
|
end
|
else if (delayed1_ex_dslot) begin
|
else if (delayed1_ex_dslot) begin
|
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
// synopsys translate_off
|
// synopsys translate_off
|
$display(" INFO: Exception during second (NOP) delay slot instruction.");
|
$display(" INFO: Exception during second (NOP) delay slot instruction.");
|
// synopsys translate_on
|
// synopsys translate_on
|
`endif
|
`endif
|
end
|
end
|
else if (delayed2_ex_dslot) begin
|
else if (delayed2_ex_dslot) begin
|
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
// synopsys translate_off
|
// synopsys translate_off
|
$display(" INFO: Exception during third delay slot (SHOULD NOT HAPPEN).");
|
$display(" INFO: Exception during third delay slot (SHOULD NOT HAPPEN).");
|
// synopsys translate_on
|
// synopsys translate_on
|
`endif
|
`endif
|
end
|
end
|
else begin
|
else begin
|
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
// synopsys translate_off
|
// synopsys translate_off
|
$display(" INFO: Exception during normal (no delay slot) instruction.");
|
$display(" INFO: Exception during normal (no delay slot) instruction.");
|
// synopsys translate_on
|
// synopsys translate_on
|
`endif
|
`endif
|
end
|
end
|
|
|
esr <= #1 sr;
|
esr <= #1 sr;
|
casex (except_trig)
|
casex (except_trig)
|
13'b1_xxxx_xxxx_xxxx: begin
|
13'b1_xxxx_xxxx_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_HPINT;
|
except_type <= #1 `OR1200_EXCEPT_HPINT;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
end
|
end
|
13'b0_1xxx_xxxx_xxxx: begin
|
13'b0_1xxx_xxxx_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
|
except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
|
eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
end
|
end
|
13'b0_01xx_xxxx_xxxx: begin
|
13'b0_01xx_xxxx_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_IPF;
|
except_type <= #1 `OR1200_EXCEPT_IPF;
|
eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
end
|
end
|
13'b0_001x_xxxx_xxxx: begin
|
13'b0_001x_xxxx_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_BUSERR;
|
except_type <= #1 `OR1200_EXCEPT_BUSERR;
|
eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
end
|
end
|
13'b0_0001_xxxx_xxxx: begin
|
13'b0_0001_xxxx_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
|
except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
end
|
end
|
13'b0_0000_1xxx_xxxx: begin
|
13'b0_0000_1xxx_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_ALIGN;
|
except_type <= #1 `OR1200_EXCEPT_ALIGN;
|
eear <= #1 lsu_addr;
|
eear <= #1 lsu_addr;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
end
|
end
|
13'b0_0000_01xx_xxxx: begin
|
13'b0_0000_01xx_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
|
except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
|
eear <= #1 lsu_addr;
|
eear <= #1 lsu_addr;
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
end
|
end
|
13'b0_0000_001x_xxxx: begin
|
13'b0_0000_001x_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_DPF;
|
except_type <= #1 `OR1200_EXCEPT_DPF;
|
eear <= #1 lsu_addr;
|
eear <= #1 lsu_addr;
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
end
|
end
|
13'b0_0000_0001_xxxx: begin
|
13'b0_0000_0001_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_BUSERR;
|
except_type <= #1 `OR1200_EXCEPT_BUSERR;
|
eear <= #1 lsu_addr;
|
eear <= #1 lsu_addr;
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
end
|
end
|
13'b0_0000_0000_1xxx: begin
|
13'b0_0000_0000_1xxx: begin
|
except_type <= #1 `OR1200_EXCEPT_LPINT;
|
except_type <= #1 `OR1200_EXCEPT_LPINT;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
end
|
end
|
13'b0_0000_0000_01xx: begin
|
13'b0_0000_0000_01xx: begin
|
except_type <= #1 `OR1200_EXCEPT_RANGE;
|
except_type <= #1 `OR1200_EXCEPT_RANGE;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
end
|
end
|
13'b0_0000_0000_001x: begin
|
13'b0_0000_0000_001x: begin
|
except_type <= #1 `OR1200_EXCEPT_TRAP;
|
except_type <= #1 `OR1200_EXCEPT_TRAP;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
end
|
end
|
13'b0_0000_0000_0001: begin
|
13'b0_0000_0000_0001: begin
|
except_type <= #1 `OR1200_EXCEPT_SYSCALL;
|
except_type <= #1 `OR1200_EXCEPT_SYSCALL;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
end
|
end
|
default:
|
default:
|
except_type <= #1 `OR1200_EXCEPT_NONE;
|
except_type <= #1 `OR1200_EXCEPT_NONE;
|
endcase
|
endcase
|
end
|
end
|
else if (pc_we) begin
|
else if (pc_we) begin
|
state <= #1 `OR1200_EXCEPTFSM_FLU1;
|
state <= #1 `OR1200_EXCEPTFSM_FLU1;
|
extend_flush <= #1 1'b1;
|
extend_flush <= #1 1'b1;
|
end
|
end
|
else begin
|
else begin
|
if (epcr_we)
|
if (epcr_we)
|
epcr <= #1 datain;
|
epcr <= #1 datain;
|
if (eear_we)
|
if (eear_we)
|
eear <= #1 datain;
|
eear <= #1 datain;
|
if (esr_we)
|
if (esr_we)
|
esr <= #1 {datain[`OR1200_SR_WIDTH-1:2], 1'b1, datain[0]};
|
esr <= #1 {datain[`OR1200_SR_WIDTH-1:2], 1'b1, datain[0]};
|
end
|
end
|
`OR1200_EXCEPTFSM_FLU1:
|
`OR1200_EXCEPTFSM_FLU1:
|
// if (!if_stall & !id_freeze)
|
// if (!if_stall & !id_freeze)
|
state <= #1 `OR1200_EXCEPTFSM_FLU2;
|
state <= #1 `OR1200_EXCEPTFSM_FLU2;
|
`OR1200_EXCEPTFSM_FLU2:
|
`OR1200_EXCEPTFSM_FLU2:
|
if (except_type == `OR1200_EXCEPT_TRAP) begin
|
if (except_type == `OR1200_EXCEPT_TRAP) begin
|
state <= #1 `OR1200_EXCEPTFSM_IDLE;
|
state <= #1 `OR1200_EXCEPTFSM_IDLE;
|
extend_flush <= #1 1'b0;
|
extend_flush <= #1 1'b0;
|
extend_flush_last <= #1 1'b0;
|
extend_flush_last <= #1 1'b0;
|
except_type <= #1 `OR1200_EXCEPT_NONE;
|
except_type <= #1 `OR1200_EXCEPT_NONE;
|
end
|
end
|
else
|
else
|
// if (!if_stall & !id_freeze)
|
// if (!if_stall & !id_freeze)
|
state <= #1 `OR1200_EXCEPTFSM_FLU3;
|
state <= #1 `OR1200_EXCEPTFSM_FLU3;
|
`OR1200_EXCEPTFSM_FLU3:
|
`OR1200_EXCEPTFSM_FLU3:
|
// if (!if_stall && !id_freeze)
|
// if (!if_stall && !id_freeze)
|
begin
|
begin
|
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
// synopsys translate_off
|
// synopsys translate_off
|
if (except_flushpipe)
|
if (except_flushpipe)
|
$display(" INFO: EPCR0 %h EEAR %h ESR %h", epcr, eear, esr);
|
$display(" INFO: EPCR0 %h EEAR %h ESR %h", epcr, eear, esr);
|
// synopsys translate_on
|
// synopsys translate_on
|
`endif
|
`endif
|
state <= #1 `OR1200_EXCEPTFSM_FLU4;
|
state <= #1 `OR1200_EXCEPTFSM_FLU4;
|
end
|
end
|
`OR1200_EXCEPTFSM_FLU4: begin
|
`OR1200_EXCEPTFSM_FLU4: begin
|
state <= #1 `OR1200_EXCEPTFSM_FLU5;
|
state <= #1 `OR1200_EXCEPTFSM_FLU5;
|
extend_flush <= #1 1'b0;
|
extend_flush <= #1 1'b0;
|
extend_flush_last <= #1 1'b0; // damjan
|
extend_flush_last <= #1 1'b0; // damjan
|
end
|
end
|
`OR1200_EXCEPTFSM_FLU5: begin
|
`OR1200_EXCEPTFSM_FLU5: begin
|
if (!if_stall && !id_freeze) begin
|
if (!if_stall && !id_freeze) begin
|
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
// synopsys translate_off
|
// synopsys translate_off
|
$display(" INFO: Just finished flushing pipeline.");
|
$display(" INFO: Just finished flushing pipeline.");
|
// synopsys translate_on
|
// synopsys translate_on
|
`endif
|
`endif
|
state <= #1 `OR1200_EXCEPTFSM_IDLE;
|
state <= #1 `OR1200_EXCEPTFSM_IDLE;
|
except_type <= #1 `OR1200_EXCEPT_NONE;
|
except_type <= #1 `OR1200_EXCEPT_NONE;
|
extend_flush_last <= #1 1'b0;
|
extend_flush_last <= #1 1'b0;
|
end
|
end
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
