//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's WISHBONE BIU ////
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//// OR1200's WISHBONE BIU ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Implements WISHBONE interface ////
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//// Implements WISHBONE interface ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - if biu_cyc/stb are deasserted and wb_ack_i is asserted ////
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//// - if biu_cyc/stb are deasserted and wb_ack_i is asserted ////
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//// and this happens even before aborted_r is asssrted, ////
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//// and this happens even before aborted_r is asssrted, ////
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//// wb_ack_i will be delivered even though transfer is ////
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//// wb_ack_i will be delivered even though transfer is ////
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//// internally considered already aborted. However most ////
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//// internally considered already aborted. However most ////
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//// wb_ack_i are externally registered and delayed. Normally ////
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//// wb_ack_i are externally registered and delayed. Normally ////
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//// this shouldn't cause any problems. ////
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//// this shouldn't cause any problems. ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6.4.1 2003/07/08 15:36:37 lampret
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// Revision 1.6.4.1 2003/07/08 15:36:37 lampret
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// Added embedded memory QMEM.
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// Added embedded memory QMEM.
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//
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//
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// Revision 1.6 2003/04/07 20:57:46 lampret
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// Revision 1.6 2003/04/07 20:57:46 lampret
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// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Fixed order of ifdefs.
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// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Fixed order of ifdefs.
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//
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//
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// Revision 1.5 2002/12/08 08:57:56 lampret
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// Revision 1.5 2002/12/08 08:57:56 lampret
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// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
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// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
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//
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//
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// Revision 1.4 2002/09/16 03:09:16 lampret
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// Revision 1.4 2002/09/16 03:09:16 lampret
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// Fixed a combinational loop.
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// Fixed a combinational loop.
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//
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//
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// Revision 1.3 2002/08/12 05:31:37 lampret
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// Revision 1.3 2002/08/12 05:31:37 lampret
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// Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers.
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// Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers.
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//
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//
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// Revision 1.2 2002/07/14 22:17:17 lampret
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// Revision 1.2 2002/07/14 22:17:17 lampret
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// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
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// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
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//
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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//
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// Revision 1.12 2001/11/22 13:42:51 lampret
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// Revision 1.12 2001/11/22 13:42:51 lampret
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// Added wb_cyc_o assignment after it was removed by accident.
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// Added wb_cyc_o assignment after it was removed by accident.
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//
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//
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// Revision 1.11 2001/11/20 21:28:10 lampret
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// Revision 1.11 2001/11/20 21:28:10 lampret
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// Added optional sampling of inputs.
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// Added optional sampling of inputs.
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//
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//
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// Revision 1.10 2001/11/18 11:32:00 lampret
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// Revision 1.10 2001/11/18 11:32:00 lampret
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// OR1200_REGISTERED_OUTPUTS can now be enabled.
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// OR1200_REGISTERED_OUTPUTS can now be enabled.
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//
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//
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// Revision 1.9 2001/10/21 17:57:16 lampret
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// Revision 1.9 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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//
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// Revision 1.8 2001/10/14 13:12:10 lampret
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// Revision 1.8 2001/10/14 13:12:10 lampret
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// MP3 version.
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// MP3 version.
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//
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//
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// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
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// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
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// no message
|
// no message
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//
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//
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// Revision 1.3 2001/08/09 13:39:33 lampret
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// Revision 1.3 2001/08/09 13:39:33 lampret
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// Major clean-up.
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// Major clean-up.
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//
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//
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// Revision 1.2 2001/07/22 03:31:54 lampret
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// Revision 1.2 2001/07/22 03:31:54 lampret
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// Fixed RAM's oen bug. Cache bypass under development.
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// Fixed RAM's oen bug. Cache bypass under development.
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//
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//
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// Revision 1.1 2001/07/20 00:46:23 lampret
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// Revision 1.1 2001/07/20 00:46:23 lampret
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// Development version of RTL. Libraries are missing.
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// Development version of RTL. Libraries are missing.
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//
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//
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//
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//
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|
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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|
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module or1200_iwb_biu(
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module or1200_iwb_biu(
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// RISC clock, reset and clock control
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// RISC clock, reset and clock control
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clk, rst, clmode,
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clk, rst, clmode,
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|
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// WISHBONE interface
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// WISHBONE interface
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wb_clk_i, wb_rst_i, wb_ack_i, wb_err_i, wb_rty_i, wb_dat_i,
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wb_clk_i, wb_rst_i, wb_ack_i, wb_err_i, wb_rty_i, wb_dat_i,
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wb_cyc_o, wb_adr_o, wb_stb_o, wb_we_o, wb_sel_o, wb_dat_o,
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wb_cyc_o, wb_adr_o, wb_stb_o, wb_we_o, wb_sel_o, wb_dat_o,
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`ifdef OR1200_WB_CAB
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`ifdef OR1200_WB_CAB
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wb_cab_o,
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wb_cab_o,
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`endif
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`endif
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`ifdef OR1200_WB_B3
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`ifdef OR1200_WB_B3
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wb_cti_o, wb_bte_o,
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wb_cti_o, wb_bte_o,
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`endif
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`endif
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// Internal RISC bus
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// Internal RISC bus
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biu_dat_i, biu_adr_i, biu_cyc_i, biu_stb_i, biu_we_i, biu_sel_i, biu_cab_i,
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biu_dat_i, biu_adr_i, biu_cyc_i, biu_stb_i, biu_we_i, biu_sel_i, biu_cab_i,
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biu_dat_o, biu_ack_o, biu_err_o
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biu_dat_o, biu_ack_o, biu_err_o
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);
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);
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|
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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|
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//
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//
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// RISC clock, reset and clock control
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// RISC clock, reset and clock control
|
//
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//
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input clk; // RISC clock
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input clk; // RISC clock
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input rst; // RISC reset
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input rst; // RISC reset
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input [1:0] clmode; // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
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input [1:0] clmode; // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
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|
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//
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//
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// WISHBONE interface
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// WISHBONE interface
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//
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//
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input wb_clk_i; // clock input
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input wb_clk_i; // clock input
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input wb_rst_i; // reset input
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input wb_rst_i; // reset input
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input wb_ack_i; // normal termination
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input wb_ack_i; // normal termination
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input wb_err_i; // termination w/ error
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input wb_err_i; // termination w/ error
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input wb_rty_i; // termination w/ retry
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input wb_rty_i; // termination w/ retry
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input [dw-1:0] wb_dat_i; // input data bus
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input [dw-1:0] wb_dat_i; // input data bus
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output wb_cyc_o; // cycle valid output
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output wb_cyc_o; // cycle valid output
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output [aw-1:0] wb_adr_o; // address bus outputs
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output [aw-1:0] wb_adr_o; // address bus outputs
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output wb_stb_o; // strobe output
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output wb_stb_o; // strobe output
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output wb_we_o; // indicates write transfer
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output wb_we_o; // indicates write transfer
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output [3:0] wb_sel_o; // byte select outputs
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output [3:0] wb_sel_o; // byte select outputs
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output [dw-1:0] wb_dat_o; // output data bus
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output [dw-1:0] wb_dat_o; // output data bus
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`ifdef OR1200_WB_CAB
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`ifdef OR1200_WB_CAB
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output wb_cab_o; // consecutive address burst
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output wb_cab_o; // consecutive address burst
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`endif
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`endif
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`ifdef OR1200_WB_B3
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`ifdef OR1200_WB_B3
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output [2:0] wb_cti_o; // cycle type identifier
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output [2:0] wb_cti_o; // cycle type identifier
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output [1:0] wb_bte_o; // burst type extension
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output [1:0] wb_bte_o; // burst type extension
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`endif
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`endif
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//
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//
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// Internal RISC interface
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// Internal RISC interface
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//
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//
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input [dw-1:0] biu_dat_i; // input data bus
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input [dw-1:0] biu_dat_i; // input data bus
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input [aw-1:0] biu_adr_i; // address bus
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input [aw-1:0] biu_adr_i; // address bus
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input biu_cyc_i; // WB cycle
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input biu_cyc_i; // WB cycle
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input biu_stb_i; // WB strobe
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input biu_stb_i; // WB strobe
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input biu_we_i; // WB write enable
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input biu_we_i; // WB write enable
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input biu_cab_i; // CAB input
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input biu_cab_i; // CAB input
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input [3:0] biu_sel_i; // byte selects
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input [3:0] biu_sel_i; // byte selects
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output [31:0] biu_dat_o; // output data bus
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output [31:0] biu_dat_o; // output data bus
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output biu_ack_o; // ack output
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output biu_ack_o; // ack output
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output biu_err_o; // err output
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output biu_err_o; // err output
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|
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//
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//
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// Registers
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// Registers
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//
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//
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reg [1:0] valid_div; // Used for synchronization
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reg [1:0] valid_div; // Used for synchronization
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`ifdef OR1200_REGISTERED_OUTPUTS
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`ifdef OR1200_REGISTERED_OUTPUTS
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reg [aw-1:0] wb_adr_o; // address bus outputs
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reg [aw-1:0] wb_adr_o; // address bus outputs
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reg wb_cyc_o; // cycle output
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reg wb_cyc_o; // cycle output
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reg wb_stb_o; // strobe output
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reg wb_stb_o; // strobe output
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reg wb_we_o; // indicates write transfer
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reg wb_we_o; // indicates write transfer
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reg [3:0] wb_sel_o; // byte select outputs
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reg [3:0] wb_sel_o; // byte select outputs
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`ifdef OR1200_WB_CAB
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`ifdef OR1200_WB_CAB
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reg wb_cab_o; // CAB output
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reg wb_cab_o; // CAB output
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`endif
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`endif
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`ifdef OR1200_WB_B3
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`ifdef OR1200_WB_B3
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reg [1:0] burst_len; // burst counter
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reg [1:0] burst_len; // burst counter
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reg [2:0] wb_cti_o; // cycle type identifier
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reg [2:0] wb_cti_o; // cycle type identifier
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`endif
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`endif
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reg [dw-1:0] wb_dat_o; // output data bus
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reg [dw-1:0] wb_dat_o; // output data bus
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`endif
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`endif
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`ifdef OR1200_REGISTERED_INPUTS
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`ifdef OR1200_REGISTERED_INPUTS
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reg long_ack_o; // normal termination
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reg long_ack_o; // normal termination
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reg long_err_o; // error termination
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reg long_err_o; // error termination
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reg [dw-1:0] biu_dat_o; // output data bus
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reg [dw-1:0] biu_dat_o; // output data bus
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`else
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`else
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wire long_ack_o; // normal termination
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wire long_ack_o; // normal termination
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wire long_err_o; // error termination
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wire long_err_o; // error termination
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`endif
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`endif
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wire aborted; // Graceful abort
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wire aborted; // Graceful abort
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reg aborted_r; // Graceful abort
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reg aborted_r; // Graceful abort
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wire retry; // Retry
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wire retry; // Retry
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`ifdef OR1200_WB_RETRY
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`ifdef OR1200_WB_RETRY
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reg [`OR1200_WB_RETRY-1:0] retry_cntr; // Retry counter
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reg [`OR1200_WB_RETRY-1:0] retry_cntr; // Retry counter
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`endif
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`endif
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reg previous_complete;
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reg previous_complete;
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wire same_addr;
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wire same_addr;
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wire repeated_access;
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wire repeated_access;
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reg repeated_access_ack;
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reg repeated_access_ack;
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reg [dw-1:0] wb_dat_r; // saved previous data read
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reg [dw-1:0] wb_dat_r; // saved previous data read
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|
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//
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//
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// WISHBONE I/F <-> Internal RISC I/F conversion
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// WISHBONE I/F <-> Internal RISC I/F conversion
|
//
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//
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|
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//
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//
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// Address bus
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// Address bus
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//
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//
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`ifdef OR1200_REGISTERED_OUTPUTS
|
`ifdef OR1200_REGISTERED_OUTPUTS
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always @(posedge wb_clk_i or posedge wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
if (wb_rst_i)
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if (wb_rst_i)
|
wb_adr_o <= #1 {aw{1'b0}};
|
wb_adr_o <= #1 {aw{1'b0}};
|
else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~aborted & ~(wb_stb_o & ~wb_ack_i) | biu_cab_i)
|
else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~aborted & ~(wb_stb_o & ~wb_ack_i) | biu_cab_i)
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wb_adr_o <= #1 biu_adr_i;
|
wb_adr_o <= #1 biu_adr_i;
|
`else
|
`else
|
assign wb_adr_o = biu_adr_i;
|
assign wb_adr_o = biu_adr_i;
|
`endif
|
`endif
|
|
|
//
|
//
|
// Same access as previous one, store previous read data
|
// Same access as previous one, store previous read data
|
//
|
//
|
assign same_addr = wb_adr_o == biu_adr_i;
|
assign same_addr = wb_adr_o == biu_adr_i;
|
assign repeated_access = same_addr & previous_complete;
|
assign repeated_access = same_addr & previous_complete;
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
wb_dat_r <= #1 32'h0000_0000;
|
wb_dat_r <= #1 32'h0000_0000;
|
else if (wb_ack_i)
|
else if (wb_ack_i)
|
wb_dat_r <= #1 wb_dat_i;
|
wb_dat_r <= #1 wb_dat_i;
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
repeated_access_ack <= #1 1'b0;
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repeated_access_ack <= #1 1'b0;
|
else if (repeated_access & biu_cyc_i & biu_stb_i)
|
else if (repeated_access & biu_cyc_i & biu_stb_i)
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repeated_access_ack <= #1 1'b1;
|
repeated_access_ack <= #1 1'b1;
|
else
|
else
|
repeated_access_ack <= #1 1'b0;
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repeated_access_ack <= #1 1'b0;
|
|
|
//
|
//
|
// Previous access completed
|
// Previous access completed
|
//
|
//
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
previous_complete <= #1 1'b0;
|
previous_complete <= #1 1'b0;
|
else if (wb_ack_i & biu_cyc_i & biu_stb_i)
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else if (wb_ack_i & biu_cyc_i & biu_stb_i)
|
previous_complete <= #1 1'b1;
|
previous_complete <= #1 1'b1;
|
else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~aborted & ~(wb_stb_o & ~wb_ack_i))
|
else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~aborted & ~(wb_stb_o & ~wb_ack_i))
|
previous_complete <= #1 1'b0;
|
previous_complete <= #1 1'b0;
|
|
|
//
|
//
|
// Input data bus
|
// Input data bus
|
//
|
//
|
`ifdef OR1200_REGISTERED_INPUTS
|
`ifdef OR1200_REGISTERED_INPUTS
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
biu_dat_o <= #1 32'h0000_0000;
|
biu_dat_o <= #1 32'h0000_0000;
|
else if (wb_ack_i)
|
else if (wb_ack_i)
|
biu_dat_o <= #1 wb_dat_i;
|
biu_dat_o <= #1 wb_dat_i;
|
`else
|
`else
|
assign biu_dat_o = repeated_access_ack ? wb_dat_r : wb_dat_i;
|
assign biu_dat_o = repeated_access_ack ? wb_dat_r : wb_dat_i;
|
`endif
|
`endif
|
|
|
//
|
//
|
// Output data bus
|
// Output data bus
|
//
|
//
|
`ifdef OR1200_REGISTERED_OUTPUTS
|
`ifdef OR1200_REGISTERED_OUTPUTS
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
wb_dat_o <= #1 {dw{1'b0}};
|
wb_dat_o <= #1 {dw{1'b0}};
|
else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~aborted)
|
else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~aborted)
|
wb_dat_o <= #1 biu_dat_i;
|
wb_dat_o <= #1 biu_dat_i;
|
`else
|
`else
|
assign wb_dat_o = biu_dat_i;
|
assign wb_dat_o = biu_dat_i;
|
`endif
|
`endif
|
|
|
//
|
//
|
// Valid_div counts RISC clock cycles by modulo 4
|
// Valid_div counts RISC clock cycles by modulo 4
|
// and is used to synchronize external WB i/f to
|
// and is used to synchronize external WB i/f to
|
// RISC clock
|
// RISC clock
|
//
|
//
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
valid_div <= #1 2'b0;
|
valid_div <= #1 2'b0;
|
else
|
else
|
valid_div <= #1 valid_div + 1'd1;
|
valid_div <= #1 valid_div + 1'd1;
|
|
|
//
|
//
|
// biu_ack_o is one RISC clock cycle long long_ack_o.
|
// biu_ack_o is one RISC clock cycle long long_ack_o.
|
// long_ack_o is one, two or four RISC clock cycles long because
|
// long_ack_o is one, two or four RISC clock cycles long because
|
// WISHBONE can work at 1, 1/2 or 1/4 RISC clock.
|
// WISHBONE can work at 1, 1/2 or 1/4 RISC clock.
|
//
|
//
|
assign biu_ack_o = (repeated_access_ack | long_ack_o) & ~aborted_r
|
assign biu_ack_o = (repeated_access_ack | long_ack_o) & ~aborted_r
|
`ifdef OR1200_CLKDIV_2_SUPPORTED
|
`ifdef OR1200_CLKDIV_2_SUPPORTED
|
& (valid_div[0] | ~clmode[0])
|
& (valid_div[0] | ~clmode[0])
|
`ifdef OR1200_CLKDIV_4_SUPPORTED
|
`ifdef OR1200_CLKDIV_4_SUPPORTED
|
& (valid_div[1] | ~clmode[1])
|
& (valid_div[1] | ~clmode[1])
|
`endif
|
`endif
|
`endif
|
`endif
|
;
|
;
|
|
|
//
|
//
|
// Acknowledgment of the data to the RISC
|
// Acknowledgment of the data to the RISC
|
//
|
//
|
// long_ack_o
|
// long_ack_o
|
//
|
//
|
`ifdef OR1200_REGISTERED_INPUTS
|
`ifdef OR1200_REGISTERED_INPUTS
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
long_ack_o <= #1 1'b0;
|
long_ack_o <= #1 1'b0;
|
else
|
else
|
long_ack_o <= #1 wb_ack_i & ~aborted;
|
long_ack_o <= #1 wb_ack_i & ~aborted;
|
`else
|
`else
|
assign long_ack_o = wb_ack_i;
|
assign long_ack_o = wb_ack_i;
|
`endif
|
`endif
|
|
|
//
|
//
|
// biu_err_o is one RISC clock cycle long long_err_o.
|
// biu_err_o is one RISC clock cycle long long_err_o.
|
// long_err_o is one, two or four RISC clock cycles long because
|
// long_err_o is one, two or four RISC clock cycles long because
|
// WISHBONE can work at 1, 1/2 or 1/4 RISC clock.
|
// WISHBONE can work at 1, 1/2 or 1/4 RISC clock.
|
//
|
//
|
assign biu_err_o = long_err_o
|
assign biu_err_o = long_err_o
|
`ifdef OR1200_CLKDIV_2_SUPPORTED
|
`ifdef OR1200_CLKDIV_2_SUPPORTED
|
& (valid_div[0] | ~clmode[0])
|
& (valid_div[0] | ~clmode[0])
|
`ifdef OR1200_CLKDIV_4_SUPPORTED
|
`ifdef OR1200_CLKDIV_4_SUPPORTED
|
& (valid_div[1] | ~clmode[1])
|
& (valid_div[1] | ~clmode[1])
|
`endif
|
`endif
|
`endif
|
`endif
|
;
|
;
|
|
|
//
|
//
|
// Error termination
|
// Error termination
|
//
|
//
|
// long_err_o
|
// long_err_o
|
//
|
//
|
`ifdef OR1200_REGISTERED_INPUTS
|
`ifdef OR1200_REGISTERED_INPUTS
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
long_err_o <= #1 1'b0;
|
long_err_o <= #1 1'b0;
|
else
|
else
|
long_err_o <= #1 wb_err_i & ~aborted;
|
long_err_o <= #1 wb_err_i & ~aborted;
|
`else
|
`else
|
assign long_err_o = wb_err_i & ~aborted_r;
|
assign long_err_o = wb_err_i & ~aborted_r;
|
`endif
|
`endif
|
|
|
//
|
//
|
// Retry counter
|
// Retry counter
|
//
|
//
|
// Assert 'retry' when 'wb_rty_i' is sampled high and keep it high
|
// Assert 'retry' when 'wb_rty_i' is sampled high and keep it high
|
// until retry counter doesn't expire
|
// until retry counter doesn't expire
|
//
|
//
|
`ifdef OR1200_WB_RETRY
|
`ifdef OR1200_WB_RETRY
|
assign retry = wb_rty_i | (|retry_cntr);
|
assign retry = wb_rty_i | (|retry_cntr);
|
`else
|
`else
|
assign retry = 1'b0;
|
assign retry = 1'b0;
|
`endif
|
`endif
|
`ifdef OR1200_WB_RETRY
|
`ifdef OR1200_WB_RETRY
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
retry_cntr <= #1 1'b0;
|
retry_cntr <= #1 1'b0;
|
else if (wb_rty_i)
|
else if (wb_rty_i)
|
retry_cntr <= #1 {`OR1200_WB_RETRY{1'b1}};
|
retry_cntr <= #1 {`OR1200_WB_RETRY{1'b1}};
|
else if (retry_cntr)
|
else if (retry_cntr)
|
retry_cntr <= #1 retry_cntr - 7'd1;
|
retry_cntr <= #1 retry_cntr - 7'd1;
|
`endif
|
`endif
|
|
|
//
|
//
|
// Graceful completion of aborted transfers
|
// Graceful completion of aborted transfers
|
//
|
//
|
// Assert 'aborted' when 1) current transfer is in progress (wb_stb_o; which
|
// Assert 'aborted' when 1) current transfer is in progress (wb_stb_o; which
|
// we know is only asserted together with wb_cyc_o) 2) and in next WB clock cycle
|
// we know is only asserted together with wb_cyc_o) 2) and in next WB clock cycle
|
// wb_stb_o would be deasserted (biu_cyc_i and biu_stb_i are low) 3) and
|
// wb_stb_o would be deasserted (biu_cyc_i and biu_stb_i are low) 3) and
|
// there is no termination of current transfer in this WB clock cycle (wb_ack_i
|
// there is no termination of current transfer in this WB clock cycle (wb_ack_i
|
// and wb_err_i are low).
|
// and wb_err_i are low).
|
// 'aborted_r' is registered 'aborted' and extended until this "aborted" transfer
|
// 'aborted_r' is registered 'aborted' and extended until this "aborted" transfer
|
// is properly terminated with wb_ack_i/wb_err_i.
|
// is properly terminated with wb_ack_i/wb_err_i.
|
//
|
//
|
assign aborted = wb_stb_o & ~(biu_cyc_i & biu_stb_i) & ~(wb_ack_i | wb_err_i);
|
assign aborted = wb_stb_o & ~(biu_cyc_i & biu_stb_i) & ~(wb_ack_i | wb_err_i);
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
aborted_r <= #1 1'b0;
|
aborted_r <= #1 1'b0;
|
else if (wb_ack_i | wb_err_i)
|
else if (wb_ack_i | wb_err_i)
|
aborted_r <= #1 1'b0;
|
aborted_r <= #1 1'b0;
|
else if (aborted)
|
else if (aborted)
|
aborted_r <= #1 1'b1;
|
aborted_r <= #1 1'b1;
|
|
|
//
|
//
|
// WB cyc_o
|
// WB cyc_o
|
//
|
//
|
// Either 1) normal transfer initiated by biu_cyc_i (and biu_cab_i if
|
// Either 1) normal transfer initiated by biu_cyc_i (and biu_cab_i if
|
// bursts are enabled) and possibly suspended by 'retry'
|
// bursts are enabled) and possibly suspended by 'retry'
|
// or 2) extended "aborted" transfer
|
// or 2) extended "aborted" transfer
|
//
|
//
|
`ifdef OR1200_REGISTERED_OUTPUTS
|
`ifdef OR1200_REGISTERED_OUTPUTS
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
wb_cyc_o <= #1 1'b0;
|
wb_cyc_o <= #1 1'b0;
|
else
|
else
|
`ifdef OR1200_NO_BURSTS
|
`ifdef OR1200_NO_BURSTS
|
wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i & ~retry & ~repeated_access | aborted & ~wb_ack_i;
|
wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i & ~retry & ~repeated_access | aborted & ~wb_ack_i;
|
`else
|
`else
|
wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i & ~retry & ~repeated_access | biu_cab_i | aborted & ~wb_ack_i;
|
wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i & ~retry & ~repeated_access | biu_cab_i | aborted & ~wb_ack_i;
|
`endif
|
`endif
|
`else
|
`else
|
`ifdef OR1200_NO_BURSTS
|
`ifdef OR1200_NO_BURSTS
|
assign wb_cyc_o = biu_cyc_i & ~retry;
|
assign wb_cyc_o = biu_cyc_i & ~retry;
|
`else
|
`else
|
assign wb_cyc_o = biu_cyc_i | biu_cab_i & ~retry;
|
assign wb_cyc_o = biu_cyc_i | biu_cab_i & ~retry;
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
//
|
//
|
// WB stb_o
|
// WB stb_o
|
//
|
//
|
`ifdef OR1200_REGISTERED_OUTPUTS
|
`ifdef OR1200_REGISTERED_OUTPUTS
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
wb_stb_o <= #1 1'b0;
|
wb_stb_o <= #1 1'b0;
|
else
|
else
|
wb_stb_o <= #1 (biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~retry & ~repeated_access | aborted & ~wb_ack_i;
|
wb_stb_o <= #1 (biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~retry & ~repeated_access | aborted & ~wb_ack_i;
|
`else
|
`else
|
assign wb_stb_o = biu_cyc_i & biu_stb_i;
|
assign wb_stb_o = biu_cyc_i & biu_stb_i;
|
`endif
|
`endif
|
|
|
//
|
//
|
// WB we_o
|
// WB we_o
|
//
|
//
|
`ifdef OR1200_REGISTERED_OUTPUTS
|
`ifdef OR1200_REGISTERED_OUTPUTS
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
wb_we_o <= #1 1'b0;
|
wb_we_o <= #1 1'b0;
|
else
|
else
|
wb_we_o <= #1 biu_cyc_i & biu_stb_i & biu_we_i | aborted & wb_we_o;
|
wb_we_o <= #1 biu_cyc_i & biu_stb_i & biu_we_i | aborted & wb_we_o;
|
`else
|
`else
|
assign wb_we_o = biu_cyc_i & biu_stb_i & biu_we_i;
|
assign wb_we_o = biu_cyc_i & biu_stb_i & biu_we_i;
|
`endif
|
`endif
|
|
|
//
|
//
|
// WB sel_o
|
// WB sel_o
|
//
|
//
|
`ifdef OR1200_REGISTERED_OUTPUTS
|
`ifdef OR1200_REGISTERED_OUTPUTS
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
wb_sel_o <= #1 4'b0000;
|
wb_sel_o <= #1 4'b0000;
|
else
|
else
|
wb_sel_o <= #1 biu_sel_i;
|
wb_sel_o <= #1 biu_sel_i;
|
`else
|
`else
|
assign wb_sel_o = biu_sel_i;
|
assign wb_sel_o = biu_sel_i;
|
`endif
|
`endif
|
|
|
`ifdef OR1200_WB_CAB
|
`ifdef OR1200_WB_CAB
|
//
|
//
|
// WB cab_o
|
// WB cab_o
|
//
|
//
|
`ifdef OR1200_REGISTERED_OUTPUTS
|
`ifdef OR1200_REGISTERED_OUTPUTS
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
wb_cab_o <= #1 1'b0;
|
wb_cab_o <= #1 1'b0;
|
else
|
else
|
wb_cab_o <= #1 biu_cab_i;
|
wb_cab_o <= #1 biu_cab_i;
|
`else
|
`else
|
assign wb_cab_o = biu_cab_i;
|
assign wb_cab_o = biu_cab_i;
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
`ifdef OR1200_WB_B3
|
`ifdef OR1200_WB_B3
|
//
|
//
|
// Count burst beats
|
// Count burst beats
|
//
|
//
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
burst_len <= #1 2'b00;
|
burst_len <= #1 2'b00;
|
else if (biu_cab_i && burst_len && wb_ack_i)
|
else if (biu_cab_i && burst_len && wb_ack_i)
|
burst_len <= #1 burst_len - 1'b1;
|
burst_len <= #1 burst_len - 1'b1;
|
else if (~biu_cab_i)
|
else if (~biu_cab_i)
|
burst_len <= #1 2'b11;
|
burst_len <= #1 2'b11;
|
|
|
//
|
//
|
// WB cti_o
|
// WB cti_o
|
//
|
//
|
`ifdef OR1200_REGISTERED_OUTPUTS
|
`ifdef OR1200_REGISTERED_OUTPUTS
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
wb_cti_o <= #1 3'b000; // classic cycle
|
wb_cti_o <= #1 3'b000; // classic cycle
|
`ifdef OR1200_NO_BURSTS
|
`ifdef OR1200_NO_BURSTS
|
else
|
else
|
wb_cti_o <= #1 3'b111; // end-of-burst
|
wb_cti_o <= #1 3'b111; // end-of-burst
|
`else
|
`else
|
else if (biu_cab_i && burst_len[1])
|
else if (biu_cab_i && burst_len[1])
|
wb_cti_o <= #1 3'b010; // incrementing burst cycle
|
wb_cti_o <= #1 3'b010; // incrementing burst cycle
|
else if (biu_cab_i && wb_ack_i)
|
else if (biu_cab_i && wb_ack_i)
|
wb_cti_o <= #1 3'b111; // end-of-burst
|
wb_cti_o <= #1 3'b111; // end-of-burst
|
`endif // OR1200_NO_BURSTS
|
`endif // OR1200_NO_BURSTS
|
`else
|
`else
|
Unsupported !!!;
|
Unsupported !!!;
|
`endif
|
`endif
|
|
|
//
|
//
|
// WB bte_o
|
// WB bte_o
|
//
|
//
|
assign wb_bte_o = 2'b01; // 4-beat wrap burst
|
assign wb_bte_o = 2'b01; // 4-beat wrap burst
|
|
|
`endif // OR1200_WB_B3
|
`endif // OR1200_WB_B3
|
|
|
endmodule
|
endmodule
|
|
|