//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's Load/Store unit ////
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//// OR1200's Load/Store unit ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Interface between CPU and DC. ////
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//// Interface between CPU and DC. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// - make it smaller and faster ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/02/11 04:33:17 lampret
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// Revision 1.3 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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//
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// Revision 1.2 2002/01/18 07:56:00 lampret
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// Revision 1.2 2002/01/18 07:56:00 lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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//
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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//
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// Revision 1.9 2001/11/30 18:59:47 simons
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// Revision 1.9 2001/11/30 18:59:47 simons
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// *** empty log message ***
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// *** empty log message ***
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//
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//
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// Revision 1.8 2001/10/21 17:57:16 lampret
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// Revision 1.8 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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//
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// Revision 1.7 2001/10/14 13:12:09 lampret
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// Revision 1.7 2001/10/14 13:12:09 lampret
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// MP3 version.
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// MP3 version.
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//
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//
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// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
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// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
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// no message
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// no message
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//
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//
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// Revision 1.2 2001/08/09 13:39:33 lampret
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// Revision 1.2 2001/08/09 13:39:33 lampret
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// Major clean-up.
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// Major clean-up.
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//
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//
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Development version of RTL. Libraries are missing.
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// Development version of RTL. Libraries are missing.
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//
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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module or1200_lsu(
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module or1200_lsu(
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// Internal i/f
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// Internal i/f
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addrbase, addrofs, lsu_op, lsu_datain, lsu_dataout, lsu_stall, lsu_unstall,
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addrbase, addrofs, lsu_op, lsu_datain, lsu_dataout, lsu_stall, lsu_unstall,
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du_stall, except_align, except_dtlbmiss, except_dmmufault, except_dbuserr,
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du_stall, except_align, except_dtlbmiss, except_dmmufault, except_dbuserr,
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// External i/f to DC
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// External i/f to DC
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dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
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dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
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dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i
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dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i
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);
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
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parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
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//
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//
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// I/O
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// I/O
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//
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//
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//
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//
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// Internal i/f
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// Internal i/f
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//
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//
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input [31:0] addrbase;
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input [31:0] addrbase;
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input [31:0] addrofs;
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input [31:0] addrofs;
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input [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
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input [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
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input [dw-1:0] lsu_datain;
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input [dw-1:0] lsu_datain;
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output [dw-1:0] lsu_dataout;
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output [dw-1:0] lsu_dataout;
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output lsu_stall;
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output lsu_stall;
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output lsu_unstall;
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output lsu_unstall;
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input du_stall;
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input du_stall;
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output except_align;
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output except_align;
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output except_dtlbmiss;
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output except_dtlbmiss;
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output except_dmmufault;
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output except_dmmufault;
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output except_dbuserr;
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output except_dbuserr;
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//
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//
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// External i/f to DC
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// External i/f to DC
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//
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//
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output [31:0] dcpu_adr_o;
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output [31:0] dcpu_adr_o;
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output dcpu_cycstb_o;
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output dcpu_cycstb_o;
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output dcpu_we_o;
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output dcpu_we_o;
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output [3:0] dcpu_sel_o;
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output [3:0] dcpu_sel_o;
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output [3:0] dcpu_tag_o;
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output [3:0] dcpu_tag_o;
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output [31:0] dcpu_dat_o;
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output [31:0] dcpu_dat_o;
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input [31:0] dcpu_dat_i;
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input [31:0] dcpu_dat_i;
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input dcpu_ack_i;
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input dcpu_ack_i;
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input dcpu_rty_i;
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input dcpu_rty_i;
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input dcpu_err_i;
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input dcpu_err_i;
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input [3:0] dcpu_tag_i;
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input [3:0] dcpu_tag_i;
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//
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//
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// Internal wires/regs
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// Internal wires/regs
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//
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//
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reg [3:0] dcpu_sel_o;
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reg [3:0] dcpu_sel_o;
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//
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//
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// Internal I/F assignments
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// Internal I/F assignments
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//
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//
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assign lsu_stall = dcpu_rty_i & dcpu_cycstb_o;
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assign lsu_stall = dcpu_rty_i & dcpu_cycstb_o;
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assign lsu_unstall = dcpu_ack_i;
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assign lsu_unstall = dcpu_ack_i;
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assign except_align = ((lsu_op == `OR1200_LSUOP_SH) | (lsu_op == `OR1200_LSUOP_LHZ) | (lsu_op == `OR1200_LSUOP_LHS)) & dcpu_adr_o[0]
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assign except_align = ((lsu_op == `OR1200_LSUOP_SH) | (lsu_op == `OR1200_LSUOP_LHZ) | (lsu_op == `OR1200_LSUOP_LHS)) & dcpu_adr_o[0]
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| ((lsu_op == `OR1200_LSUOP_SW) | (lsu_op == `OR1200_LSUOP_LWZ) | (lsu_op == `OR1200_LSUOP_LWS)) & |dcpu_adr_o[1:0];
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| ((lsu_op == `OR1200_LSUOP_SW) | (lsu_op == `OR1200_LSUOP_LWZ) | (lsu_op == `OR1200_LSUOP_LWS)) & |dcpu_adr_o[1:0];
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assign except_dtlbmiss = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_TE);
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assign except_dtlbmiss = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_TE);
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assign except_dmmufault = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_PE);
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assign except_dmmufault = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_PE);
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assign except_dbuserr = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_BE);
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assign except_dbuserr = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_BE);
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//
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//
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// External I/F assignments
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// External I/F assignments
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//
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//
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assign dcpu_adr_o = addrbase + addrofs;
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assign dcpu_adr_o = addrbase + addrofs;
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assign dcpu_cycstb_o = du_stall | lsu_unstall ? 1'b0 : |lsu_op;
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assign dcpu_cycstb_o = du_stall | lsu_unstall ? 1'b0 : |lsu_op;
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assign dcpu_we_o = lsu_op[3];
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assign dcpu_we_o = lsu_op[3];
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assign dcpu_tag_o = dcpu_cycstb_o ? `OR1200_DTAG_ND : `OR1200_DTAG_IDLE;
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assign dcpu_tag_o = dcpu_cycstb_o ? `OR1200_DTAG_ND : `OR1200_DTAG_IDLE;
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always @(lsu_op or dcpu_adr_o)
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always @(lsu_op or dcpu_adr_o)
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casex({lsu_op, dcpu_adr_o[1:0]})
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casex({lsu_op, dcpu_adr_o[1:0]})
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{`OR1200_LSUOP_SB, 2'b00} : dcpu_sel_o = 4'b1000;
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{`OR1200_LSUOP_SB, 2'b00} : dcpu_sel_o = 4'b1000;
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{`OR1200_LSUOP_SB, 2'b01} : dcpu_sel_o = 4'b0100;
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{`OR1200_LSUOP_SB, 2'b01} : dcpu_sel_o = 4'b0100;
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{`OR1200_LSUOP_SB, 2'b10} : dcpu_sel_o = 4'b0010;
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{`OR1200_LSUOP_SB, 2'b10} : dcpu_sel_o = 4'b0010;
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{`OR1200_LSUOP_SB, 2'b11} : dcpu_sel_o = 4'b0001;
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{`OR1200_LSUOP_SB, 2'b11} : dcpu_sel_o = 4'b0001;
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{`OR1200_LSUOP_SH, 2'b00} : dcpu_sel_o = 4'b1100;
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{`OR1200_LSUOP_SH, 2'b00} : dcpu_sel_o = 4'b1100;
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{`OR1200_LSUOP_SH, 2'b10} : dcpu_sel_o = 4'b0011;
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{`OR1200_LSUOP_SH, 2'b10} : dcpu_sel_o = 4'b0011;
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{`OR1200_LSUOP_SW, 2'b00} : dcpu_sel_o = 4'b1111;
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{`OR1200_LSUOP_SW, 2'b00} : dcpu_sel_o = 4'b1111;
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{`OR1200_LSUOP_LBZ, 2'b00}, {`OR1200_LSUOP_LBS, 2'b00} : dcpu_sel_o = 4'b1000;
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{`OR1200_LSUOP_LBZ, 2'b00}, {`OR1200_LSUOP_LBS, 2'b00} : dcpu_sel_o = 4'b1000;
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{`OR1200_LSUOP_LBZ, 2'b01}, {`OR1200_LSUOP_LBS, 2'b01} : dcpu_sel_o = 4'b0100;
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{`OR1200_LSUOP_LBZ, 2'b01}, {`OR1200_LSUOP_LBS, 2'b01} : dcpu_sel_o = 4'b0100;
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{`OR1200_LSUOP_LBZ, 2'b10}, {`OR1200_LSUOP_LBS, 2'b10} : dcpu_sel_o = 4'b0010;
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{`OR1200_LSUOP_LBZ, 2'b10}, {`OR1200_LSUOP_LBS, 2'b10} : dcpu_sel_o = 4'b0010;
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{`OR1200_LSUOP_LBZ, 2'b11}, {`OR1200_LSUOP_LBS, 2'b11} : dcpu_sel_o = 4'b0001;
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{`OR1200_LSUOP_LBZ, 2'b11}, {`OR1200_LSUOP_LBS, 2'b11} : dcpu_sel_o = 4'b0001;
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{`OR1200_LSUOP_LHZ, 2'b00}, {`OR1200_LSUOP_LHS, 2'b00} : dcpu_sel_o = 4'b1100;
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{`OR1200_LSUOP_LHZ, 2'b00}, {`OR1200_LSUOP_LHS, 2'b00} : dcpu_sel_o = 4'b1100;
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{`OR1200_LSUOP_LHZ, 2'b10}, {`OR1200_LSUOP_LHS, 2'b10} : dcpu_sel_o = 4'b0011;
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{`OR1200_LSUOP_LHZ, 2'b10}, {`OR1200_LSUOP_LHS, 2'b10} : dcpu_sel_o = 4'b0011;
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{`OR1200_LSUOP_LWZ, 2'b00}, {`OR1200_LSUOP_LWS, 2'b00} : dcpu_sel_o = 4'b1111;
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{`OR1200_LSUOP_LWZ, 2'b00}, {`OR1200_LSUOP_LWS, 2'b00} : dcpu_sel_o = 4'b1111;
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default : dcpu_sel_o = 4'b0000;
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default : dcpu_sel_o = 4'b0000;
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endcase
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endcase
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//
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//
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// Instantiation of Memory-to-regfile aligner
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// Instantiation of Memory-to-regfile aligner
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//
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//
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or1200_mem2reg or1200_mem2reg(
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or1200_mem2reg or1200_mem2reg(
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.addr(dcpu_adr_o[1:0]),
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.addr(dcpu_adr_o[1:0]),
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.lsu_op(lsu_op),
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.lsu_op(lsu_op),
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.memdata(dcpu_dat_i),
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.memdata(dcpu_dat_i),
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.regdata(lsu_dataout)
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.regdata(lsu_dataout)
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);
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);
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//
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//
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// Instantiation of Regfile-to-memory aligner
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// Instantiation of Regfile-to-memory aligner
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//
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//
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or1200_reg2mem or1200_reg2mem(
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or1200_reg2mem or1200_reg2mem(
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.addr(dcpu_adr_o[1:0]),
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.addr(dcpu_adr_o[1:0]),
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.lsu_op(lsu_op),
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.lsu_op(lsu_op),
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.regdata(lsu_datain),
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.regdata(lsu_datain),
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.memdata(dcpu_dat_o)
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.memdata(dcpu_dat_o)
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);
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);
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endmodule
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endmodule
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