//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Generic Single-Port Synchronous RAM with byte write signals ////
|
//// Generic Single-Port Synchronous RAM with byte write signals ////
|
//// ////
|
//// ////
|
//// This file is part of memory library available from ////
|
//// This file is part of memory library available from ////
|
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
|
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// This block is a wrapper with common single-port ////
|
//// This block is a wrapper with common single-port ////
|
//// synchronous memory interface for different ////
|
//// synchronous memory interface for different ////
|
//// types of ASIC and FPGA RAMs. Beside universal memory ////
|
//// types of ASIC and FPGA RAMs. Beside universal memory ////
|
//// interface it also provides behavioral model of generic ////
|
//// interface it also provides behavioral model of generic ////
|
//// single-port synchronous RAM. ////
|
//// single-port synchronous RAM. ////
|
//// It should be used in all OPENCORES designs that want to be ////
|
//// It should be used in all OPENCORES designs that want to be ////
|
//// portable accross different target technologies and ////
|
//// portable accross different target technologies and ////
|
//// independent of target memory. ////
|
//// independent of target memory. ////
|
//// ////
|
//// ////
|
//// Supported ASIC RAMs are: ////
|
//// Supported ASIC RAMs are: ////
|
//// - Artisan Single-Port Sync RAM ////
|
//// - Artisan Single-Port Sync RAM ////
|
//// - Avant! Two-Port Sync RAM (*) ////
|
//// - Avant! Two-Port Sync RAM (*) ////
|
//// - Virage Single-Port Sync RAM ////
|
//// - Virage Single-Port Sync RAM ////
|
//// - Virtual Silicon Single-Port Sync RAM ////
|
//// - Virtual Silicon Single-Port Sync RAM ////
|
//// ////
|
//// ////
|
//// Supported FPGA RAMs are: ////
|
//// Supported FPGA RAMs are: ////
|
//// - Xilinx Virtex RAMB4_S16 ////
|
//// - Xilinx Virtex RAMB4_S16 ////
|
//// - Altera LPM ////
|
//// - Altera LPM ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - xilinx rams need external tri-state logic ////
|
//// - xilinx rams need external tri-state logic ////
|
//// - fix avant! two-port ram ////
|
//// - fix avant! two-port ram ////
|
//// - add additional RAMs ////
|
//// - add additional RAMs ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Damjan Lampret, lampret@opencores.org ////
|
//// - Damjan Lampret, lampret@opencores.org ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.1 2003/08/26 09:37:02 simons
|
|
// Added support for rams with byte write access.
|
|
//
|
//
|
//
|
|
|
// synopsys translate_off
|
// synopsys translate_off
|
`include "timescale.v"
|
`include "timescale.v"
|
// synopsys translate_on
|
// synopsys translate_on
|
`include "or1200_defines.v"
|
`include "or1200_defines.v"
|
|
|
module or1200_spram_2048x32_bw(
|
module or1200_spram_2048x32_bw(
|
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
// RAM BIST
|
// RAM BIST
|
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
|
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
|
`endif
|
`endif
|
// Generic synchronous single-port RAM interface
|
// Generic synchronous single-port RAM interface
|
clk, rst, ce, we, oe, addr, di, do
|
clk, rst, ce, we, oe, addr, di, do
|
);
|
);
|
|
|
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
//
|
//
|
// RAM BIST
|
// RAM BIST
|
//
|
//
|
input scanb_rst,
|
input scanb_rst,
|
scanb_si,
|
scanb_si,
|
scanb_en,
|
scanb_en,
|
scanb_clk;
|
scanb_clk;
|
output scanb_so;
|
output scanb_so;
|
`endif
|
`endif
|
|
|
//
|
//
|
// Generic synchronous single-port RAM interface
|
// Generic synchronous single-port RAM interface
|
//
|
//
|
input clk; // Clock
|
input clk; // Clock
|
input rst; // Reset
|
input rst; // Reset
|
input ce; // Chip enable input
|
input ce; // Chip enable input
|
input [3:0] we; // Write enable input
|
input [3:0] we; // Write enable input
|
input oe; // Output enable input
|
input oe; // Output enable input
|
input [10:0] addr; // address bus inputs
|
input [10:0] addr; // address bus inputs
|
input [31:0] di; // input data bus
|
input [31:0] di; // input data bus
|
output [31:0] do; // output data bus
|
output [31:0] do; // output data bus
|
|
|
//
|
//
|
// Internal wires and registers
|
// Internal wires and registers
|
//
|
//
|
|
|
`ifdef OR1200_ARTISAN_SSP
|
`ifdef OR1200_ARTISAN_SSP
|
`else
|
`else
|
`ifdef OR1200_VIRTUALSILICON_SSP
|
`ifdef OR1200_VIRTUALSILICON_SSP
|
`else
|
`else
|
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
assign scanb_so = scanb_si;
|
assign scanb_so = scanb_si;
|
`endif
|
`endif
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
|
|
`ifdef OR1200_ARTISAN_SSP
|
`ifdef OR1200_ARTISAN_SSP
|
|
|
//
|
//
|
// Instantiation of ASIC memory:
|
// Instantiation of ASIC memory:
|
//
|
//
|
// Artisan Synchronous Single-Port RAM (ra1sh)
|
// Artisan Synchronous Single-Port RAM (ra1sh)
|
//
|
//
|
`ifdef UNUSED
|
`ifdef UNUSED
|
art_hssp_2048x32_bw artisan_ssp(
|
art_hssp_2048x32_bw artisan_ssp(
|
`else
|
`else
|
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
art_hssp_2048x32_bw_bist artisan_ssp(
|
art_hssp_2048x32_bw_bist artisan_ssp(
|
`else
|
`else
|
art_hssp_2048x32_bw artisan_ssp(
|
art_hssp_2048x32_bw artisan_ssp(
|
`endif
|
`endif
|
`endif
|
`endif
|
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
// RAM BIST
|
// RAM BIST
|
.scanb_rst(scanb_rst),
|
.scanb_rst(scanb_rst),
|
.scanb_si(scanb_si),
|
.scanb_si(scanb_si),
|
.scanb_so(scanb_so),
|
.scanb_so(scanb_so),
|
.scanb_en(scanb_en),
|
.scanb_en(scanb_en),
|
.scanb_clk(scanb_clk),
|
.scanb_clk(scanb_clk),
|
`endif
|
`endif
|
.CLK(clk),
|
.CLK(clk),
|
.CEN(~ce),
|
.CEN(~ce),
|
.WEN(~we),
|
.WEN(~we),
|
.A(addr),
|
.A(addr),
|
.D(di),
|
.D(di),
|
.OEN(~oe),
|
.OEN(~oe),
|
.Q(do)
|
.Q(do)
|
);
|
);
|
|
|
`else
|
`else
|
|
|
`ifdef OR1200_AVANT_ATP
|
`ifdef OR1200_AVANT_ATP
|
|
|
//
|
//
|
// Instantiation of ASIC memory:
|
// Instantiation of ASIC memory:
|
//
|
//
|
// Avant! Asynchronous Two-Port RAM
|
// Avant! Asynchronous Two-Port RAM
|
//
|
//
|
avant_atp avant_atp(
|
avant_atp avant_atp(
|
.web(~we),
|
.web(~we),
|
.reb(),
|
.reb(),
|
.oeb(~oe),
|
.oeb(~oe),
|
.rcsb(),
|
.rcsb(),
|
.wcsb(),
|
.wcsb(),
|
.ra(addr),
|
.ra(addr),
|
.wa(addr),
|
.wa(addr),
|
.di(di),
|
.di(di),
|
.do(do)
|
.do(do)
|
);
|
);
|
|
|
`else
|
`else
|
|
|
`ifdef OR1200_VIRAGE_SSP
|
`ifdef OR1200_VIRAGE_SSP
|
|
|
//
|
//
|
// Instantiation of ASIC memory:
|
// Instantiation of ASIC memory:
|
//
|
//
|
// Virage Synchronous 1-port R/W RAM
|
// Virage Synchronous 1-port R/W RAM
|
//
|
//
|
virage_ssp virage_ssp(
|
virage_ssp virage_ssp(
|
.clk(clk),
|
.clk(clk),
|
.adr(addr),
|
.adr(addr),
|
.d(di),
|
.d(di),
|
.we(we),
|
.we(we),
|
.oe(oe),
|
.oe(oe),
|
.me(ce),
|
.me(ce),
|
.q(do)
|
.q(do)
|
);
|
);
|
|
|
`else
|
`else
|
|
|
`ifdef OR1200_VIRTUALSILICON_SSP
|
`ifdef OR1200_VIRTUALSILICON_SSP
|
|
|
//
|
//
|
// Instantiation of ASIC memory:
|
// Instantiation of ASIC memory:
|
//
|
//
|
// Virtual Silicon Single-Port Synchronous SRAM
|
// Virtual Silicon Single-Port Synchronous SRAM
|
//
|
//
|
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
wire scanb_si_ram_0;
|
wire scanb_si_ram_0;
|
wire scanb_si_ram_1;
|
wire scanb_si_ram_1;
|
wire scanb_si_ram_2;
|
wire scanb_si_ram_2;
|
wire scanb_si_ram_3;
|
wire scanb_si_ram_3;
|
wire scanb_so_ram_0;
|
wire scanb_so_ram_0;
|
wire scanb_so_ram_1;
|
wire scanb_so_ram_1;
|
wire scanb_so_ram_2;
|
wire scanb_so_ram_2;
|
wire scanb_so_ram_3;
|
wire scanb_so_ram_3;
|
assign scanb_si_ram_0 = scanb_si;
|
assign scanb_si_ram_0 = scanb_si;
|
assign scanb_si_ram_1 = scanb_so_ram_0;
|
assign scanb_si_ram_1 = scanb_so_ram_0;
|
assign scanb_si_ram_2 = scanb_so_ram_1;
|
assign scanb_si_ram_2 = scanb_so_ram_1;
|
assign scanb_si_ram_3 = scanb_so_ram_2;
|
assign scanb_si_ram_3 = scanb_so_ram_2;
|
assign scanb_so = scanb_so_ram_3;
|
assign scanb_so = scanb_so_ram_3;
|
`endif
|
`endif
|
|
|
`ifdef UNUSED
|
`ifdef UNUSED
|
vs_hdsp_2048x8 vs_ssp_0(
|
vs_hdsp_2048x8 vs_ssp_0(
|
`else
|
`else
|
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
vs_hdsp_2048x8_bist vs_ssp_0(
|
vs_hdsp_2048x8_bist vs_ssp_0(
|
`else
|
`else
|
vs_hdsp_2048x8 vs_ssp_0(
|
vs_hdsp_2048x8 vs_ssp_0(
|
`endif
|
`endif
|
`endif
|
`endif
|
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
// RAM BIST
|
// RAM BIST
|
.scanb_rst(scanb_rst),
|
.scanb_rst(scanb_rst),
|
.scanb_si(scanb_si_ram_0),
|
.scanb_si(scanb_si_ram_0),
|
.scanb_so(scanb_so_ram_0),
|
.scanb_so(scanb_so_ram_0),
|
.scanb_en(scanb_en),
|
.scanb_en(scanb_en),
|
.scanb_clk(scanb_clk),
|
.scanb_clk(scanb_clk),
|
`endif
|
`endif
|
.CK(clk),
|
.CK(clk),
|
.ADR(addr),
|
.ADR(addr),
|
.DI(di[7:0]),
|
.DI(di[7:0]),
|
.WEN(~we[0]),
|
.WEN(~we[0]),
|
.CEN(~ce),
|
.CEN(~ce),
|
.OEN(~oe),
|
.OEN(~oe),
|
.DOUT(do[7:0])
|
.DOUT(do[7:0])
|
);
|
);
|
|
|
`ifdef UNUSED
|
`ifdef UNUSED
|
vs_hdsp_2048x8 vs_ssp_1(
|
vs_hdsp_2048x8 vs_ssp_1(
|
`else
|
`else
|
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
vs_hdsp_2048x8_bist vs_ssp_1(
|
vs_hdsp_2048x8_bist vs_ssp_1(
|
`else
|
`else
|
vs_hdsp_2048x8 vs_ssp_1(
|
vs_hdsp_2048x8 vs_ssp_1(
|
`endif
|
`endif
|
`endif
|
`endif
|
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
// RAM BIST
|
// RAM BIST
|
.scanb_rst(scanb_rst),
|
.scanb_rst(scanb_rst),
|
.scanb_si(scanb_si_ram_1),
|
.scanb_si(scanb_si_ram_1),
|
.scanb_so(scanb_so_ram_1),
|
.scanb_so(scanb_so_ram_1),
|
.scanb_en(scanb_en),
|
.scanb_en(scanb_en),
|
.scanb_clk(scanb_clk),
|
.scanb_clk(scanb_clk),
|
`endif
|
`endif
|
.CK(clk),
|
.CK(clk),
|
.ADR(addr),
|
.ADR(addr),
|
.DI(di[15:8]),
|
.DI(di[15:8]),
|
.WEN(~we[1]),
|
.WEN(~we[1]),
|
.CEN(~ce),
|
.CEN(~ce),
|
.OEN(~oe),
|
.OEN(~oe),
|
.DOUT(do[15:8])
|
.DOUT(do[15:8])
|
);
|
);
|
|
|
`ifdef UNUSED
|
`ifdef UNUSED
|
vs_hdsp_2048x8 vs_ssp_2(
|
vs_hdsp_2048x8 vs_ssp_2(
|
`else
|
`else
|
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
vs_hdsp_2048x8_bist vs_ssp_2(
|
vs_hdsp_2048x8_bist vs_ssp_2(
|
`else
|
`else
|
vs_hdsp_2048x8 vs_ssp_2(
|
vs_hdsp_2048x8 vs_ssp_2(
|
`endif
|
`endif
|
`endif
|
`endif
|
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
// RAM BIST
|
// RAM BIST
|
.scanb_rst(scanb_rst),
|
.scanb_rst(scanb_rst),
|
.scanb_si(scanb_si_ram_2),
|
.scanb_si(scanb_si_ram_2),
|
.scanb_so(scanb_so_ram_2),
|
.scanb_so(scanb_so_ram_2),
|
.scanb_en(scanb_en),
|
.scanb_en(scanb_en),
|
.scanb_clk(scanb_clk),
|
.scanb_clk(scanb_clk),
|
`endif
|
`endif
|
.CK(clk),
|
.CK(clk),
|
.ADR(addr),
|
.ADR(addr),
|
.DI(di[23:16]),
|
.DI(di[23:16]),
|
.WEN(~we[2]),
|
.WEN(~we[2]),
|
.CEN(~ce),
|
.CEN(~ce),
|
.OEN(~oe),
|
.OEN(~oe),
|
.DOUT(do[23:16])
|
.DOUT(do[23:16])
|
);
|
);
|
|
|
`ifdef UNUSED
|
`ifdef UNUSED
|
vs_hdsp_2048x8 vs_ssp_3(
|
vs_hdsp_2048x8 vs_ssp_3(
|
`else
|
`else
|
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
vs_hdsp_2048x8_bist vs_ssp_3(
|
vs_hdsp_2048x8_bist vs_ssp_3(
|
`else
|
`else
|
vs_hdsp_2048x8 vs_ssp_3(
|
vs_hdsp_2048x8 vs_ssp_3(
|
`endif
|
`endif
|
`endif
|
`endif
|
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
// RAM BIST
|
// RAM BIST
|
.scanb_rst(scanb_rst),
|
.scanb_rst(scanb_rst),
|
.scanb_si(scanb_si_ram_3),
|
.scanb_si(scanb_si_ram_3),
|
.scanb_so(scanb_so_ram_3),
|
.scanb_so(scanb_so_ram_3),
|
.scanb_en(scanb_en),
|
.scanb_en(scanb_en),
|
.scanb_clk(scanb_clk),
|
.scanb_clk(scanb_clk),
|
`endif
|
`endif
|
.CK(clk),
|
.CK(clk),
|
.ADR(addr),
|
.ADR(addr),
|
.DI(di[31:24]),
|
.DI(di[31:24]),
|
.WEN(~we[3]),
|
.WEN(~we[3]),
|
.CEN(~ce),
|
.CEN(~ce),
|
.OEN(~oe),
|
.OEN(~oe),
|
.DOUT(do[31:24])
|
.DOUT(do[31:24])
|
);
|
);
|
|
|
`else
|
`else
|
|
|
`ifdef OR1200_XILINX_RAMB4
|
`ifdef OR1200_XILINX_RAMB4
|
|
|
//
|
//
|
// Instantiation of FPGA memory:
|
// Instantiation of FPGA memory:
|
//
|
//
|
// Virtex/Spartan2
|
// Virtex/Spartan2
|
//
|
//
|
|
|
//
|
//
|
// Block 0
|
// Block 0
|
//
|
//
|
RAMB4_S2 ramb4_s2_0(
|
RAMB4_S2 ramb4_s2_0(
|
.CLK(clk),
|
.CLK(clk),
|
.RST(rst),
|
.RST(rst),
|
.ADDR(addr),
|
.ADDR(addr),
|
.DI(di[1:0]),
|
.DI(di[1:0]),
|
.EN(ce),
|
.EN(ce),
|
.WE(we[0]),
|
.WE(we[0]),
|
.DO(do[1:0])
|
.DO(do[1:0])
|
);
|
);
|
|
|
//
|
//
|
// Block 1
|
// Block 1
|
//
|
//
|
RAMB4_S2 ramb4_s2_1(
|
RAMB4_S2 ramb4_s2_1(
|
.CLK(clk),
|
.CLK(clk),
|
.RST(rst),
|
.RST(rst),
|
.ADDR(addr),
|
.ADDR(addr),
|
.DI(di[3:2]),
|
.DI(di[3:2]),
|
.EN(ce),
|
.EN(ce),
|
.WE(we[0]),
|
.WE(we[0]),
|
.DO(do[3:2])
|
.DO(do[3:2])
|
);
|
);
|
|
|
//
|
//
|
// Block 2
|
// Block 2
|
//
|
//
|
RAMB4_S2 ramb4_s2_2(
|
RAMB4_S2 ramb4_s2_2(
|
.CLK(clk),
|
.CLK(clk),
|
.RST(rst),
|
.RST(rst),
|
.ADDR(addr),
|
.ADDR(addr),
|
.DI(di[5:4]),
|
.DI(di[5:4]),
|
.EN(ce),
|
.EN(ce),
|
.WE(we[0]),
|
.WE(we[0]),
|
.DO(do[5:4])
|
.DO(do[5:4])
|
);
|
);
|
|
|
//
|
//
|
// Block 3
|
// Block 3
|
//
|
//
|
RAMB4_S2 ramb4_s2_3(
|
RAMB4_S2 ramb4_s2_3(
|
.CLK(clk),
|
.CLK(clk),
|
.RST(rst),
|
.RST(rst),
|
.ADDR(addr),
|
.ADDR(addr),
|
.DI(di[7:6]),
|
.DI(di[7:6]),
|
.EN(ce),
|
.EN(ce),
|
.WE(we[0]),
|
.WE(we[0]),
|
.DO(do[7:6])
|
.DO(do[7:6])
|
|
);
|
//
|
//
|
// Block 4
|
// Block 4
|
//
|
//
|
RAMB4_S2 ramb4_s2_4(
|
RAMB4_S2 ramb4_s2_4(
|
.CLK(clk),
|
.CLK(clk),
|
.RST(rst),
|
.RST(rst),
|
.ADDR(addr),
|
.ADDR(addr),
|
.DI(di[9:8]),
|
.DI(di[9:8]),
|
.EN(ce),
|
.EN(ce),
|
.WE(we[1]),
|
.WE(we[1]),
|
.DO(do[9:8])
|
.DO(do[9:8])
|
);
|
);
|
|
|
//
|
//
|
// Block 5
|
// Block 5
|
//
|
//
|
RAMB4_S2 ramb4_s2_5(
|
RAMB4_S2 ramb4_s2_5(
|
.CLK(clk),
|
.CLK(clk),
|
.RST(rst),
|
.RST(rst),
|
.ADDR(addr),
|
.ADDR(addr),
|
.DI(di[11:10]),
|
.DI(di[11:10]),
|
.EN(ce),
|
.EN(ce),
|
.WE(we[1]),
|
.WE(we[1]),
|
.DO(do[11:10])
|
.DO(do[11:10])
|
);
|
);
|
|
|
//
|
//
|
// Block 6
|
// Block 6
|
//
|
//
|
RAMB4_S2 ramb4_s2_6(
|
RAMB4_S2 ramb4_s2_6(
|
.CLK(clk),
|
.CLK(clk),
|
.RST(rst),
|
.RST(rst),
|
.ADDR(addr),
|
.ADDR(addr),
|
.DI(di[13:12]),
|
.DI(di[13:12]),
|
.EN(ce),
|
.EN(ce),
|
.WE(we[1]),
|
.WE(we[1]),
|
.DO(do[13:12])
|
.DO(do[13:12])
|
);
|
);
|
|
|
//
|
//
|
// Block 7
|
// Block 7
|
//
|
//
|
RAMB4_S2 ramb4_s2_7(
|
RAMB4_S2 ramb4_s2_7(
|
.CLK(clk),
|
.CLK(clk),
|
.RST(rst),
|
.RST(rst),
|
.ADDR(addr),
|
.ADDR(addr),
|
.DI(di[15:14]),
|
.DI(di[15:14]),
|
.EN(ce),
|
.EN(ce),
|
.WE(we[1]),
|
.WE(we[1]),
|
.DO(do[15:14])
|
.DO(do[15:14])
|
|
);
|
//
|
//
|
// Block 8
|
// Block 8
|
//
|
//
|
RAMB4_S2 ramb4_s2_8(
|
RAMB4_S2 ramb4_s2_8(
|
.CLK(clk),
|
.CLK(clk),
|
.RST(rst),
|
.RST(rst),
|
.ADDR(addr),
|
.ADDR(addr),
|
.DI(di[17:16]),
|
.DI(di[17:16]),
|
.EN(ce),
|
.EN(ce),
|
.WE(we[2]),
|
.WE(we[2]),
|
.DO(do[17:16])
|
.DO(do[17:16])
|
);
|
);
|
|
|
//
|
//
|
// Block 9
|
// Block 9
|
//
|
//
|
RAMB4_S2 ramb4_s2_9(
|
RAMB4_S2 ramb4_s2_9(
|
.CLK(clk),
|
.CLK(clk),
|
.RST(rst),
|
.RST(rst),
|
.ADDR(addr),
|
.ADDR(addr),
|
.DI(di[19:18]),
|
.DI(di[19:18]),
|
.EN(ce),
|
.EN(ce),
|
.WE(we[2]),
|
.WE(we[2]),
|
.DO(do[19:18])
|
.DO(do[19:18])
|
);
|
);
|
|
|
//
|
//
|
// Block 10
|
// Block 10
|
//
|
//
|
RAMB4_S2 ramb4_s2_10(
|
RAMB4_S2 ramb4_s2_10(
|
.CLK(clk),
|
.CLK(clk),
|
.RST(rst),
|
.RST(rst),
|
.ADDR(addr),
|
.ADDR(addr),
|
.DI(di[21:20]),
|
.DI(di[21:20]),
|
.EN(ce),
|
.EN(ce),
|
.WE(we[2]),
|
.WE(we[2]),
|
.DO(do[21:20])
|
.DO(do[21:20])
|
);
|
);
|
|
|
//
|
//
|
// Block 11
|
// Block 11
|
//
|
//
|
RAMB4_S2 ramb4_s2_11(
|
RAMB4_S2 ramb4_s2_11(
|
.CLK(clk),
|
.CLK(clk),
|
.RST(rst),
|
.RST(rst),
|
.ADDR(addr),
|
.ADDR(addr),
|
.DI(di[23:22]),
|
.DI(di[23:22]),
|
.EN(ce),
|
.EN(ce),
|
.WE(we[2]),
|
.WE(we[2]),
|
.DO(do[23:22])
|
.DO(do[23:22])
|
|
);
|
//
|
//
|
// Block 12
|
// Block 12
|
//
|
//
|
RAMB4_S2 ramb4_s2_12(
|
RAMB4_S2 ramb4_s2_12(
|
.CLK(clk),
|
.CLK(clk),
|
.RST(rst),
|
.RST(rst),
|
.ADDR(addr),
|
.ADDR(addr),
|
.DI(di[25:24]),
|
.DI(di[25:24]),
|
.EN(ce),
|
.EN(ce),
|
.WE(we[3]),
|
.WE(we[3]),
|
.DO(do[25:24])
|
.DO(do[25:24])
|
);
|
);
|
|
|
//
|
//
|
// Block 13
|
// Block 13
|
//
|
//
|
RAMB4_S2 ramb4_s2_13(
|
RAMB4_S2 ramb4_s2_13(
|
.CLK(clk),
|
.CLK(clk),
|
.RST(rst),
|
.RST(rst),
|
.ADDR(addr),
|
.ADDR(addr),
|
.DI(di[27:26]),
|
.DI(di[27:26]),
|
.EN(ce),
|
.EN(ce),
|
.WE(we[3]),
|
.WE(we[3]),
|
.DO(do[27:26])
|
.DO(do[27:26])
|
);
|
);
|
|
|
//
|
//
|
// Block 14
|
// Block 14
|
//
|
//
|
RAMB4_S2 ramb4_s2_14(
|
RAMB4_S2 ramb4_s2_14(
|
.CLK(clk),
|
.CLK(clk),
|
.RST(rst),
|
.RST(rst),
|
.ADDR(addr),
|
.ADDR(addr),
|
.DI(di[29:28]),
|
.DI(di[29:28]),
|
.EN(ce),
|
.EN(ce),
|
.WE(we[3]),
|
.WE(we[3]),
|
.DO(do[29:28])
|
.DO(do[29:28])
|
);
|
);
|
|
|
//
|
//
|
// Block 15
|
// Block 15
|
//
|
//
|
RAMB4_S2 ramb4_s2_15(
|
RAMB4_S2 ramb4_s2_15(
|
.CLK(clk),
|
.CLK(clk),
|
.RST(rst),
|
.RST(rst),
|
.ADDR(addr),
|
.ADDR(addr),
|
.DI(di[31:30]),
|
.DI(di[31:30]),
|
.EN(ce),
|
.EN(ce),
|
.WE(we[3]),
|
.WE(we[3]),
|
.DO(do[31:30])
|
.DO(do[31:30])
|
|
);
|
|
|
`else
|
`else
|
|
|
//
|
//
|
// Generic single-port synchronous RAM model
|
// Generic single-port synchronous RAM model
|
//
|
//
|
|
|
//
|
//
|
// Generic RAM's registers and wires
|
// Generic RAM's registers and wires
|
//
|
//
|
reg [31:0] mem_0 [10:0]; // RAM content
|
reg [31:0] mem_0 [10:0]; // RAM content
|
reg [31:0] mem_1 [10:0]; // RAM content
|
reg [31:0] mem_1 [10:0]; // RAM content
|
reg [31:0] mem_2 [10:0]; // RAM content
|
reg [31:0] mem_2 [10:0]; // RAM content
|
reg [31:0] mem_3 [10:0]; // RAM content
|
reg [31:0] mem_3 [10:0]; // RAM content
|
reg [31:0] do_reg; // RAM data output register
|
reg [31:0] do_reg; // RAM data output register
|
|
|
//
|
//
|
// Data output drivers
|
// Data output drivers
|
//
|
//
|
assign do = (oe) ? do_reg : {32{1'b0}};
|
assign do = (oe) ? do_reg : {32{1'b0}};
|
|
|
//
|
//
|
// RAM read and write
|
// RAM read and write
|
//
|
//
|
always @(posedge clk)
|
always @(posedge clk)
|
if (ce && !we) begin
|
if (ce && !we) begin
|
do_reg[7:0] <= #1 mem_0[addr];
|
do_reg[7:0] <= #1 mem_0[addr];
|
do_reg[15:8] <= #1 mem_1[addr];
|
do_reg[15:8] <= #1 mem_1[addr];
|
do_reg[23:16] <= #1 mem_2[addr];
|
do_reg[23:16] <= #1 mem_2[addr];
|
do_reg[31:24] <= #1 mem_3[addr];
|
do_reg[31:24] <= #1 mem_3[addr];
|
end
|
end
|
else if (ce && we[0])
|
else if (ce && we[0])
|
mem_0[addr] <= #1 di[7:0];
|
mem_0[addr] <= #1 di[7:0];
|
else if (ce && we[1])
|
else if (ce && we[1])
|
mem_1[addr] <= #1 di[15:8];
|
mem_1[addr] <= #1 di[15:8];
|
else if (ce && we[2])
|
else if (ce && we[2])
|
mem_2[addr] <= #1 di[23:16];
|
mem_2[addr] <= #1 di[23:16];
|
else if (ce && we[3])
|
else if (ce && we[3])
|
mem_3[addr] <= #1 di[31:24];
|
mem_3[addr] <= #1 di[31:24];
|
|
|
`endif // !OR1200_XILINX_RAMB4_S16
|
`endif // !OR1200_XILINX_RAMB4_S16
|
`endif // !OR1200_VIRTUALSILICON_SSP
|
`endif // !OR1200_VIRTUALSILICON_SSP
|
`endif // !OR1200_VIRAGE_SSP
|
`endif // !OR1200_VIRAGE_SSP
|
`endif // !OR1200_AVANT_ATP
|
`endif // !OR1200_AVANT_ATP
|
`endif // !OR1200_ARTISAN_SSP
|
`endif // !OR1200_ARTISAN_SSP
|
|
|
endmodule
|
endmodule
|
|
|