//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200 Top Level ////
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//// OR1200 Top Level ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// OR1200 Top Level ////
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//// OR1200 Top Level ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// - make it smaller and faster ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2002/03/29 15:16:56 lampret
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// Some of the warnings fixed.
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//
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// Revision 1.5 2002/02/11 04:33:17 lampret
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// Revision 1.5 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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//
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// Revision 1.4 2002/02/01 19:56:55 lampret
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// Revision 1.4 2002/02/01 19:56:55 lampret
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// Fixed combinational loops.
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// Fixed combinational loops.
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//
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//
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// Revision 1.3 2002/01/28 01:16:00 lampret
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// Revision 1.3 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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//
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// Revision 1.2 2002/01/18 07:56:00 lampret
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// Revision 1.2 2002/01/18 07:56:00 lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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//
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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//
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// Revision 1.13 2001/11/23 08:38:51 lampret
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// Revision 1.13 2001/11/23 08:38:51 lampret
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// Changed DSR/DRR behavior and exception detection.
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// Changed DSR/DRR behavior and exception detection.
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//
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//
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// Revision 1.12 2001/11/20 00:57:22 lampret
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// Revision 1.12 2001/11/20 00:57:22 lampret
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// Fixed width of du_except.
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// Fixed width of du_except.
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//
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//
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// Revision 1.11 2001/11/18 08:36:28 lampret
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// Revision 1.11 2001/11/18 08:36:28 lampret
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// For GDB changed single stepping and disabled trap exception.
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// For GDB changed single stepping and disabled trap exception.
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//
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//
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// Revision 1.10 2001/10/21 17:57:16 lampret
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// Revision 1.10 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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//
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// Revision 1.9 2001/10/14 13:12:10 lampret
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// Revision 1.9 2001/10/14 13:12:10 lampret
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// MP3 version.
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// MP3 version.
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//
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//
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// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
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// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
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// no message
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// no message
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//
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//
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// Revision 1.4 2001/08/13 03:36:20 lampret
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// Revision 1.4 2001/08/13 03:36:20 lampret
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// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
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// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
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//
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//
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// Revision 1.3 2001/08/09 13:39:33 lampret
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// Revision 1.3 2001/08/09 13:39:33 lampret
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// Major clean-up.
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// Major clean-up.
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//
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//
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// Revision 1.2 2001/07/22 03:31:54 lampret
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// Revision 1.2 2001/07/22 03:31:54 lampret
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// Fixed RAM's oen bug. Cache bypass under development.
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// Fixed RAM's oen bug. Cache bypass under development.
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//
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//
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// Revision 1.1 2001/07/20 00:46:21 lampret
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// Revision 1.1 2001/07/20 00:46:21 lampret
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// Development version of RTL. Libraries are missing.
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// Development version of RTL. Libraries are missing.
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//
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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module or1200_top(
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module or1200_top(
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// System
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// System
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clk_i, rst_i, pic_ints_i, clmode_i,
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clk_i, rst_i, pic_ints_i, clmode_i,
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// Instruction WISHBONE INTERFACE
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// Instruction WISHBONE INTERFACE
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iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,
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iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,
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iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_cab_o, iwb_dat_o,
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iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_cab_o, iwb_dat_o,
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// Data WISHBONE INTERFACE
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// Data WISHBONE INTERFACE
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dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,
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dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,
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dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_cab_o, dwb_dat_o,
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dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_cab_o, dwb_dat_o,
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// External Debug Interface
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// External Debug Interface
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dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
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dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
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dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o,
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dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o,
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// Power Management
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// Power Management
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pm_cpustall_i,
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pm_cpustall_i,
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pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o,
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pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o,
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pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o
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pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o
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);
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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parameter ppic_ints = `OR1200_PIC_INTS;
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parameter ppic_ints = `OR1200_PIC_INTS;
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//
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//
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// I/O
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// I/O
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//
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//
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//
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//
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// System
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// System
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//
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//
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input clk_i;
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input clk_i;
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input rst_i;
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input rst_i;
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input [1:0] clmode_i; // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
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input [1:0] clmode_i; // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
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input [ppic_ints-1:0] pic_ints_i;
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input [ppic_ints-1:0] pic_ints_i;
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//
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//
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// Instruction WISHBONE interface
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// Instruction WISHBONE interface
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//
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//
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input iwb_clk_i; // clock input
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input iwb_clk_i; // clock input
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input iwb_rst_i; // reset input
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input iwb_rst_i; // reset input
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input iwb_ack_i; // normal termination
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input iwb_ack_i; // normal termination
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input iwb_err_i; // termination w/ error
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input iwb_err_i; // termination w/ error
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input iwb_rty_i; // termination w/ retry
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input iwb_rty_i; // termination w/ retry
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input [dw-1:0] iwb_dat_i; // input data bus
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input [dw-1:0] iwb_dat_i; // input data bus
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output iwb_cyc_o; // cycle valid output
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output iwb_cyc_o; // cycle valid output
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output [aw-1:0] iwb_adr_o; // address bus outputs
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output [aw-1:0] iwb_adr_o; // address bus outputs
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output iwb_stb_o; // strobe output
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output iwb_stb_o; // strobe output
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output iwb_we_o; // indicates write transfer
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output iwb_we_o; // indicates write transfer
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output [3:0] iwb_sel_o; // byte select outputs
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output [3:0] iwb_sel_o; // byte select outputs
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output iwb_cab_o; // indicates consecutive address burst
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output iwb_cab_o; // indicates consecutive address burst
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output [dw-1:0] iwb_dat_o; // output data bus
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output [dw-1:0] iwb_dat_o; // output data bus
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//
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//
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// Data WISHBONE interface
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// Data WISHBONE interface
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//
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//
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input dwb_clk_i; // clock input
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input dwb_clk_i; // clock input
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input dwb_rst_i; // reset input
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input dwb_rst_i; // reset input
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input dwb_ack_i; // normal termination
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input dwb_ack_i; // normal termination
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input dwb_err_i; // termination w/ error
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input dwb_err_i; // termination w/ error
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input dwb_rty_i; // termination w/ retry
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input dwb_rty_i; // termination w/ retry
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input [dw-1:0] dwb_dat_i; // input data bus
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input [dw-1:0] dwb_dat_i; // input data bus
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output dwb_cyc_o; // cycle valid output
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output dwb_cyc_o; // cycle valid output
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output [aw-1:0] dwb_adr_o; // address bus outputs
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output [aw-1:0] dwb_adr_o; // address bus outputs
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output dwb_stb_o; // strobe output
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output dwb_stb_o; // strobe output
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output dwb_we_o; // indicates write transfer
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output dwb_we_o; // indicates write transfer
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output [3:0] dwb_sel_o; // byte select outputs
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output [3:0] dwb_sel_o; // byte select outputs
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output dwb_cab_o; // indicates consecutive address burst
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output dwb_cab_o; // indicates consecutive address burst
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output [dw-1:0] dwb_dat_o; // output data bus
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output [dw-1:0] dwb_dat_o; // output data bus
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//
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//
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// External Debug Interface
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// External Debug Interface
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//
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//
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input dbg_stall_i; // External Stall Input
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input dbg_stall_i; // External Stall Input
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input [dw-1:0] dbg_dat_i; // External Data Input
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input [dw-1:0] dbg_dat_i; // External Data Input
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input [aw-1:0] dbg_adr_i; // External Address Input
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input [aw-1:0] dbg_adr_i; // External Address Input
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input [2:0] dbg_op_i; // External Operation Select Input
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input [2:0] dbg_op_i; // External Operation Select Input
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input dbg_ewt_i; // External Watchpoint Trigger Input
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input dbg_ewt_i; // External Watchpoint Trigger Input
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output [3:0] dbg_lss_o; // External Load/Store Unit Status
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output [3:0] dbg_lss_o; // External Load/Store Unit Status
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output [1:0] dbg_is_o; // External Insn Fetch Status
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output [1:0] dbg_is_o; // External Insn Fetch Status
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output [10:0] dbg_wp_o; // Watchpoints Outputs
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output [10:0] dbg_wp_o; // Watchpoints Outputs
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output dbg_bp_o; // Breakpoint Output
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output dbg_bp_o; // Breakpoint Output
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output [dw-1:0] dbg_dat_o; // External Data Output
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output [dw-1:0] dbg_dat_o; // External Data Output
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//
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//
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// Power Management
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// Power Management
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//
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//
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input pm_cpustall_i;
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input pm_cpustall_i;
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output [3:0] pm_clksd_o;
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output [3:0] pm_clksd_o;
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output pm_dc_gate_o;
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output pm_dc_gate_o;
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output pm_ic_gate_o;
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output pm_ic_gate_o;
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output pm_dmmu_gate_o;
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output pm_dmmu_gate_o;
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output pm_immu_gate_o;
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output pm_immu_gate_o;
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output pm_tt_gate_o;
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output pm_tt_gate_o;
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output pm_cpu_gate_o;
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output pm_cpu_gate_o;
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output pm_wakeup_o;
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output pm_wakeup_o;
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output pm_lvolt_o;
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output pm_lvolt_o;
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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//
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//
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// DC to BIU
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// DC to BIU
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//
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//
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wire [dw-1:0] dcbiu_dat_dc;
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wire [dw-1:0] dcbiu_dat_dc;
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wire [aw-1:0] dcbiu_adr_dc;
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wire [aw-1:0] dcbiu_adr_dc;
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wire dcbiu_cyc_dc;
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wire dcbiu_cyc_dc;
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wire dcbiu_stb_dc;
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wire dcbiu_stb_dc;
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wire dcbiu_we_dc;
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wire dcbiu_we_dc;
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wire [3:0] dcbiu_sel_dc;
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wire [3:0] dcbiu_sel_dc;
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wire [3:0] dcbiu_tag_dc;
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wire [3:0] dcbiu_tag_dc;
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wire [dw-1:0] dcbiu_dat_biu;
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wire [dw-1:0] dcbiu_dat_biu;
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wire dcbiu_ack_biu;
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wire dcbiu_ack_biu;
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wire dcbiu_err_biu;
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wire dcbiu_err_biu;
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wire [3:0] dcbiu_tag_biu;
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wire [3:0] dcbiu_tag_biu;
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//
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//
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// IC to BIU
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// IC to BIU
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//
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//
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wire [dw-1:0] icbiu_dat_ic;
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wire [dw-1:0] icbiu_dat_ic;
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wire [aw-1:0] icbiu_adr_ic;
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wire [aw-1:0] icbiu_adr_ic;
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wire icbiu_cyc_ic;
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wire icbiu_cyc_ic;
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wire icbiu_stb_ic;
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wire icbiu_stb_ic;
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wire icbiu_we_ic;
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wire icbiu_we_ic;
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wire [3:0] icbiu_sel_ic;
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wire [3:0] icbiu_sel_ic;
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wire [3:0] icbiu_tag_ic;
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wire [3:0] icbiu_tag_ic;
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wire [dw-1:0] icbiu_dat_biu;
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wire [dw-1:0] icbiu_dat_biu;
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wire icbiu_ack_biu;
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wire icbiu_ack_biu;
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wire icbiu_err_biu;
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wire icbiu_err_biu;
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wire [3:0] icbiu_tag_biu;
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wire [3:0] icbiu_tag_biu;
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//
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//
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// CPU's SPR access to various RISC units (shared wires)
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// CPU's SPR access to various RISC units (shared wires)
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//
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//
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wire supv;
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wire supv;
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wire [aw-1:0] spr_addr;
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wire [aw-1:0] spr_addr;
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wire [dw-1:0] spr_dat_cpu;
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wire [dw-1:0] spr_dat_cpu;
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wire [31:0] spr_cs;
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wire [31:0] spr_cs;
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wire spr_we;
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wire spr_we;
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//
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//
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// DMMU and CPU
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// DMMU and CPU
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//
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//
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wire dmmu_en;
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wire dmmu_en;
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wire [31:0] spr_dat_dmmu;
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wire [31:0] spr_dat_dmmu;
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//
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//
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// DMMU and DC
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// DMMU and DC
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//
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//
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wire dcdmmu_err_dc;
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wire dcdmmu_err_dc;
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wire [3:0] dcdmmu_tag_dc;
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wire [3:0] dcdmmu_tag_dc;
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wire [aw-1:0] dcdmmu_adr_dmmu;
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wire [aw-1:0] dcdmmu_adr_dmmu;
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wire dcdmmu_cycstb_dmmu;
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wire dcdmmu_cycstb_dmmu;
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wire dcdmmu_ci_dmmu;
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wire dcdmmu_ci_dmmu;
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//
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//
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// CPU and data memory subsystem
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// CPU and data memory subsystem
|
//
|
//
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wire dc_en;
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wire dc_en;
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wire [31:0] dcpu_adr_cpu;
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wire [31:0] dcpu_adr_cpu;
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wire dcpu_we_cpu;
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wire dcpu_we_cpu;
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wire [3:0] dcpu_sel_cpu;
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wire [3:0] dcpu_sel_cpu;
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wire [3:0] dcpu_tag_cpu;
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wire [3:0] dcpu_tag_cpu;
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wire [31:0] dcpu_dat_cpu;
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wire [31:0] dcpu_dat_cpu;
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wire [31:0] dcpu_dat_dc;
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wire [31:0] dcpu_dat_dc;
|
wire dcpu_ack_dc;
|
wire dcpu_ack_dc;
|
wire dcpu_rty_dc;
|
wire dcpu_rty_dc;
|
wire dcpu_err_dmmu;
|
wire dcpu_err_dmmu;
|
wire [3:0] dcpu_tag_dmmu;
|
wire [3:0] dcpu_tag_dmmu;
|
|
|
//
|
//
|
// IMMU and CPU
|
// IMMU and CPU
|
//
|
//
|
wire immu_en;
|
wire immu_en;
|
wire [31:0] spr_dat_immu;
|
wire [31:0] spr_dat_immu;
|
|
|
//
|
//
|
// CPU and insn memory subsystem
|
// CPU and insn memory subsystem
|
//
|
//
|
wire ic_en;
|
wire ic_en;
|
wire [31:0] icpu_adr_cpu;
|
wire [31:0] icpu_adr_cpu;
|
wire icpu_cycstb_cpu;
|
wire icpu_cycstb_cpu;
|
wire [3:0] icpu_sel_cpu;
|
wire [3:0] icpu_sel_cpu;
|
wire [3:0] icpu_tag_cpu;
|
wire [3:0] icpu_tag_cpu;
|
wire [31:0] icpu_dat_ic;
|
wire [31:0] icpu_dat_ic;
|
wire icpu_ack_ic;
|
wire icpu_ack_ic;
|
wire [31:0] icpu_adr_immu;
|
wire [31:0] icpu_adr_immu;
|
wire icpu_err_immu;
|
wire icpu_err_immu;
|
wire [3:0] icpu_tag_immu;
|
wire [3:0] icpu_tag_immu;
|
|
|
//
|
//
|
// IMMU and IC
|
// IMMU and IC
|
//
|
//
|
wire [aw-1:0] icimmu_adr_immu;
|
wire [aw-1:0] icimmu_adr_immu;
|
wire icimmu_rty_ic;
|
wire icimmu_rty_ic;
|
wire icimmu_err_ic;
|
wire icimmu_err_ic;
|
wire [3:0] icimmu_tag_ic;
|
wire [3:0] icimmu_tag_ic;
|
wire icimmu_cycstb_immu;
|
wire icimmu_cycstb_immu;
|
wire icimmu_ci_immu;
|
wire icimmu_ci_immu;
|
|
|
//
|
//
|
// Connection between CPU and PIC
|
// Connection between CPU and PIC
|
//
|
//
|
wire [dw-1:0] spr_dat_pic;
|
wire [dw-1:0] spr_dat_pic;
|
wire pic_wakeup;
|
wire pic_wakeup;
|
wire sig_int;
|
wire sig_int;
|
|
|
//
|
//
|
// Connection between CPU and PM
|
// Connection between CPU and PM
|
//
|
//
|
wire [dw-1:0] spr_dat_pm;
|
wire [dw-1:0] spr_dat_pm;
|
|
|
//
|
//
|
// CPU and TT
|
// CPU and TT
|
//
|
//
|
wire [dw-1:0] spr_dat_tt;
|
wire [dw-1:0] spr_dat_tt;
|
wire sig_tick;
|
wire sig_tick;
|
|
|
//
|
//
|
// Debug port and caches/MMUs
|
// Debug port and caches/MMUs
|
//
|
//
|
wire [dw-1:0] spr_dat_du;
|
wire [dw-1:0] spr_dat_du;
|
wire du_stall;
|
wire du_stall;
|
wire [dw-1:0] du_addr;
|
wire [dw-1:0] du_addr;
|
wire [dw-1:0] du_dat_du;
|
wire [dw-1:0] du_dat_du;
|
wire du_read;
|
wire du_read;
|
wire du_write;
|
wire du_write;
|
wire [12:0] du_except;
|
wire [12:0] du_except;
|
wire [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
|
wire [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
|
wire [dw-1:0] du_dat_cpu;
|
wire [dw-1:0] du_dat_cpu;
|
|
|
wire ex_freeze;
|
wire ex_freeze;
|
wire [31:0] ex_insn;
|
wire [31:0] ex_insn;
|
wire [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
|
wire [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
|
|
wire [31:0] spr_dat_npc;
|
|
wire [31:0] rf_dataw;
|
|
|
|
|
//
|
//
|
// Instantiation of Instruction WISHBONE BIU
|
// Instantiation of Instruction WISHBONE BIU
|
//
|
//
|
or1200_wb_biu iwb_biu(
|
or1200_wb_biu iwb_biu(
|
// RISC clk, rst and clock control
|
// RISC clk, rst and clock control
|
.clk(clk_i),
|
.clk(clk_i),
|
.rst(rst_i),
|
.rst(rst_i),
|
.clmode(clmode_i),
|
.clmode(clmode_i),
|
|
|
// WISHBONE interface
|
// WISHBONE interface
|
.wb_clk_i(iwb_clk_i),
|
.wb_clk_i(iwb_clk_i),
|
.wb_rst_i(iwb_rst_i),
|
.wb_rst_i(iwb_rst_i),
|
.wb_ack_i(iwb_ack_i),
|
.wb_ack_i(iwb_ack_i),
|
.wb_err_i(iwb_err_i),
|
.wb_err_i(iwb_err_i),
|
.wb_rty_i(iwb_rty_i),
|
.wb_rty_i(iwb_rty_i),
|
.wb_dat_i(iwb_dat_i),
|
.wb_dat_i(iwb_dat_i),
|
.wb_cyc_o(iwb_cyc_o),
|
.wb_cyc_o(iwb_cyc_o),
|
.wb_adr_o(iwb_adr_o),
|
.wb_adr_o(iwb_adr_o),
|
.wb_stb_o(iwb_stb_o),
|
.wb_stb_o(iwb_stb_o),
|
.wb_we_o(iwb_we_o),
|
.wb_we_o(iwb_we_o),
|
.wb_sel_o(iwb_sel_o),
|
.wb_sel_o(iwb_sel_o),
|
.wb_cab_o(iwb_cab_o),
|
.wb_cab_o(iwb_cab_o),
|
.wb_dat_o(iwb_dat_o),
|
.wb_dat_o(iwb_dat_o),
|
|
|
// Internal RISC bus
|
// Internal RISC bus
|
.biu_dat_i(icbiu_dat_ic),
|
.biu_dat_i(icbiu_dat_ic),
|
.biu_adr_i(icbiu_adr_ic),
|
.biu_adr_i(icbiu_adr_ic),
|
.biu_cyc_i(icbiu_cyc_ic),
|
.biu_cyc_i(icbiu_cyc_ic),
|
.biu_stb_i(icbiu_stb_ic),
|
.biu_stb_i(icbiu_stb_ic),
|
.biu_we_i(icbiu_we_ic),
|
.biu_we_i(icbiu_we_ic),
|
.biu_sel_i(icbiu_sel_ic),
|
.biu_sel_i(icbiu_sel_ic),
|
.biu_cab_i(icbiu_cab_ic),
|
.biu_cab_i(icbiu_cab_ic),
|
.biu_dat_o(icbiu_dat_biu),
|
.biu_dat_o(icbiu_dat_biu),
|
.biu_ack_o(icbiu_ack_biu),
|
.biu_ack_o(icbiu_ack_biu),
|
.biu_err_o(icbiu_err_biu)
|
.biu_err_o(icbiu_err_biu)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of Data WISHBONE BIU
|
// Instantiation of Data WISHBONE BIU
|
//
|
//
|
or1200_wb_biu dwb_biu(
|
or1200_wb_biu dwb_biu(
|
// RISC clk, rst and clock control
|
// RISC clk, rst and clock control
|
.clk(clk_i),
|
.clk(clk_i),
|
.rst(rst_i),
|
.rst(rst_i),
|
.clmode(clmode_i),
|
.clmode(clmode_i),
|
|
|
// WISHBONE interface
|
// WISHBONE interface
|
.wb_clk_i(dwb_clk_i),
|
.wb_clk_i(dwb_clk_i),
|
.wb_rst_i(dwb_rst_i),
|
.wb_rst_i(dwb_rst_i),
|
.wb_ack_i(dwb_ack_i),
|
.wb_ack_i(dwb_ack_i),
|
.wb_err_i(dwb_err_i),
|
.wb_err_i(dwb_err_i),
|
.wb_rty_i(dwb_rty_i),
|
.wb_rty_i(dwb_rty_i),
|
.wb_dat_i(dwb_dat_i),
|
.wb_dat_i(dwb_dat_i),
|
.wb_cyc_o(dwb_cyc_o),
|
.wb_cyc_o(dwb_cyc_o),
|
.wb_adr_o(dwb_adr_o),
|
.wb_adr_o(dwb_adr_o),
|
.wb_stb_o(dwb_stb_o),
|
.wb_stb_o(dwb_stb_o),
|
.wb_we_o(dwb_we_o),
|
.wb_we_o(dwb_we_o),
|
.wb_sel_o(dwb_sel_o),
|
.wb_sel_o(dwb_sel_o),
|
.wb_cab_o(dwb_cab_o),
|
.wb_cab_o(dwb_cab_o),
|
.wb_dat_o(dwb_dat_o),
|
.wb_dat_o(dwb_dat_o),
|
|
|
// Internal RISC bus
|
// Internal RISC bus
|
.biu_dat_i(dcbiu_dat_dc),
|
.biu_dat_i(dcbiu_dat_dc),
|
.biu_adr_i(dcbiu_adr_dc),
|
.biu_adr_i(dcbiu_adr_dc),
|
.biu_cyc_i(dcbiu_cyc_dc),
|
.biu_cyc_i(dcbiu_cyc_dc),
|
.biu_stb_i(dcbiu_stb_dc),
|
.biu_stb_i(dcbiu_stb_dc),
|
.biu_we_i(dcbiu_we_dc),
|
.biu_we_i(dcbiu_we_dc),
|
.biu_sel_i(dcbiu_sel_dc),
|
.biu_sel_i(dcbiu_sel_dc),
|
.biu_cab_i(dcbiu_cab_dc),
|
.biu_cab_i(dcbiu_cab_dc),
|
.biu_dat_o(dcbiu_dat_biu),
|
.biu_dat_o(dcbiu_dat_biu),
|
.biu_ack_o(dcbiu_ack_biu),
|
.biu_ack_o(dcbiu_ack_biu),
|
.biu_err_o(dcbiu_err_biu)
|
.biu_err_o(dcbiu_err_biu)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of IMMU
|
// Instantiation of IMMU
|
//
|
//
|
or1200_immu_top or1200_immu_top(
|
or1200_immu_top or1200_immu_top(
|
// Rst and clk
|
// Rst and clk
|
.clk(clk_i),
|
.clk(clk_i),
|
.rst(rst_i),
|
.rst(rst_i),
|
|
|
// CPU i/f
|
// CPU i/f
|
.ic_en(ic_en),
|
.ic_en(ic_en),
|
.immu_en(immu_en),
|
.immu_en(immu_en),
|
.supv(supv),
|
.supv(supv),
|
.icpu_adr_i(icpu_adr_cpu),
|
.icpu_adr_i(icpu_adr_cpu),
|
.icpu_cycstb_i(icpu_cycstb_cpu),
|
.icpu_cycstb_i(icpu_cycstb_cpu),
|
.icpu_adr_o(icpu_adr_immu),
|
.icpu_adr_o(icpu_adr_immu),
|
.icpu_tag_o(icpu_tag_immu),
|
.icpu_tag_o(icpu_tag_immu),
|
.icpu_rty_o(icpu_rty_immu),
|
.icpu_rty_o(icpu_rty_immu),
|
.icpu_err_o(icpu_err_immu),
|
.icpu_err_o(icpu_err_immu),
|
|
|
// SPR access
|
// SPR access
|
.spr_cs(spr_cs[`OR1200_SPR_GROUP_IMMU]),
|
.spr_cs(spr_cs[`OR1200_SPR_GROUP_IMMU]),
|
.spr_write(spr_we),
|
.spr_write(spr_we),
|
.spr_addr(spr_addr),
|
.spr_addr(spr_addr),
|
.spr_dat_i(spr_dat_cpu),
|
.spr_dat_i(spr_dat_cpu),
|
.spr_dat_o(spr_dat_immu),
|
.spr_dat_o(spr_dat_immu),
|
|
|
// IC i/f
|
// IC i/f
|
.icimmu_rty_i(icimmu_rty_ic),
|
.icimmu_rty_i(icimmu_rty_ic),
|
.icimmu_err_i(icimmu_err_ic),
|
.icimmu_err_i(icimmu_err_ic),
|
.icimmu_tag_i(icimmu_tag_ic),
|
.icimmu_tag_i(icimmu_tag_ic),
|
.icimmu_adr_o(icimmu_adr_immu),
|
.icimmu_adr_o(icimmu_adr_immu),
|
.icimmu_cycstb_o(icimmu_cycstb_immu),
|
.icimmu_cycstb_o(icimmu_cycstb_immu),
|
.icimmu_ci_o(icimmu_ci_immu)
|
.icimmu_ci_o(icimmu_ci_immu)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of Instruction Cache
|
// Instantiation of Instruction Cache
|
//
|
//
|
or1200_ic_top or1200_ic_top(
|
or1200_ic_top or1200_ic_top(
|
.clk(clk_i),
|
.clk(clk_i),
|
.rst(rst_i),
|
.rst(rst_i),
|
|
|
// IC and CPU/IMMU
|
// IC and CPU/IMMU
|
.ic_en(ic_en),
|
.ic_en(ic_en),
|
.icimmu_adr_i(icimmu_adr_immu),
|
.icimmu_adr_i(icimmu_adr_immu),
|
.icimmu_cycstb_i(icimmu_cycstb_immu),
|
.icimmu_cycstb_i(icimmu_cycstb_immu),
|
.icimmu_ci_i(icimmu_ci_immu),
|
.icimmu_ci_i(icimmu_ci_immu),
|
.icpu_sel_i(icpu_sel_cpu),
|
.icpu_sel_i(icpu_sel_cpu),
|
.icpu_tag_i(icpu_tag_cpu),
|
.icpu_tag_i(icpu_tag_cpu),
|
.icpu_dat_o(icpu_dat_ic),
|
.icpu_dat_o(icpu_dat_ic),
|
.icpu_ack_o(icpu_ack_ic),
|
.icpu_ack_o(icpu_ack_ic),
|
.icimmu_rty_o(icimmu_rty_ic),
|
.icimmu_rty_o(icimmu_rty_ic),
|
.icimmu_err_o(icimmu_err_ic),
|
.icimmu_err_o(icimmu_err_ic),
|
.icimmu_tag_o(icimmu_tag_ic),
|
.icimmu_tag_o(icimmu_tag_ic),
|
|
|
// SPR access
|
// SPR access
|
.spr_cs(spr_cs[`OR1200_SPR_GROUP_IC]),
|
.spr_cs(spr_cs[`OR1200_SPR_GROUP_IC]),
|
.spr_write(spr_we),
|
.spr_write(spr_we),
|
.spr_dat_i(spr_dat_cpu),
|
.spr_dat_i(spr_dat_cpu),
|
|
|
// IC and BIU
|
// IC and BIU
|
.icbiu_dat_o(icbiu_dat_ic),
|
.icbiu_dat_o(icbiu_dat_ic),
|
.icbiu_adr_o(icbiu_adr_ic),
|
.icbiu_adr_o(icbiu_adr_ic),
|
.icbiu_cyc_o(icbiu_cyc_ic),
|
.icbiu_cyc_o(icbiu_cyc_ic),
|
.icbiu_stb_o(icbiu_stb_ic),
|
.icbiu_stb_o(icbiu_stb_ic),
|
.icbiu_we_o(icbiu_we_ic),
|
.icbiu_we_o(icbiu_we_ic),
|
.icbiu_sel_o(icbiu_sel_ic),
|
.icbiu_sel_o(icbiu_sel_ic),
|
.icbiu_cab_o(icbiu_cab_ic),
|
.icbiu_cab_o(icbiu_cab_ic),
|
.icbiu_dat_i(icbiu_dat_biu),
|
.icbiu_dat_i(icbiu_dat_biu),
|
.icbiu_ack_i(icbiu_ack_biu),
|
.icbiu_ack_i(icbiu_ack_biu),
|
.icbiu_err_i(icbiu_err_biu)
|
.icbiu_err_i(icbiu_err_biu)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of Instruction Cache
|
// Instantiation of Instruction Cache
|
//
|
//
|
or1200_cpu or1200_cpu(
|
or1200_cpu or1200_cpu(
|
.clk(clk_i),
|
.clk(clk_i),
|
.rst(rst_i),
|
.rst(rst_i),
|
|
|
// Connection IC and IFETCHER inside CPU
|
// Connection IC and IFETCHER inside CPU
|
.ic_en(ic_en),
|
.ic_en(ic_en),
|
.icpu_adr_o(icpu_adr_cpu),
|
.icpu_adr_o(icpu_adr_cpu),
|
.icpu_cycstb_o(icpu_cycstb_cpu),
|
.icpu_cycstb_o(icpu_cycstb_cpu),
|
.icpu_sel_o(icpu_sel_cpu),
|
.icpu_sel_o(icpu_sel_cpu),
|
.icpu_tag_o(icpu_tag_cpu),
|
.icpu_tag_o(icpu_tag_cpu),
|
.icpu_dat_i(icpu_dat_ic),
|
.icpu_dat_i(icpu_dat_ic),
|
.icpu_ack_i(icpu_ack_ic),
|
.icpu_ack_i(icpu_ack_ic),
|
.icpu_rty_i(icpu_rty_immu),
|
.icpu_rty_i(icpu_rty_immu),
|
.icpu_adr_i(icpu_adr_immu),
|
.icpu_adr_i(icpu_adr_immu),
|
.icpu_err_i(icpu_err_immu),
|
.icpu_err_i(icpu_err_immu),
|
.icpu_tag_i(icpu_tag_immu),
|
.icpu_tag_i(icpu_tag_immu),
|
|
|
// Connection CPU to external Debug port
|
// Connection CPU to external Debug port
|
.ex_freeze(ex_freeze),
|
.ex_freeze(ex_freeze),
|
.ex_insn(ex_insn),
|
.ex_insn(ex_insn),
|
.branch_op(branch_op),
|
.branch_op(branch_op),
|
.du_stall(du_stall),
|
.du_stall(du_stall),
|
.du_addr(du_addr),
|
.du_addr(du_addr),
|
.du_dat_du(du_dat_du),
|
.du_dat_du(du_dat_du),
|
.du_read(du_read),
|
.du_read(du_read),
|
.du_write(du_write),
|
.du_write(du_write),
|
.du_dsr(du_dsr),
|
.du_dsr(du_dsr),
|
.du_except(du_except),
|
.du_except(du_except),
|
.du_dat_cpu(du_dat_cpu),
|
.du_dat_cpu(du_dat_cpu),
|
|
.rf_dataw(rf_dataw),
|
|
|
|
|
// Connection IMMU and CPU internally
|
// Connection IMMU and CPU internally
|
.immu_en(immu_en),
|
.immu_en(immu_en),
|
|
|
// Connection DC and CPU
|
// Connection DC and CPU
|
.dc_en(dc_en),
|
.dc_en(dc_en),
|
.dcpu_adr_o(dcpu_adr_cpu),
|
.dcpu_adr_o(dcpu_adr_cpu),
|
.dcpu_cycstb_o(dcpu_cycstb_cpu),
|
.dcpu_cycstb_o(dcpu_cycstb_cpu),
|
.dcpu_we_o(dcpu_we_cpu),
|
.dcpu_we_o(dcpu_we_cpu),
|
.dcpu_sel_o(dcpu_sel_cpu),
|
.dcpu_sel_o(dcpu_sel_cpu),
|
.dcpu_tag_o(dcpu_tag_cpu),
|
.dcpu_tag_o(dcpu_tag_cpu),
|
.dcpu_dat_o(dcpu_dat_cpu),
|
.dcpu_dat_o(dcpu_dat_cpu),
|
.dcpu_dat_i(dcpu_dat_dc),
|
.dcpu_dat_i(dcpu_dat_dc),
|
.dcpu_ack_i(dcpu_ack_dc),
|
.dcpu_ack_i(dcpu_ack_dc),
|
.dcpu_rty_i(dcpu_rty_dc),
|
.dcpu_rty_i(dcpu_rty_dc),
|
.dcpu_err_i(dcpu_err_dmmu),
|
.dcpu_err_i(dcpu_err_dmmu),
|
.dcpu_tag_i(dcpu_tag_dmmu),
|
.dcpu_tag_i(dcpu_tag_dmmu),
|
|
|
// Connection DMMU and CPU internally
|
// Connection DMMU and CPU internally
|
.dmmu_en(dmmu_en),
|
.dmmu_en(dmmu_en),
|
|
|
// Connection PIC and CPU's EXCEPT
|
// Connection PIC and CPU's EXCEPT
|
.sig_int(sig_int),
|
.sig_int(sig_int),
|
.sig_tick(sig_tick),
|
.sig_tick(sig_tick),
|
|
|
// SPRs
|
// SPRs
|
.supv(supv),
|
.supv(supv),
|
.spr_addr(spr_addr),
|
.spr_addr(spr_addr),
|
.spr_dat_cpu(spr_dat_cpu),
|
.spr_dat_cpu(spr_dat_cpu),
|
.spr_dat_pic(spr_dat_pic),
|
.spr_dat_pic(spr_dat_pic),
|
.spr_dat_tt(spr_dat_tt),
|
.spr_dat_tt(spr_dat_tt),
|
.spr_dat_pm(spr_dat_pm),
|
.spr_dat_pm(spr_dat_pm),
|
.spr_dat_dmmu(spr_dat_dmmu),
|
.spr_dat_dmmu(spr_dat_dmmu),
|
.spr_dat_immu(spr_dat_immu),
|
.spr_dat_immu(spr_dat_immu),
|
.spr_dat_du(spr_dat_du),
|
.spr_dat_du(spr_dat_du),
|
|
.spr_dat_npc(spr_dat_npc),
|
.spr_cs(spr_cs),
|
.spr_cs(spr_cs),
|
.spr_we(spr_we)
|
.spr_we(spr_we)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of DMMU
|
// Instantiation of DMMU
|
//
|
//
|
or1200_dmmu_top or1200_dmmu_top(
|
or1200_dmmu_top or1200_dmmu_top(
|
// Rst and clk
|
// Rst and clk
|
.clk(clk_i),
|
.clk(clk_i),
|
.rst(rst_i),
|
.rst(rst_i),
|
|
|
// CPU i/f
|
// CPU i/f
|
.dc_en(dc_en),
|
.dc_en(dc_en),
|
.dmmu_en(dmmu_en),
|
.dmmu_en(dmmu_en),
|
.supv(supv),
|
.supv(supv),
|
.dcpu_adr_i(dcpu_adr_cpu),
|
.dcpu_adr_i(dcpu_adr_cpu),
|
.dcpu_cycstb_i(dcpu_cycstb_cpu),
|
.dcpu_cycstb_i(dcpu_cycstb_cpu),
|
.dcpu_we_i(dcpu_we_cpu),
|
.dcpu_we_i(dcpu_we_cpu),
|
.dcpu_tag_o(dcpu_tag_dmmu),
|
.dcpu_tag_o(dcpu_tag_dmmu),
|
.dcpu_err_o(dcpu_err_dmmu),
|
.dcpu_err_o(dcpu_err_dmmu),
|
|
|
// SPR access
|
// SPR access
|
.spr_cs(spr_cs[`OR1200_SPR_GROUP_DMMU]),
|
.spr_cs(spr_cs[`OR1200_SPR_GROUP_DMMU]),
|
.spr_write(spr_we),
|
.spr_write(spr_we),
|
.spr_addr(spr_addr),
|
.spr_addr(spr_addr),
|
.spr_dat_i(spr_dat_cpu),
|
.spr_dat_i(spr_dat_cpu),
|
.spr_dat_o(spr_dat_dmmu),
|
.spr_dat_o(spr_dat_dmmu),
|
|
|
// DC i/f
|
// DC i/f
|
.dcdmmu_err_i(dcdmmu_err_dc),
|
.dcdmmu_err_i(dcdmmu_err_dc),
|
.dcdmmu_tag_i(dcdmmu_tag_dc),
|
.dcdmmu_tag_i(dcdmmu_tag_dc),
|
.dcdmmu_adr_o(dcdmmu_adr_dmmu),
|
.dcdmmu_adr_o(dcdmmu_adr_dmmu),
|
.dcdmmu_cycstb_o(dcdmmu_cycstb_dmmu),
|
.dcdmmu_cycstb_o(dcdmmu_cycstb_dmmu),
|
.dcdmmu_ci_o(dcdmmu_ci_dmmu)
|
.dcdmmu_ci_o(dcdmmu_ci_dmmu)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of Data Cache
|
// Instantiation of Data Cache
|
//
|
//
|
or1200_dc_top or1200_dc_top(
|
or1200_dc_top or1200_dc_top(
|
.clk(clk_i),
|
.clk(clk_i),
|
.rst(rst_i),
|
.rst(rst_i),
|
|
|
// DC and CPU/DMMU
|
// DC and CPU/DMMU
|
.dc_en(dc_en),
|
.dc_en(dc_en),
|
.dcdmmu_adr_i(dcdmmu_adr_dmmu),
|
.dcdmmu_adr_i(dcdmmu_adr_dmmu),
|
.dcdmmu_cycstb_i(dcdmmu_cycstb_dmmu),
|
.dcdmmu_cycstb_i(dcdmmu_cycstb_dmmu),
|
.dcdmmu_ci_i(dcdmmu_ci_dmmu),
|
.dcdmmu_ci_i(dcdmmu_ci_dmmu),
|
.dcpu_we_i(dcpu_we_cpu),
|
.dcpu_we_i(dcpu_we_cpu),
|
.dcpu_sel_i(dcpu_sel_cpu),
|
.dcpu_sel_i(dcpu_sel_cpu),
|
.dcpu_tag_i(dcpu_tag_cpu),
|
.dcpu_tag_i(dcpu_tag_cpu),
|
.dcpu_dat_i(dcpu_dat_cpu),
|
.dcpu_dat_i(dcpu_dat_cpu),
|
.dcpu_dat_o(dcpu_dat_dc),
|
.dcpu_dat_o(dcpu_dat_dc),
|
.dcpu_ack_o(dcpu_ack_dc),
|
.dcpu_ack_o(dcpu_ack_dc),
|
.dcpu_rty_o(dcpu_rty_dc),
|
.dcpu_rty_o(dcpu_rty_dc),
|
.dcdmmu_err_o(dcdmmu_err_dc),
|
.dcdmmu_err_o(dcdmmu_err_dc),
|
.dcdmmu_tag_o(dcdmmu_tag_dc),
|
.dcdmmu_tag_o(dcdmmu_tag_dc),
|
|
|
// SPR access
|
// SPR access
|
.spr_cs(spr_cs[`OR1200_SPR_GROUP_DC]),
|
.spr_cs(spr_cs[`OR1200_SPR_GROUP_DC]),
|
.spr_write(spr_we),
|
.spr_write(spr_we),
|
.spr_dat_i(spr_dat_cpu),
|
.spr_dat_i(spr_dat_cpu),
|
|
|
// DC and BIU
|
// DC and BIU
|
.dcbiu_dat_o(dcbiu_dat_dc),
|
.dcbiu_dat_o(dcbiu_dat_dc),
|
.dcbiu_adr_o(dcbiu_adr_dc),
|
.dcbiu_adr_o(dcbiu_adr_dc),
|
.dcbiu_cyc_o(dcbiu_cyc_dc),
|
.dcbiu_cyc_o(dcbiu_cyc_dc),
|
.dcbiu_stb_o(dcbiu_stb_dc),
|
.dcbiu_stb_o(dcbiu_stb_dc),
|
.dcbiu_we_o(dcbiu_we_dc),
|
.dcbiu_we_o(dcbiu_we_dc),
|
.dcbiu_sel_o(dcbiu_sel_dc),
|
.dcbiu_sel_o(dcbiu_sel_dc),
|
.dcbiu_cab_o(dcbiu_cab_dc),
|
.dcbiu_cab_o(dcbiu_cab_dc),
|
.dcbiu_dat_i(dcbiu_dat_biu),
|
.dcbiu_dat_i(dcbiu_dat_biu),
|
.dcbiu_ack_i(dcbiu_ack_biu),
|
.dcbiu_ack_i(dcbiu_ack_biu),
|
.dcbiu_err_i(dcbiu_err_biu)
|
.dcbiu_err_i(dcbiu_err_biu)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of Debug Unit
|
// Instantiation of Debug Unit
|
//
|
//
|
or1200_du or1200_du(
|
or1200_du or1200_du(
|
// RISC Internal Interface
|
// RISC Internal Interface
|
.clk(clk_i),
|
.clk(clk_i),
|
.rst(rst_i),
|
.rst(rst_i),
|
.dcpu_cycstb_i(dcpu_cycstb_cpu),
|
.dcpu_cycstb_i(dcpu_cycstb_cpu),
|
.dcpu_we_i(dcpu_we_cpu),
|
.dcpu_we_i(dcpu_we_cpu),
|
.icpu_cycstb_i(icpu_cycstb_cpu),
|
.icpu_cycstb_i(icpu_cycstb_cpu),
|
.ex_freeze(ex_freeze),
|
.ex_freeze(ex_freeze),
|
.branch_op(branch_op),
|
.branch_op(branch_op),
|
.ex_insn(ex_insn),
|
.ex_insn(ex_insn),
|
.du_dsr(du_dsr),
|
.du_dsr(du_dsr),
|
|
|
|
// For Trace buffer
|
|
.spr_dat_npc(spr_dat_npc),
|
|
.rf_dataw(rf_dataw),
|
|
|
// DU's access to SPR unit
|
// DU's access to SPR unit
|
.du_stall(du_stall),
|
.du_stall(du_stall),
|
.du_addr(du_addr),
|
.du_addr(du_addr),
|
.du_dat_i(du_dat_cpu),
|
.du_dat_i(du_dat_cpu),
|
.du_dat_o(du_dat_du),
|
.du_dat_o(du_dat_du),
|
.du_read(du_read),
|
.du_read(du_read),
|
.du_write(du_write),
|
.du_write(du_write),
|
.du_except(du_except),
|
.du_except(du_except),
|
|
|
// Access to DU's SPRs
|
// Access to DU's SPRs
|
.spr_cs(spr_cs[`OR1200_SPR_GROUP_DU]),
|
.spr_cs(spr_cs[`OR1200_SPR_GROUP_DU]),
|
.spr_write(spr_we),
|
.spr_write(spr_we),
|
.spr_addr(spr_addr),
|
.spr_addr(spr_addr),
|
.spr_dat_i(spr_dat_cpu),
|
.spr_dat_i(spr_dat_cpu),
|
.spr_dat_o(spr_dat_du),
|
.spr_dat_o(spr_dat_du),
|
|
|
// External Debug Interface
|
// External Debug Interface
|
.dbg_stall_i(dbg_stall_i),
|
.dbg_stall_i(dbg_stall_i),
|
.dbg_dat_i(dbg_dat_i),
|
.dbg_dat_i(dbg_dat_i),
|
.dbg_adr_i(dbg_adr_i),
|
.dbg_adr_i(dbg_adr_i),
|
.dbg_op_i(dbg_op_i),
|
.dbg_op_i(dbg_op_i),
|
.dbg_ewt_i(dbg_ewt_i),
|
.dbg_ewt_i(dbg_ewt_i),
|
.dbg_lss_o(dbg_lss_o),
|
.dbg_lss_o(dbg_lss_o),
|
.dbg_is_o(dbg_is_o),
|
.dbg_is_o(dbg_is_o),
|
.dbg_wp_o(dbg_wp_o),
|
.dbg_wp_o(dbg_wp_o),
|
.dbg_bp_o(dbg_bp_o),
|
.dbg_bp_o(dbg_bp_o),
|
.dbg_dat_o(dbg_dat_o)
|
.dbg_dat_o(dbg_dat_o)
|
);
|
);
|
|
|
//
|
//
|
// Programmable interrupt controller
|
// Programmable interrupt controller
|
//
|
//
|
or1200_pic or1200_pic(
|
or1200_pic or1200_pic(
|
// RISC Internal Interface
|
// RISC Internal Interface
|
.clk(clk_i),
|
.clk(clk_i),
|
.rst(rst_i),
|
.rst(rst_i),
|
.spr_cs(spr_cs[`OR1200_SPR_GROUP_PIC]),
|
.spr_cs(spr_cs[`OR1200_SPR_GROUP_PIC]),
|
.spr_write(spr_we),
|
.spr_write(spr_we),
|
.spr_addr(spr_addr),
|
.spr_addr(spr_addr),
|
.spr_dat_i(spr_dat_cpu),
|
.spr_dat_i(spr_dat_cpu),
|
.spr_dat_o(spr_dat_pic),
|
.spr_dat_o(spr_dat_pic),
|
.pic_wakeup(pic_wakeup),
|
.pic_wakeup(pic_wakeup),
|
.int(sig_int),
|
.int(sig_int),
|
|
|
// PIC Interface
|
// PIC Interface
|
.pic_int(pic_ints_i)
|
.pic_int(pic_ints_i)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of Tick timer
|
// Instantiation of Tick timer
|
//
|
//
|
or1200_tt or1200_tt(
|
or1200_tt or1200_tt(
|
// RISC Internal Interface
|
// RISC Internal Interface
|
.clk(clk_i),
|
.clk(clk_i),
|
.rst(rst_i),
|
.rst(rst_i),
|
.du_stall(du_stall),
|
.du_stall(du_stall),
|
.spr_cs(spr_cs[`OR1200_SPR_GROUP_TT]),
|
.spr_cs(spr_cs[`OR1200_SPR_GROUP_TT]),
|
.spr_write(spr_we),
|
.spr_write(spr_we),
|
.spr_addr(spr_addr),
|
.spr_addr(spr_addr),
|
.spr_dat_i(spr_dat_cpu),
|
.spr_dat_i(spr_dat_cpu),
|
.spr_dat_o(spr_dat_tt),
|
.spr_dat_o(spr_dat_tt),
|
.int(sig_tick)
|
.int(sig_tick)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of Power Management
|
// Instantiation of Power Management
|
//
|
//
|
or1200_pm or1200_pm(
|
or1200_pm or1200_pm(
|
// RISC Internal Interface
|
// RISC Internal Interface
|
.clk(clk_i),
|
.clk(clk_i),
|
.rst(rst_i),
|
.rst(rst_i),
|
.pic_wakeup(pic_wakeup),
|
.pic_wakeup(pic_wakeup),
|
.spr_write(spr_we),
|
.spr_write(spr_we),
|
.spr_addr(spr_addr),
|
.spr_addr(spr_addr),
|
.spr_dat_i(spr_dat_cpu),
|
.spr_dat_i(spr_dat_cpu),
|
.spr_dat_o(spr_dat_pm),
|
.spr_dat_o(spr_dat_pm),
|
|
|
// Power Management Interface
|
// Power Management Interface
|
.pm_cpustall(pm_cpustall_i),
|
.pm_cpustall(pm_cpustall_i),
|
.pm_clksd(pm_clksd_o),
|
.pm_clksd(pm_clksd_o),
|
.pm_dc_gate(pm_dc_gate_o),
|
.pm_dc_gate(pm_dc_gate_o),
|
.pm_ic_gate(pm_ic_gate_o),
|
.pm_ic_gate(pm_ic_gate_o),
|
.pm_dmmu_gate(pm_dmmu_gate_o),
|
.pm_dmmu_gate(pm_dmmu_gate_o),
|
.pm_immu_gate(pm_immu_gate_o),
|
.pm_immu_gate(pm_immu_gate_o),
|
.pm_tt_gate(pm_tt_gate_o),
|
.pm_tt_gate(pm_tt_gate_o),
|
.pm_cpu_gate(pm_cpu_gate_o),
|
.pm_cpu_gate(pm_cpu_gate_o),
|
.pm_wakeup(pm_wakeup_o),
|
.pm_wakeup(pm_wakeup_o),
|
.pm_lvolt(pm_lvolt_o)
|
.pm_lvolt(pm_lvolt_o)
|
);
|
);
|
|
|
|
|
endmodule
|
endmodule
|
|
|