//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's WISHBONE BIU ////
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//// OR1200's WISHBONE BIU ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Implements WISHBONE interface ////
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//// Implements WISHBONE interface ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - add support for wb_err_i ////
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//// - add support for wb_err_i ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.12 2001/11/22 13:42:51 lampret
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// Revision 1.12 2001/11/22 13:42:51 lampret
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// Added wb_cyc_o assignment after it was removed by accident.
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// Added wb_cyc_o assignment after it was removed by accident.
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//
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//
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// Revision 1.11 2001/11/20 21:28:10 lampret
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// Revision 1.11 2001/11/20 21:28:10 lampret
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// Added optional sampling of inputs.
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// Added optional sampling of inputs.
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//
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//
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// Revision 1.10 2001/11/18 11:32:00 lampret
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// Revision 1.10 2001/11/18 11:32:00 lampret
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// OR1200_REGISTERED_OUTPUTS can now be enabled.
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// OR1200_REGISTERED_OUTPUTS can now be enabled.
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//
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//
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// Revision 1.9 2001/10/21 17:57:16 lampret
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// Revision 1.9 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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//
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// Revision 1.8 2001/10/14 13:12:10 lampret
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// Revision 1.8 2001/10/14 13:12:10 lampret
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// MP3 version.
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// MP3 version.
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//
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//
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// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
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// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
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// no message
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// no message
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//
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//
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// Revision 1.3 2001/08/09 13:39:33 lampret
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// Revision 1.3 2001/08/09 13:39:33 lampret
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// Major clean-up.
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// Major clean-up.
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//
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//
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// Revision 1.2 2001/07/22 03:31:54 lampret
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// Revision 1.2 2001/07/22 03:31:54 lampret
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// Fixed RAM's oen bug. Cache bypass under development.
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// Fixed RAM's oen bug. Cache bypass under development.
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//
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//
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// Revision 1.1 2001/07/20 00:46:23 lampret
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// Revision 1.1 2001/07/20 00:46:23 lampret
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// Development version of RTL. Libraries are missing.
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// Development version of RTL. Libraries are missing.
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//
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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module or1200_wb_biu(
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module or1200_wb_biu(
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// RISC clock, reset and clock control
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// RISC clock, reset and clock control
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clk, rst, clmode,
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clk, rst, clmode,
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// WISHBONE interface
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// WISHBONE interface
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wb_clk_i, wb_rst_i, wb_ack_i, wb_err_i, wb_rty_i, wb_dat_i,
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wb_clk_i, wb_rst_i, wb_ack_i, wb_err_i, wb_rty_i, wb_dat_i,
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wb_cyc_o, wb_adr_o, wb_stb_o, wb_we_o, wb_sel_o, wb_cab_o, wb_dat_o,
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wb_cyc_o, wb_adr_o, wb_stb_o, wb_we_o, wb_sel_o, wb_cab_o, wb_dat_o,
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// Internal RISC bus
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// Internal RISC bus
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biu_dat_i, biu_adr_i, biu_cyc_i, biu_stb_i, biu_we_i, biu_sel_i, biu_cab_i,
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biu_dat_i, biu_adr_i, biu_cyc_i, biu_stb_i, biu_we_i, biu_sel_i, biu_cab_i,
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biu_dat_o, biu_ack_o, biu_err_o
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biu_dat_o, biu_ack_o, biu_err_o
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);
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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//
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//
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// RISC clock, reset and clock control
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// RISC clock, reset and clock control
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//
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//
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input clk; // RISC clock
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input clk; // RISC clock
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input rst; // RISC reset
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input rst; // RISC reset
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input [1:0] clmode; // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
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input [1:0] clmode; // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
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//
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//
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// WISHBONE interface
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// WISHBONE interface
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//
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//
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input wb_clk_i; // clock input
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input wb_clk_i; // clock input
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input wb_rst_i; // reset input
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input wb_rst_i; // reset input
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input wb_ack_i; // normal termination
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input wb_ack_i; // normal termination
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input wb_err_i; // termination w/ error
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input wb_err_i; // termination w/ error
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input wb_rty_i; // termination w/ retry
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input wb_rty_i; // termination w/ retry
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input [dw-1:0] wb_dat_i; // input data bus
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input [dw-1:0] wb_dat_i; // input data bus
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output wb_cyc_o; // cycle valid output
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output wb_cyc_o; // cycle valid output
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output [aw-1:0] wb_adr_o; // address bus outputs
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output [aw-1:0] wb_adr_o; // address bus outputs
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output wb_stb_o; // strobe output
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output wb_stb_o; // strobe output
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output wb_we_o; // indicates write transfer
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output wb_we_o; // indicates write transfer
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output [3:0] wb_sel_o; // byte select outputs
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output [3:0] wb_sel_o; // byte select outputs
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output wb_cab_o; // consecutive address burst
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output wb_cab_o; // consecutive address burst
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output [dw-1:0] wb_dat_o; // output data bus
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output [dw-1:0] wb_dat_o; // output data bus
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//
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//
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// Internal RISC interface
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// Internal RISC interface
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//
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//
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input [dw-1:0] biu_dat_i; // input data bus
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input [dw-1:0] biu_dat_i; // input data bus
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input [aw-1:0] biu_adr_i; // address bus
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input [aw-1:0] biu_adr_i; // address bus
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input biu_cyc_i; // WB cycle
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input biu_cyc_i; // WB cycle
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input biu_stb_i; // WB strobe
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input biu_stb_i; // WB strobe
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input biu_we_i; // WB write enable
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input biu_we_i; // WB write enable
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input biu_cab_i; // CAB input
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input biu_cab_i; // CAB input
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input [3:0] biu_sel_i; // byte selects
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input [3:0] biu_sel_i; // byte selects
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output [31:0] biu_dat_o; // output data bus
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output [31:0] biu_dat_o; // output data bus
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output biu_ack_o; // ack output
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output biu_ack_o; // ack output
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output biu_err_o; // err output
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output biu_err_o; // err output
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//
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//
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// Registers
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// Registers
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//
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//
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reg [1:0] valid_div; // Used for synchronization
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reg [1:0] valid_div; // Used for synchronization
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`ifdef OR1200_REGISTERED_OUTPUTS
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`ifdef OR1200_REGISTERED_OUTPUTS
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reg [aw-1:0] wb_adr_o; // address bus outputs
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reg [aw-1:0] wb_adr_o; // address bus outputs
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reg wb_cyc_o; // cycle output
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reg wb_cyc_o; // cycle output
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reg wb_stb_o; // strobe output
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reg wb_stb_o; // strobe output
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reg wb_we_o; // indicates write transfer
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reg wb_we_o; // indicates write transfer
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reg [3:0] wb_sel_o; // byte select outputs
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reg [3:0] wb_sel_o; // byte select outputs
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reg wb_cab_o; // CAB output
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reg wb_cab_o; // CAB output
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reg [dw-1:0] wb_dat_o; // output data bus
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reg [dw-1:0] wb_dat_o; // output data bus
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`endif
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`endif
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`ifdef OR1200_REGISTERED_INPUTS
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`ifdef OR1200_REGISTERED_INPUTS
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reg long_ack_o; // normal termination
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reg long_ack_o; // normal termination
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reg long_err_o; // error termination
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reg long_err_o; // error termination
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reg [dw-1:0] biu_dat_o; // output data bus
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reg [dw-1:0] biu_dat_o; // output data bus
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`else
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`else
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wire long_ack_o; // normal termination
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wire long_ack_o; // normal termination
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wire long_err_o; // error termination
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wire long_err_o; // error termination
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`endif
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`endif
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//
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//
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// WISHBONE I/F <-> Internal RISC I/F conversion
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// WISHBONE I/F <-> Internal RISC I/F conversion
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//
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//
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//
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//
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// Address bus
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// Address bus
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//
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//
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`ifdef OR1200_REGISTERED_OUTPUTS
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`ifdef OR1200_REGISTERED_OUTPUTS
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always @(posedge wb_clk_i or posedge wb_rst_i)
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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if (wb_rst_i)
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wb_adr_o <= #1 {aw{1'b0}};
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wb_adr_o <= #1 {aw{1'b0}};
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else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i)
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else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i)
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wb_adr_o <= #1 biu_adr_i;
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wb_adr_o <= #1 biu_adr_i;
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`else
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`else
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assign wb_adr_o = biu_adr_i;
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assign wb_adr_o = biu_adr_i;
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`endif
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`endif
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//
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//
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// Input data bus
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// Input data bus
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//
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//
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`ifdef OR1200_REGISTERED_INPUTS
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`ifdef OR1200_REGISTERED_INPUTS
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always @(posedge wb_clk_i or posedge wb_rst_i)
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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if (wb_rst_i)
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biu_dat_o <= #1 32'h0000_0000;
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biu_dat_o <= #1 32'h0000_0000;
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else if (wb_ack_i)
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else if (wb_ack_i)
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biu_dat_o <= #1 wb_dat_i;
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biu_dat_o <= #1 wb_dat_i;
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`else
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`else
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assign biu_dat_o = wb_dat_i;
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assign biu_dat_o = wb_dat_i;
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`endif
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`endif
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//
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//
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// Output data bus
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// Output data bus
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//
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//
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`ifdef OR1200_REGISTERED_OUTPUTS
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`ifdef OR1200_REGISTERED_OUTPUTS
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always @(posedge wb_clk_i or posedge wb_rst_i)
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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if (wb_rst_i)
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wb_dat_o <= #1 {dw{1'b0}};
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wb_dat_o <= #1 {dw{1'b0}};
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else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i)
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else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i)
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wb_dat_o <= #1 biu_dat_i;
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wb_dat_o <= #1 biu_dat_i;
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`else
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`else
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assign wb_dat_o = biu_dat_i;
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assign wb_dat_o = biu_dat_i;
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`endif
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`endif
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//
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//
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// Valid_div counts RISC clock cycles by modulo 4
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// Valid_div counts RISC clock cycles by modulo 4
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// and is used to synchronize external WB i/f to
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// and is used to synchronize external WB i/f to
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// RISC clock
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// RISC clock
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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valid_div <= #1 2'b0;
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valid_div <= #1 2'b0;
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else
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else
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valid_div <= #1 valid_div + 'd1;
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valid_div <= #1 valid_div + 'd1;
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//
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//
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// biu_ack_o is one RISC clock cycle long long_ack_o.
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// biu_ack_o is one RISC clock cycle long long_ack_o.
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// long_ack_o is one, two or four RISC clock cycles long because
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// long_ack_o is one, two or four RISC clock cycles long because
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// WISHBONE can work at 1, 1/2 or 1/4 RISC clock.
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// WISHBONE can work at 1, 1/2 or 1/4 RISC clock.
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//
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//
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assign biu_ack_o = long_ack_o
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assign biu_ack_o = long_ack_o
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`ifdef OR1200_CLKDIV_4_SUPPORTED
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`ifdef OR1200_CLKDIV_4_SUPPORTED
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& (valid_div[1] | ~clmode[1])
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& (valid_div[1] | ~clmode[1])
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`ifdef OR1200_CLKDIV_2_SUPPORTED
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`ifdef OR1200_CLKDIV_2_SUPPORTED
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& (valid_div[0] | ~clmode[0])
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& (valid_div[0] | ~clmode[0])
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`endif
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`endif
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`endif
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`endif
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;
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;
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//
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//
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// Acknowledgment of the data to the RISC
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// Acknowledgment of the data to the RISC
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//
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//
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// long_ack_o
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// long_ack_o
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//
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//
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`ifdef OR1200_REGISTERED_INPUTS
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`ifdef OR1200_REGISTERED_INPUTS
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always @(posedge wb_clk_i or posedge wb_rst_i)
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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if (wb_rst_i)
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long_ack_o <= #1 1'b0;
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long_ack_o <= #1 1'b0;
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else
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else
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long_ack_o <= #1 wb_ack_i;
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long_ack_o <= #1 wb_ack_i;
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`else
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`else
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assign long_ack_o = wb_ack_i;
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assign long_ack_o = wb_ack_i;
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`endif
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`endif
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//
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//
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// biu_err_o is one RISC clock cycle long long_err_o.
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// biu_err_o is one RISC clock cycle long long_err_o.
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// long_err_o is one, two or four RISC clock cycles long because
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// long_err_o is one, two or four RISC clock cycles long because
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// WISHBONE can work at 1, 1/2 or 1/4 RISC clock.
|
// WISHBONE can work at 1, 1/2 or 1/4 RISC clock.
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//
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//
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assign biu_err_o = long_err_o
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assign biu_err_o = long_err_o
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`ifdef OR1200_CLKDIV_4_SUPPORTED
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`ifdef OR1200_CLKDIV_4_SUPPORTED
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& (valid_div[1] | ~clmode[1])
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& (valid_div[1] | ~clmode[1])
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`ifdef OR1200_CLKDIV_2_SUPPORTED
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`ifdef OR1200_CLKDIV_2_SUPPORTED
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& (valid_div[0] | ~clmode[0])
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& (valid_div[0] | ~clmode[0])
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`endif
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`endif
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`endif
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`endif
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;
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;
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|
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//
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//
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// Error termination
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// Error termination
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//
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//
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// long_err_o
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// long_err_o
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//
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//
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`ifdef OR1200_REGISTERED_INPUTS
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`ifdef OR1200_REGISTERED_INPUTS
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always @(posedge wb_clk_i or posedge wb_rst_i)
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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if (wb_rst_i)
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long_err_o <= #1 1'b0;
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long_err_o <= #1 1'b0;
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else
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else
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long_err_o <= #1 wb_err_i;
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long_err_o <= #1 wb_err_i;
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`else
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`else
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assign long_err_o = wb_err_i;
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assign long_err_o = wb_err_i;
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`endif
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`endif
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//
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//
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// WB cyc_o
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// WB cyc_o
|
//
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//
|
`ifdef OR1200_REGISTERED_OUTPUTS
|
`ifdef OR1200_REGISTERED_OUTPUTS
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always @(posedge wb_clk_i or posedge wb_rst_i)
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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if (wb_rst_i)
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wb_cyc_o <= #1 1'b0;
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wb_cyc_o <= #1 1'b0;
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else
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else
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`ifdef OR1200_NO_BURSTS
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wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i;
|
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`else
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wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i | biu_cab_i;
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wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i | biu_cab_i;
|
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`endif
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`else
|
|
`ifdef OR1200_NO_BURSTS
|
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assign wb_cyc_o = biu_cyc_i;
|
`else
|
`else
|
assign wb_cyc_o = biu_cyc_i | biu_cab_i;
|
assign wb_cyc_o = biu_cyc_i | biu_cab_i;
|
`endif
|
`endif
|
|
`endif
|
|
|
//
|
//
|
// WB stb_o
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// WB stb_o
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//
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//
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`ifdef OR1200_REGISTERED_OUTPUTS
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`ifdef OR1200_REGISTERED_OUTPUTS
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always @(posedge wb_clk_i or posedge wb_rst_i)
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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if (wb_rst_i)
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wb_stb_o <= #1 1'b0;
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wb_stb_o <= #1 1'b0;
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else
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else
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wb_stb_o <= #1 (biu_cyc_i & biu_stb_i) & ~wb_ack_i;
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wb_stb_o <= #1 (biu_cyc_i & biu_stb_i) & ~wb_ack_i;
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`else
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`else
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assign wb_stb_o = biu_cyc_i & biu_stb_i;
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assign wb_stb_o = biu_cyc_i & biu_stb_i;
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`endif
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`endif
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//
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//
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// WB we_o
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// WB we_o
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//
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//
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`ifdef OR1200_REGISTERED_OUTPUTS
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`ifdef OR1200_REGISTERED_OUTPUTS
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always @(posedge wb_clk_i or posedge wb_rst_i)
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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if (wb_rst_i)
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wb_we_o <= #1 1'b0;
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wb_we_o <= #1 1'b0;
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else
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else
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wb_we_o <= #1 biu_cyc_i & biu_stb_i & biu_we_i;
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wb_we_o <= #1 biu_cyc_i & biu_stb_i & biu_we_i;
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`else
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`else
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assign wb_we_o = biu_cyc_i & biu_stb_i & biu_we_i;
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assign wb_we_o = biu_cyc_i & biu_stb_i & biu_we_i;
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`endif
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`endif
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|
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//
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//
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// WB sel_o
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// WB sel_o
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//
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//
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`ifdef OR1200_REGISTERED_OUTPUTS
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`ifdef OR1200_REGISTERED_OUTPUTS
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always @(posedge wb_clk_i or posedge wb_rst_i)
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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if (wb_rst_i)
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wb_sel_o <= #1 4'b0000;
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wb_sel_o <= #1 4'b0000;
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else
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else
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wb_sel_o <= #1 biu_sel_i;
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wb_sel_o <= #1 biu_sel_i;
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`else
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`else
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assign wb_sel_o = biu_sel_i;
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assign wb_sel_o = biu_sel_i;
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`endif
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`endif
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|
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//
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//
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// WB cab_o
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// WB cab_o
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//
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//
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`ifdef OR1200_REGISTERED_OUTPUTS
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`ifdef OR1200_REGISTERED_OUTPUTS
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always @(posedge wb_clk_i or posedge wb_rst_i)
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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if (wb_rst_i)
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wb_cab_o <= #1 1'b0;
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wb_cab_o <= #1 1'b0;
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else
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else
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wb_cab_o <= #1 biu_cab_i;
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wb_cab_o <= #1 biu_cab_i;
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`else
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`else
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assign wb_cab_o = biu_cab_i;
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assign wb_cab_o = biu_cab_i;
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`endif
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`endif
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|
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endmodule
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endmodule
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