/* dma.h -- Definition of types and structures for DMA
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/* dma.h -- Definition of types and structures for DMA
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Copyright (C) 2001 by Erez Volk, erez@opencores.org
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Copyright (C) 2001 by Erez Volk, erez@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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*/
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#include "dma_defs.h"
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/* Exported function prototypes */
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/* Exported function prototypes */
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void dma_reset( void );
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void dma_reset( void );
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void dma_clock( void );
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void dma_clock( void );
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void dma_status( void );
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void dma_status( void );
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void set_dma_req_i( unsigned dma_controller, unsigned channel );
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void set_dma_req_i( unsigned dma_controller, unsigned channel );
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void clear_dma_req_i( unsigned dma_controller, unsigned channel );
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void clear_dma_req_i( unsigned dma_controller, unsigned channel );
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void set_dma_nd_i( unsigned dma_controller, unsigned channel );
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void set_dma_nd_i( unsigned dma_controller, unsigned channel );
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void clear_dma_nd_i( unsigned dma_controller, unsigned channel );
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void clear_dma_nd_i( unsigned dma_controller, unsigned channel );
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unsigned check_dma_ack_o( unsigned dma_controller, unsigned channel );
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unsigned check_dma_ack_o( unsigned dma_controller, unsigned channel );
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/* Number of channel per DMA controller */
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#define DMA_NUM_CHANNELS 31
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/* Address space required by one DMA controller */
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#define DMA_ADDR_SPACE 0x400
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/* Relative Register Addresses */
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#define DMA_CSR 0x00
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#define DMA_INT_MSK_A 0x04
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#define DMA_INT_MSK_B 0x08
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#define DMA_INT_SRC_A 0x0C
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#define DMA_INT_SRC_B 0x10
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/* Channel registers definitions */
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#define DMA_CH_BASE 0x20 /* Offset of first channel registers */
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#define DMA_CH_SIZE 0x20 /* Per-channel address space */
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/* Per-channel Register Addresses, relative to channel start */
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#define DMA_CH_CSR 0x00
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#define DMA_CH_SZ 0x04
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#define DMA_CH_A0 0x08
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#define DMA_CH_AM0 0x0C
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#define DMA_CH_A1 0x10
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#define DMA_CH_AM1 0x14
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#define DMA_CH_DESC 0x18
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#define DMA_CH_SWPTR 0x1C
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/* Field Definitions for the Main CSR */
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#define DMA_CSR_PAUSE_OFFSET 0
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/* Field Definitions for the Channel CSR(s) */
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#define DMA_CH_CSR_CH_EN_OFFSET 0
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#define DMA_CH_CSR_DST_SEL_OFFSET 1
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#define DMA_CH_CSR_SRC_SEL_OFFSET 2
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#define DMA_CH_CSR_INC_DST_OFFSET 3
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#define DMA_CH_CSR_INC_SRC_OFFSET 4
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#define DMA_CH_CSR_MODE_OFFSET 5
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#define DMA_CH_CSR_ARS_OFFSET 6
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#define DMA_CH_CSR_USE_ED_OFFSET 7
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#define DMA_CH_CSR_SZ_WB_OFFSET 8
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#define DMA_CH_CSR_STOP_OFFSET 9
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#define DMA_CH_CSR_BUSY_OFFSET 10
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#define DMA_CH_CSR_DONE_OFFSET 11
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#define DMA_CH_CSR_ERR_OFFSET 12
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#define DMA_CH_CSR_PRIORITY_OFFSET 13
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#define DMA_CH_CSR_PRIORITY_WIDTH 3
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#define DMA_CH_CSR_REST_EN_OFFSET 16
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#define DMA_CH_CSR_INE_ERR_OFFSET 17
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#define DMA_CH_CSR_INE_DONE_OFFSET 18
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#define DMA_CH_CSR_INE_CHK_DONE_OFFSET 19
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#define DMA_CH_CSR_INT_ERR_OFFSET 20
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#define DMA_CH_CSR_INT_DONE_OFFSET 21
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#define DMA_CH_CSR_INT_CHUNK_DONE_OFFSET 22
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#define DMA_CH_CSR_RESERVED_OFFSET 23
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#define DMA_CH_CSR_RESERVED_WIDTH 9
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/* Masks -- Writable and readonly parts of the register */
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#define DMA_CH_CSR_WRITE_MASK 0x000FE3FF
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/* Field definitions for Channel Size Registers */
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#define DMA_CH_SZ_TOT_SZ_OFFSET 0
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#define DMA_CH_SZ_TOT_SZ_WIDTH 12
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#define DMA_CH_SZ_CHK_SZ_OFFSET 16
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#define DMA_CH_SZ_CHK_SZ_WIDTH 9
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/* Field definitions for Channel Address Registers CHn_Am */
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#define DMA_CH_A0_ADDR_OFFSET 2
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#define DMA_CH_A0_ADDR_WIDTH 30
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#define DMA_CH_A1_ADDR_OFFSET 2
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#define DMA_CH_A1_ADDR_WIDTH 30
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/* Field definitions for Channel Address Mask Registers CHn_AMm */
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#define DMA_CH_AM0_MASK_OFFSET 4
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#define DMA_CH_AM0_MASK_WIDTH 28
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#define DMA_CH_AM1_MASK_OFFSET 4
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#define DMA_CH_AM1_MASK_WIDTH 28
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/* Field definitions for Channel Linked List descriptor Pointer CHn_DESC */
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#define DMA_CH_DESC_ADDR_OFFSET 2
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#define DMA_CH_DESC_ADDR_WIDTH 30
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/* Field definitions for Channel Software Pointer */
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#define DMA_CH_SWPTR_PTR_OFFSET 2
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#define DMA_CH_SWPTR_PTR_WIDTH 29
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#define DMA_CH_SWPTR_EN_OFFSET 31
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/* Structure of linked list descriptors (offsets of elements) */
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#define DMA_DESC_CSR 0x00
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#define DMA_DESC_ADR0 0x04
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#define DMA_DESC_ADR1 0x08
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#define DMA_DESC_NEXT 0x0C
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/* Field definitions for linked list descriptor DESC_CSR */
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#define DMA_DESC_CSR_EOL_OFFSET 20
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#define DMA_DESC_CSR_INC_SRC_OFFSET 19
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#define DMA_DESC_CSR_INC_DST_OFFSET 18
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#define DMA_DESC_CSR_SRC_SEL_OFFSET 17
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#define DMA_DESC_CSR_DST_SEL_OFFSET 16
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#define DMA_DESC_CSR_TOT_SZ_OFFSET 0
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#define DMA_DESC_CSR_TOT_SZ_WIDTH 12
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/* Implementation of DMA Channel Registers and State */
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/* Implementation of DMA Channel Registers and State */
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struct dma_channel
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struct dma_channel
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{
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{
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/* The controller we belong to */
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/* The controller we belong to */
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struct dma_controller *controller;
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struct dma_controller *controller;
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/* Our channel number and bit mask */
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/* Our channel number and bit mask */
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unsigned channel_number;
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unsigned channel_number;
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unsigned long channel_mask;
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unsigned long channel_mask;
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/* Used for dump, to save dumping all 32 channels */
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/* Used for dump, to save dumping all 32 channels */
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unsigned referenced;
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unsigned referenced;
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/* Inner state of transfer etc. */
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/* Inner state of transfer etc. */
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unsigned load_next_descriptor_when_done;
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unsigned load_next_descriptor_when_done;
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unsigned long current_descriptor;
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unsigned long current_descriptor;
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unsigned long source, destination, source_mask, destination_mask;
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unsigned long source, destination, source_mask, destination_mask;
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unsigned long chunk_size, total_size, words_transferred;
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unsigned long chunk_size, total_size, words_transferred;
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/* The interface registers */
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/* The interface registers */
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struct
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struct
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{
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{
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unsigned long csr;
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unsigned long csr;
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unsigned long sz;
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unsigned long sz;
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unsigned long a0;
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unsigned long a0;
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unsigned long am0;
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unsigned long am0;
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unsigned long a1;
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unsigned long a1;
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unsigned long am1;
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unsigned long am1;
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unsigned long desc;
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unsigned long desc;
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unsigned long swptr;
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unsigned long swptr;
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} regs;
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} regs;
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/* Some control signals */
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/* Some control signals */
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unsigned dma_req_i;
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unsigned dma_req_i;
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unsigned dma_ack_o;
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unsigned dma_ack_o;
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unsigned dma_nd_i;
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unsigned dma_nd_i;
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};
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};
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/* Implementation of DMA Controller Registers and State */
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/* Implementation of DMA Controller Registers and State */
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struct dma_controller
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struct dma_controller
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{
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{
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/* Base address in memory */
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/* Base address in memory */
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oraddr_t baseaddr;
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oraddr_t baseaddr;
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/* Which interrupt number we generate */
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/* Which interrupt number we generate */
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unsigned irq;
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unsigned irq;
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/* Controller Registers */
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/* Controller Registers */
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struct
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struct
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{
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{
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unsigned long csr;
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unsigned long csr;
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unsigned long int_msk_a;
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unsigned long int_msk_a;
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unsigned long int_msk_b;
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unsigned long int_msk_b;
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unsigned long int_src_a;
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unsigned long int_src_a;
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unsigned long int_src_b;
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unsigned long int_src_b;
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} regs;
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} regs;
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/* Channels */
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/* Channels */
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struct dma_channel ch[DMA_NUM_CHANNELS];
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struct dma_channel ch[DMA_NUM_CHANNELS];
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};
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};
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