/* sim.cfg -- Simulator configuration script file
|
/* sim.cfg -- Simulator configuration script file
|
Copyright (C) 2001, Marko Mlinar, markom@opencores.org
|
Copyright (C) 2001, Marko Mlinar, markom@opencores.org
|
|
|
This file includes a lot of help about configurations and default one
|
|
|
|
This file is part of OpenRISC 1000 Architectural Simulator.
|
This file is part of OpenRISC 1000 Architectural Simulator.
|
|
It contains the default configuration and help about configuring
|
|
the simulator.
|
|
|
This program is free software; you can redistribute it and/or modify
|
This program is free software; you can redistribute it and/or modify
|
it under the terms of the GNU General Public License as published by
|
it under the terms of the GNU General Public License as published by
|
the Free Software Foundation; either version 2 of the License, or
|
the Free Software Foundation; either version 2 of the License, or
|
(at your option) any later version.
|
(at your option) any later version.
|
|
|
This program is distributed in the hope that it will be useful,
|
This program is distributed in the hope that it will be useful,
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
GNU General Public License for more details.
|
GNU General Public License for more details.
|
|
|
You should have received a copy of the GNU General Public License
|
You should have received a copy of the GNU General Public License
|
along with this program; if not, write to the Free Software
|
along with this program; if not, write to the Free Software
|
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
|
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
|
|
|
|
|
/* INTRODUCTION
|
/* INTRODUCTION
|
|
|
The or1ksim have various parameters, which can be set in configuration
|
The ork1sim has various parameters, that are set in configuration files
|
files. Multiple configurations may be used and switched between at
|
like this one. The user can switch between configurations at startup by
|
or1ksim startup.
|
specifying the required configuration file with the -f option.
|
By default, or1ksim loads condfiguration file from './sim.cfg' and if not
|
If no configuration file is specified or1ksim searches for the default
|
found it checks '~/.or1k/sim.cfg'. If even this file is not found or
|
configuration file sim.cfg. First it searches for './sim.cfg'. If this
|
all parameters are not defined, default configuration is used.
|
file is not found, it searches for '~/or1k/sim.cfg'. If this file is
|
Users should not rely on default configuration, but rather redefine all
|
not found too, it reverts to the built-in default configuration.
|
critical settings, since default configuration may differ in newer
|
|
versions of the or1ksim.
|
NOTE: Users should not rely on the built-in configuration, since the
|
If multiple configurations are used, user can switch between them by
|
default configuration may differ between version.
|
supplying -f option when starting simulator.
|
Rather create a configuration file that sets all critical values.
|
|
|
This file may contain (standard C) only comments - no // support.
|
|
|
|
Configure files can also be included, using:
|
This file may contain (standard C) comments only - no // support.
|
|
|
|
Configure files may be be included, using:
|
include "file_name_to_include"
|
include "file_name_to_include"
|
|
|
Like normal configuration file, this file is divided in sections,
|
Like normal configuration files, the included file is divided into
|
where each section is described in detail also.
|
sections. Each section is described in detail also.
|
|
|
Some section also have subsections. One example of such subsection is
|
Some section have subsections. One example of such a subsection is:
|
block:
|
|
|
|
device
|
device
|
instance specific parameters...
|
instance specific parameters...
|
enddevice
|
enddevice
|
|
|
which creates a device instance.
|
which creates a device instance.
|
*/
|
*/
|
|
|
|
|
/* MEMORY SECTION
|
/* MEMORY SECTION
|
|
|
This section specifies how is initial memory generated and which blocks
|
This section specifies how the memory is generated and the blocks
|
it consist of.
|
it consists of.
|
|
|
type = random/unknown/pattern
|
type = random/unknown/pattern
|
specifies the initial memory values. 'random' parameter generate
|
Specifies the initial memory values.
|
random memory using seed 'random_seed' parameter. 'pattern' parameter
|
'random' generates random memory using seed 'random_seed'.
|
fills memory with 'pattern' parameter and 'unknown' does not specify
|
'pattern' fills memory with 'pattern'.
|
how memory should be generated - the fastest option.
|
'unknown' does not specify how memory should be generated,
|
|
leaving the memory in a undefined state. This is the fastest
|
|
option.
|
|
|
random_seed =
|
random_seed =
|
random seed for randomizer, used if type = random
|
random seed for randomizer, used if type = 'random'.
|
|
|
pattern =
|
pattern =
|
pattern to fill memory, used if type = pattern
|
pattern to fill memory, used if type = 'pattern'.
|
|
|
nmemories =
|
nmemories =
|
number of memory instances connected
|
number of memory instances connected
|
|
|
instance specific:
|
instance specific:
|
baseaddr =
|
baseaddr =
|
memory start address
|
memory start address
|
|
|
size =
|
size =
|
memory size
|
memory size
|
|
|
name = ""
|
name = ""
|
memory block name
|
memory block name
|
|
|
ce =
|
ce =
|
chip enable index of the memory instance
|
chip enable index of the memory instance
|
|
|
delayr =
|
delayr =
|
cycles, required for read access, -1 if instance does not support reading
|
cycles, required for read access, -1 if instance does not support reading
|
|
|
delayw =
|
delayw =
|
cycles, required for write access, -1 if instance does not support writing
|
cycles, required for write access, -1 if instance does not support writing
|
|
|
16550 = 0/1
|
|
0, if this device is uart 16450 and 1, if it is 16550
|
|
|
|
log = ""
|
log = ""
|
filename, where to log memory accesses to, no log, if log command is not specified
|
filename, where to log memory accesses to, no log, if log command is not specified
|
*/
|
*/
|
|
|
section memory
|
section memory
|
/*random_seed = 12345
|
/*random_seed = 12345
|
type = random*/
|
type = random*/
|
pattern = 0x00
|
pattern = 0x00
|
type = unknown /* Fastest */
|
type = unknown /* Fastest */
|
|
|
nmemories = 2
|
nmemories = 2
|
device 0
|
device 0
|
name = "FLASH"
|
name = "FLASH"
|
ce = 0
|
ce = 0
|
baseaddr = 0x00000000
|
baseaddr = 0x00000000
|
size = 0x00200000
|
size = 0x00200000
|
delayr = 10
|
delayr = 10
|
delayw = -1
|
delayw = -1
|
enddevice
|
enddevice
|
|
|
device 1
|
device 1
|
name = "RAM"
|
name = "RAM"
|
ce = 1
|
ce = 1
|
baseaddr = 0x40000000
|
baseaddr = 0x40000000
|
size = 0x00200000
|
size = 0x00200000
|
delayr = 2
|
delayr = 2
|
delayw = 4
|
delayw = 4
|
enddevice
|
enddevice
|
end
|
end
|
|
|
|
|
/* IMMU SECTION
|
/* IMMU SECTION
|
|
|
This section configures Instruction Memory Menangement Unit
|
This section configures the Instruction Memory Manangement Unit
|
|
|
enabled = 0/1
|
enabled = 0/1
|
whether IMMU is enabled
|
'0': disabled
|
|
'1': enabled
|
(NOTE: UPR bit is set)
|
(NOTE: UPR bit is set)
|
|
|
nsets =
|
nsets =
|
number of ITLB sets; must be power of two
|
number of ITLB sets; must be power of two
|
|
|
nways =
|
nways =
|
number of ITLB ways
|
number of ITLB ways
|
|
|
pagesize =
|
pagesize =
|
instruction page size; must be power of two
|
instruction page size; must be power of two
|
|
|
entrysize =
|
entrysize =
|
instruction entry size in bytes
|
instruction entry size in bytes
|
|
|
ustates =
|
ustates =
|
number of ITLB usage states (2, 3, 4 etc., max is 4)
|
number of ITLB usage states (2, 3, 4 etc., max is 4)
|
|
|
hitdelay =
|
hitdelay =
|
number of cycles immu hit costs
|
number of cycles immu hit costs
|
|
|
missdelay =
|
missdelay =
|
number of cycles immu miss costs
|
number of cycles immu miss costs
|
*/
|
*/
|
|
|
section immu
|
section immu
|
enabled = 0
|
enabled = 0
|
nsets = 32
|
nsets = 32
|
nways = 1
|
nways = 1
|
pagesize = 8192
|
pagesize = 8192
|
hitdelay = 0
|
hitdelay = 0
|
missdelay = 0
|
missdelay = 0
|
end
|
end
|
|
|
|
|
/* DMMU SECTION
|
/* DMMU SECTION
|
|
|
This section configures Data Memory Menangement Unit
|
This section configures the Data Memory Manangement Unit
|
|
|
enabled = 0/1
|
enabled = 0/1
|
whether DMMU is enabled
|
'0': disabled
|
|
'1': enabled
|
(NOTE: UPR bit is set)
|
(NOTE: UPR bit is set)
|
|
|
nsets =
|
nsets =
|
number of DTLB sets; must be power of two
|
number of DTLB sets; must be power of two
|
|
|
nways =
|
nways =
|
number of DTLB ways
|
number of DTLB ways
|
|
|
pagesize =
|
pagesize =
|
data page size; must be power of two
|
data page size; must be power of two
|
|
|
entrysize =
|
entrysize =
|
data entry size in bytes
|
data entry size in bytes
|
|
|
ustates =
|
ustates =
|
number of DTLB usage states (2, 3, 4 etc., max is 4)
|
number of DTLB usage states (2, 3, 4 etc., max is 4)
|
|
|
hitdelay =
|
hitdelay =
|
number of cycles immu hit costs
|
number of cycles dmmu hit costs
|
|
|
missdelay =
|
missdelay =
|
number of cycles immu miss costs
|
number of cycles dmmu miss costs
|
*/
|
*/
|
|
|
section dmmu
|
section dmmu
|
enabled = 0
|
enabled = 0
|
nsets = 32
|
nsets = 32
|
nways = 1
|
nways = 1
|
pagesize = 8192
|
pagesize = 8192
|
hitdelay = 0
|
hitdelay = 0
|
missdelay = 0
|
missdelay = 0
|
end
|
end
|
|
|
|
|
/* IC SECTION
|
/* IC SECTION
|
|
|
This section configures Instruction Cache
|
This section configures the Instruction Cache
|
|
|
enabled = 0/1
|
enabled = 0/1
|
whether IC is enabled
|
'0': disabled
|
|
'1': enabled
|
(NOTE: UPR bit is set)
|
(NOTE: UPR bit is set)
|
|
|
nsets =
|
nsets =
|
number of IC sets; must be power of two
|
number of IC sets; must be power of two
|
|
|
nways =
|
nways =
|
number of IC ways
|
number of IC ways
|
|
|
blocksize =
|
blocksize =
|
IC block size in bytes; must be power of two
|
IC block size in bytes; must be power of two
|
|
|
ustates =
|
ustates =
|
number of IC usage states (2, 3, 4 etc., max is 4)
|
number of IC usage states (2, 3, 4 etc., max is 4)
|
|
|
hitdelay =
|
hitdelay =
|
number of cycles ic hit costs
|
number of cycles ic hit costs
|
|
|
missdelay =
|
missdelay =
|
number of cycles ic miss costs
|
number of cycles ic miss costs
|
*/
|
*/
|
|
|
section ic
|
section ic
|
enabled = 0
|
enabled = 0
|
nsets = 512
|
nsets = 512
|
nways = 1
|
nways = 1
|
blocksize = 16
|
blocksize = 16
|
hitdelay = 0
|
hitdelay = 0
|
missdelay = 0
|
missdelay = 0
|
end
|
end
|
|
|
|
|
/* DC SECTION
|
/* DC SECTION
|
|
|
This section configures Data Cache
|
This section configures the Data Cache
|
|
|
enabled = 0/1
|
enabled = 0/1
|
whether DC is enabled
|
'0': disabled
|
|
'1': enabled
|
(NOTE: UPR bit is set)
|
(NOTE: UPR bit is set)
|
|
|
nsets =
|
nsets =
|
number of DC sets; must be power of two
|
number of DC sets; must be power of two
|
|
|
nways =
|
nways =
|
number of DC ways
|
number of DC ways
|
|
|
blocksize =
|
blocksize =
|
DC block size in bytes; must be power of two
|
DC block size in bytes; must be power of two
|
|
|
ustates =
|
ustates =
|
number of DC usage states (2, 3, 4 etc., max is 4)
|
number of DC usage states (2, 3, 4 etc., max is 4)
|
|
|
load_hitdelay =
|
load_hitdelay =
|
number of cycles dc load hit costs
|
number of cycles dc load hit costs
|
|
|
load_missdelay =
|
load_missdelay =
|
number of cycles dc load miss costs
|
number of cycles dc load miss costs
|
|
|
store_hitdelay =
|
store_hitdelay =
|
number of cycles dc load hit costs
|
number of cycles dc load hit costs
|
|
|
store_missdelay =
|
store_missdelay =
|
number of cycles dc load miss costs
|
number of cycles dc load miss costs
|
*/
|
*/
|
|
|
section dc
|
section dc
|
enabled = 0
|
enabled = 0
|
nsets = 512
|
nsets = 512
|
nways = 1
|
nways = 1
|
blocksize = 16
|
blocksize = 16
|
load_hitdelay = 0
|
load_hitdelay = 0
|
load_missdelay = 0
|
load_missdelay = 0
|
store_hitdelay = 0
|
store_hitdelay = 0
|
store_missdelay = 0
|
store_missdelay = 0
|
end
|
end
|
|
|
/* SIM SECTION
|
/* SIM SECTION
|
|
|
This section specifies how should sim behave.
|
This section specifies how or1ksim should behave.
|
|
|
verbose = 0/1
|
verbose = 0/1
|
whether to print out extra messages
|
'0': don't print extra messages
|
|
'1': print extra messages
|
|
|
debug = 0-9
|
debug = 0-9
|
= 0 disabled debug messages
|
0 : no debug messages
|
1-9 level of sim debug information, greater the number more verbose is
|
1-9: debug message level.
|
the output
|
higher numbers produce more messages
|
|
|
profile = 0/1
|
profile = 0/1
|
whether to generate profiling file 'sim.profile'
|
'0': don't generate profiling file 'sim.profile'
|
|
'1': don't generate profiling file 'sim.profile'
|
|
|
prof_fn = ""
|
prof_fn = ""
|
filename, where to generate profiling info, used
|
optional filename for the profiling file.
|
only if 'profile' is set
|
valid only if 'profile' is set
|
|
|
mprofile = 0/1
|
mprofile = 0/1
|
whether to generate memory profiling file 'sim.mprofile'
|
'0': don't generate memory profiling file 'sim.mprofile'
|
|
'1': generate memory profiling file 'sim.mprofile'
|
|
|
mprof_fn = ""
|
mprof_fn = ""
|
filename, where to generate memory profiling info, used
|
optional filename for the memory profiling file.
|
only if 'mprofile' is set
|
valid only if 'mprofile' is set
|
|
|
history = 0/1
|
history = 0/1
|
whether instruction execution flow is tracked for
|
'0': don't track execution flow
|
display by simulator hist command. Useful for
|
'1': track execution flow
|
back-trace debugging.
|
Execution flow can be tracked for the simulator's
|
|
'hist' command. Useful for back-trace debugging.
|
|
|
iprompt = 0/1
|
iprompt = 0/1
|
whether we strart in interactive prompt
|
'0': start in (so what do we start in ???)
|
|
'1': start in interactive prompt.
|
|
|
exe_log = 0/1
|
exe_log = 0/1
|
whether execution log should be generated
|
'0': don't generate execution log.
|
|
'1': generate execution log.
|
|
|
exe_log = default/hardware/simple/software
|
exe_log = default/hardware/simple/software
|
type of executed log, default is used if not specified
|
type of execution log, default is used when not specified
|
|
|
exe_log_start =
|
exe_log_start =
|
index of first instruction to start log with, default = 0
|
index of first instruction to start logging, default = 0
|
|
|
exe_log_end =
|
exe_log_end =
|
index of last instruction to end log with; not limited, if omitted
|
index of last instruction to end logging; not limited, if omitted
|
|
|
exe_log_marker =
|
exe_log_marker =
|
specifies number of instructions before horizontal marker is
|
specifies number of instructions before horizontal marker is
|
printed; if zero, markers are disabled (default)
|
printed; if zero, markers are disabled (default)
|
|
|
exe_log_fn = ""
|
exe_log_fn = ""
|
where to put execution log in, used only if 'exe_log'
|
filename for the exection log file.
|
is set
|
valid only if 'exe_log' is set
|
|
|
spr_log = 0/1
|
spr_log = 0/1
|
whether log of writes/reads to/from sprs should be generated
|
'0': log reads/writes to/from sprs
|
|
'1': don't log reads/write to/from sprs
|
|
|
spr_log_fn = ""
|
spr_log_fn = ""
|
where to put sprs writes/reads in log, used only if 'spr_log'
|
filename for the sprs log file.
|
is set
|
valid only if 'spr_log' is set
|
|
|
clkcycle = [ps|ns|us|ms]
|
clkcycle = [ps|ns|us|ms]
|
specifies time measurement for one cycle
|
specifies time measurement for one cycle
|
*/
|
*/
|
|
|
section sim
|
section sim
|
/* verbose = 1 */
|
/* verbose = 1 */
|
debug = 3
|
debug = 3
|
profile = 0
|
profile = 0
|
prof_fn = "sim.profile"
|
prof_fn = "sim.profile"
|
mprofile = 0
|
mprofile = 0
|
mprof_fn = "sim.mprofile"
|
mprof_fn = "sim.mprofile"
|
|
|
history = 1
|
history = 1
|
/* iprompt = 0 */
|
/* iprompt = 0 */
|
exe_log = 0
|
exe_log = 0
|
exe_log_type = hardware
|
exe_log_type = hardware
|
exe_log_start = 0
|
exe_log_start = 0
|
exe_log_end = 0
|
exe_log_end = 0
|
exe_log_marker = 0
|
exe_log_marker = 0
|
exe_log_fn = "executed.log"
|
exe_log_fn = "executed.log"
|
spr_log = 0
|
spr_log = 0
|
spr_log_fn = "spr.log"
|
spr_log_fn = "spr.log"
|
clkcycle = 100ns
|
clkcycle = 100ns
|
end
|
end
|
|
|
|
|
/* SECTION VAPI
|
/* SECTION VAPI
|
|
|
This section configures Verification API, used for Advanced
|
This section configures the Verification API, used for Advanced
|
Core Verification.
|
Core Verification.
|
|
|
enabled = 0/1
|
enabled = 0/1
|
whether to start VAPI server
|
'0': disbable VAPI server
|
|
'1': enable/start VAPI server
|
|
|
server_port =
|
server_port =
|
TCP/IP port to start VAPI server on
|
TCP/IP port to start VAPI server on
|
|
|
log_enabled = 0/1
|
log_enabled = 0/1
|
whether logging of VAPI requests is enabled
|
'0': disable VAPI requests logging
|
|
'1': enable VAPI requests logging
|
|
|
hide_device_id = 0/1
|
hide_device_id = 0/1
|
whether to disable logging of device id (for compatability with old version)
|
'0': don't log device id (for compatability with old version)
|
|
'1': log device id
|
|
|
|
|
vapi_fn =
|
vapi_fn =
|
specifies filename where to log into, if log_enabled is selected
|
filename for the log file.
|
|
valid only if log_enabled is set
|
*/
|
*/
|
|
|
section VAPI
|
section VAPI
|
enabled = 0
|
enabled = 0
|
server_port = 9998
|
server_port = 9998
|
log_enabled = 0
|
log_enabled = 0
|
vapi_log_fn = "vapi.log"
|
vapi_log_fn = "vapi.log"
|
end
|
end
|
|
|
|
|
/* CPU SECTION
|
/* CPU SECTION
|
|
|
This section specifies various CPU parameters.
|
This section specifies various CPU parameters.
|
|
|
ver =
|
ver =
|
rev =
|
rev =
|
specifies version and revision of the CPU used
|
specifies version and revision of the CPU used
|
|
|
upr =
|
upr =
|
changes the upr register
|
changes the upr register
|
|
|
sr =
|
sr =
|
sets the initial Supervision Register value
|
sets the initial Supervision Register value
|
|
|
superscalar = 0/1
|
superscalar = 0/1
|
whether CPU is scalar or superscalar
|
'0': CPU is scalar
|
|
'1': CPU is superscalar
|
(modify cpu/or32/execute.c to tune superscalar model)
|
(modify cpu/or32/execute.c to tune superscalar model)
|
|
|
hazards = 0/1
|
hazards = 0/1
|
whether data hazards are tracked in superscalar CPU
|
'0': don't track data hazards in superscalar CPU
|
and displayed by the simulator r command
|
'1': track data hazards in superscalar CPU
|
|
If tracked, data hazards can be displayed using the
|
|
simulator's 'r' command.
|
|
|
dependstats = 0/1
|
dependstats = 0/1
|
whether inter-instruction dependencies are calculated
|
'0': don't calculate inter-instruction dependencies.
|
and displayed by simulator stats command.
|
'1': calculate inter-instruction dependencies.
|
|
If calculated, inter-instruction dependencies can be
|
|
displayed using the simulator's 'stat' command.
|
|
|
raw_range =
|
raw_range =
|
range in cycles for raw register over time analysis, 0 = disabled
|
range in cycles for raw register over time analysis, 0 = disabled
|
|
|
sbuf_len =
|
sbuf_len =
|
length of store buffer (<= 256), 0 = disabled
|
length of store buffer (<= 256), 0 = disabled
|
*/
|
*/
|
|
|
section cpu
|
section cpu
|
ver = 0x1200
|
ver = 0x1200
|
rev = 0x0001
|
rev = 0x0001
|
/* upr = */
|
/* upr = */
|
sr = 0x00008003
|
sr = 0x00008003
|
superscalar = 0
|
superscalar = 0
|
hazards = 0
|
hazards = 0
|
dependstats = 0
|
dependstats = 0
|
raw_range = 0
|
raw_range = 0
|
sbuf_len = 0
|
sbuf_len = 0
|
end
|
end
|
|
|
|
|
/* PM SECTION
|
/* PM SECTION
|
|
|
This section specifies Power Menagement paramaters
|
This section specifies Power Management parameters
|
|
|
enabled = 0/1
|
enabled = 0/1
|
whether power menagement is enabled
|
'0': disable power management
|
|
'1': enable power management
|
*/
|
*/
|
|
|
section pm
|
section pm
|
enabled = 0
|
enabled = 0
|
end
|
end
|
|
|
/* BPB SECTION
|
/* BPB SECTION
|
|
|
This section specifies how branch prediction should behave.
|
This section specifies how branch prediction should behave.
|
|
|
enabled = 0/1
|
enabled = 0/1
|
whether bpb is enabled
|
'0': disable branch prediction
|
|
'1': enable branch prediction
|
|
|
btic = 0/1
|
btic = 0/1
|
enable branch target instruction cache model
|
'0': disable branch target instruction cache model
|
|
'1': enable branch target instruction cache model
|
|
|
sbp_bf_fwd = 0/1
|
sbp_bf_fwd = 0/1
|
whether static branch prediction for l.bf uses forward prediction
|
Static branch prediction for 'l.bf'
|
|
'0': don't use forward prediction
|
|
'1': use forward prediction
|
|
|
sbp_bnf_fwd = 0/1
|
sbp_bnf_fwd = 0/1
|
whether static branch prediction for l.bnf uses forward prediction
|
Static branch prediction for 'l.bnf'
|
|
'0': don't use forward prediction
|
|
'1': use forward prediction
|
|
|
hitdelay =
|
hitdelay =
|
number of cycles bpb hit costs
|
number of cycles bpb hit costs
|
|
|
missdelay =
|
missdelay =
|
number of cycles bpb miss costs
|
number of cycles bpb miss costs
|
*/
|
*/
|
|
|
section bpb
|
section bpb
|
enabled = 0
|
enabled = 0
|
btic = 0
|
btic = 0
|
sbp_bf_fwd = 0
|
sbp_bf_fwd = 0
|
sbp_bnf_fwd = 0
|
sbp_bnf_fwd = 0
|
hitdelay = 0
|
hitdelay = 0
|
missdelay = 0
|
missdelay = 0
|
end
|
end
|
|
|
|
|
/* DEBUG SECTION
|
/* DEBUG SECTION
|
|
|
This sections specifies how debug unit should behave.
|
This sections specifies how the debug unit should behave.
|
|
|
enabled = 0/1
|
enabled = 0/1
|
whether debug unit is enabled
|
'0': disable debug unit
|
|
'1': enable debug unit
|
|
|
gdb_enabled = 0/1
|
gdb_enabled = 0/1
|
whether to start gdb server at 'server_port' port
|
'0': don't start gdb server
|
|
'1': start gdb server at port 'server_port'
|
|
|
server_port =
|
server_port =
|
TCP/IP port to start gdb server on, used only if gdb_enabled
|
TCP/IP port to start gdb server on
|
is set
|
valid only if gdb_enabled is set
|
|
|
vapi_id =
|
vapi_id =
|
Used to create "fake" vapi log file containing the JTAG proxy messages.
|
Used to create "fake" vapi log file containing the JTAG proxy messages.
|
*/
|
*/
|
|
|
section debug
|
section debug
|
enabled = 1
|
enabled = 1
|
gdb_enabled = 0
|
gdb_enabled = 0
|
server_port = 9999
|
server_port = 9999
|
vapi_id = 0xFFFF
|
vapi_id = 0xFFFF
|
end
|
end
|
|
|
|
|
/* MC SECTION
|
/* MC SECTION
|
|
|
This section configures the memory controller
|
This section configures the memory controller
|
|
|
enabled = 0/1
|
enabled = 0/1
|
whether memory controller is enabled
|
'0': disable memory controller
|
|
'1': enable memory controller
|
|
|
baseaddr =
|
baseaddr =
|
address of first MC register
|
address of first MC register
|
|
|
POC =
|
POC =
|
Power On Configuration register
|
Power On Configuration register
|
*/
|
*/
|
|
|
section mc
|
section mc
|
enabled = 0
|
enabled = 0
|
baseaddr = 0x60000000
|
baseaddr = 0x60000000
|
POC = 0x00000008 /* Power on configuration register */
|
POC = 0x00000008 /* Power on configuration register */
|
end
|
end
|
|
|
|
|
/* UART SECTION
|
/* UART SECTION
|
|
|
This section configures UARTs
|
This section configures the UARTs
|
|
|
nuarts =
|
nuarts =
|
make specified number of instances, configure each
|
make specified number of instances, configure each
|
instance within device - enddevice construct.
|
instance within device - enddevice construct.
|
|
|
instance specific:
|
instance specific:
|
baseaddr =
|
baseaddr =
|
address of first UART register for this device
|
address of first UART register for this device
|
|
|
rxfile = ""
|
rxfile = ""
|
filename, where to read data from
|
filename, where to read data from
|
|
|
txfile = ""
|
txfile = ""
|
filename, where to write data to
|
filename, where to write data to
|
|
|
irq =
|
irq =
|
irq number for this device
|
irq number for this device
|
|
|
16550 = 0/1
|
16550 = 0/1
|
0, if this device is uart 16450 and 1, if it is 16550
|
'0': this device is a UART16450
|
|
'1': this device is a UART16550
|
|
|
jitter =
|
jitter =
|
in msecs... time to block, -1 to disable it
|
in msecs... time to block, -1 to disable it
|
|
|
vapi_id =
|
vapi_id =
|
VAPI id of this instance
|
VAPI id of this instance
|
*/
|
*/
|
|
|
section uart
|
section uart
|
nuarts = 1
|
nuarts = 1
|
|
|
device 0
|
device 0
|
baseaddr = 0x90000000
|
baseaddr = 0x90000000
|
irq = 2
|
irq = 2
|
rxfile = "/tmp/uart0.rx"
|
rxfile = "/tmp/uart0.rx"
|
txfile = "/tmp/uart0.tx"
|
txfile = "/tmp/uart0.tx"
|
jitter = -1 /* async behaviour */
|
jitter = -1 /* async behaviour */
|
enddevice
|
enddevice
|
end
|
end
|
|
|
|
|
/* DMA SECTION
|
/* DMA SECTION
|
|
|
This section configures DMAs
|
This section configures the DMAs
|
|
|
ndmas =
|
ndmas =
|
make specified number of instances, configure each
|
make specified number of instances, configure each
|
instance within device - enddevice construct.
|
instance within device - enddevice construct.
|
|
|
instance specific:
|
instance specific:
|
baseaddr =
|
baseaddr =
|
address of first DMA register for this device
|
address of first DMA register for this device
|
|
|
irq =
|
irq =
|
irq number for this device
|
irq number for this device
|
|
|
vapi_id =
|
vapi_id =
|
VAPI id of this instance
|
VAPI id of this instance
|
*/
|
*/
|
|
|
section dma
|
section dma
|
ndmas = 0
|
ndmas = 0
|
/*
|
/*
|
device 0
|
device 0
|
baseaddr = 0x90000000
|
baseaddr = 0x90000000
|
irq = 4
|
irq = 4
|
enddevice
|
enddevice
|
*/
|
*/
|
end
|
end
|
|
|
|
|
/* ETHERNET SECTION
|
/* ETHERNET SECTION
|
|
|
This section configures ethernets
|
This section configures the ETHERNETs
|
|
|
nethernets =
|
nethernets =
|
make specified number of instances, configure each
|
make specified number of instances, configure each
|
instance within device - enddevice construct.
|
instance within device - enddevice construct.
|
|
|
instance specific:
|
instance specific:
|
baseaddr =
|
baseaddr =
|
address of first ethernet register for this device
|
address of first ethernet register for this device
|
|
|
dma =
|
dma =
|
which controller is this ethernet "connected" to
|
which controller is this ethernet "connected" to
|
|
|
irq =
|
irq =
|
ethernet mac IRQ level
|
ethernet mac IRQ level
|
|
|
rtx_type =
|
rtx_type =
|
use 0 - file interface, 1 - socket interface
|
use 0 - file interface, 1 - socket interface
|
|
|
rx_channel =
|
rx_channel =
|
DMA channel used for RX
|
DMA channel used for RX
|
|
|
tx_channel =
|
tx_channel =
|
DMA channel used for TX
|
DMA channel used for TX
|
|
|
rxfile = ""
|
rxfile = ""
|
filename, where to read data from
|
filename, where to read data from
|
|
|
txfile = ""
|
txfile = ""
|
filename, where to write data to
|
filename, where to write data to
|
|
|
sockif = ""
|
sockif = ""
|
interface name of ethernet socket
|
interface name of ethernet socket
|
|
|
vapi_id =
|
vapi_id =
|
VAPI id of this instance
|
VAPI id of this instance
|
*/
|
*/
|
|
|
section ethernet
|
section ethernet
|
nethernets = 1
|
nethernets = 1
|
|
|
|
|
device 0
|
device 0
|
baseaddr = 0x88000000
|
baseaddr = 0x88000000
|
dma = 0
|
dma = 0
|
irq = 15
|
irq = 15
|
rtx_type = 0
|
rtx_type = 0
|
tx_channel = 0
|
tx_channel = 0
|
rx_channel = 1
|
rx_channel = 1
|
rxfile = "/tmp/eth0.rx"
|
rxfile = "/tmp/eth0.rx"
|
txfile = "/tmp/eth0.tx"
|
txfile = "/tmp/eth0.tx"
|
sockif = "lo"
|
sockif = "lo"
|
enddevice
|
enddevice
|
|
|
end
|
end
|
|
|
/* GPIO SECTION
|
/* GPIO SECTION
|
|
|
This section configure GPIOs
|
This section configures the GPIOs
|
|
|
ngpios =
|
ngpios =
|
make specified number of instances, configure each
|
make specified number of instances, configure each
|
instance within device - enddevice construct.
|
instance within device - enddevice construct.
|
|
|
instance specific:
|
instance specific:
|
baseaddr =
|
baseaddr =
|
address of first GPIO register for this device
|
address of first GPIO register for this device
|
|
|
irq =
|
irq =
|
irq number for this device
|
irq number for this device
|
|
|
base_vapi_id =
|
base_vapi_id =
|
first VAPI id of this instance
|
first VAPI id of this instance
|
GPIO uses 8 consecutive VAPI IDs
|
GPIO uses 8 consecutive VAPI IDs
|
*/
|
*/
|
|
|
section gpio
|
section gpio
|
ngpios = 1
|
ngpios = 1
|
|
|
device 0
|
device 0
|
baseaddr = 0xA0000000
|
baseaddr = 0xA0000000
|
irq = 23
|
irq = 23
|
base_vapi_id = 0x0200
|
base_vapi_id = 0x0200
|
enddevice
|
enddevice
|
end
|
end
|
|
|
/* VGA SECTION
|
/* VGA SECTION
|
|
|
This section configures VGA/LCD controller
|
This section configures the VGA/LCD controller
|
|
|
nvgas =
|
nvgas =
|
number of VGA devices connected
|
number of VGA devices connected
|
|
|
instance specific:
|
instance specific:
|
baseaddr =
|
baseaddr =
|
address of first VGA register
|
address of first VGA register
|
|
|
irq =
|
irq =
|
irq number for this device
|
irq number for this device
|
|
|
refresh_rate =
|
refresh_rate =
|
number of cycles between screen dumps
|
number of cycles between screen dumps
|
|
|
filename = ""
|
filename = ""
|
template name for generated names (e.g. "primary" produces "primary0023.bmp")
|
template name for generated names (e.g. "primary" produces "primary0023.bmp")
|
*/
|
*/
|
|
|
section vga
|
section vga
|
nvgas = 1
|
nvgas = 1
|
|
|
device 0
|
device 0
|
baseaddr = 0xb0000000
|
baseaddr = 0xb0000000
|
irq = 20
|
irq = 20
|
refresh_rate = 100000
|
refresh_rate = 100000
|
filename = "primary"
|
filename = "primary"
|
enddevice
|
enddevice
|
end
|
end
|
|
|
/* FB SECTION
|
/* FB SECTION
|
|
|
This section configures frame buffer
|
This section configures the frame buffer
|
|
|
enabled = 0/1
|
enabled = 0/1
|
whether frame buffer is enabled
|
whether frame buffer is enabled
|
|
|
baseaddr =
|
baseaddr =
|
base address of frame buffer
|
base address of frame buffer
|
|
|
paladdr =
|
paladdr =
|
base address of first palette entry
|
base address of first palette entry
|
|
|
refresh_rate =
|
refresh_rate =
|
number of cycles between screen dumps
|
number of cycles between screen dumps
|
|
|
filename = ""
|
filename = ""
|
template name for generated names (e.g. "primary" produces "primary0023.bmp")
|
template name for generated names (e.g. "primary" produces "primary0023.bmp")
|
*/
|
*/
|
|
|
section fb
|
section fb
|
enabled = 1
|
enabled = 1
|
baseaddr = 0xb8000000
|
baseaddr = 0xb8000000
|
refresh_rate = 100000
|
refresh_rate = 100000
|
filename = "primary"
|
filename = "primary"
|
end
|
end
|
|
|
/* KBD SECTION
|
/* KBD SECTION
|
|
|
This section configures PS/2 compatible keyboard
|
This section configures the PS/2 compatible keyboard
|
|
|
enabled = 0/1
|
enabled = 0/1
|
whether keyboard is enabled
|
whether keyboard is enabled
|
|
|
baseaddr =
|
baseaddr =
|
base address of the keyboard device
|
base address of the keyboard device
|
|
|
rxfile = ""
|
rxfile = ""
|
filename, where to read data from
|
filename, where to read data from
|
*/
|
*/
|
|
|
section kbd
|
section kbd
|
enabled = 1
|
enabled = 1
|
irq = 21
|
irq = 21
|
baseaddr = 0xb1000000
|
baseaddr = 0xb1000000
|
rxfile = "/tmp/kbd.rx"
|
rxfile = "/tmp/kbd.rx"
|
end
|
end
|
|
|
|
|
|
/* ATA SECTION
|
|
|
|
This section configures the ATA/ATAPI host controller
|
|
|
|
natas =
|
|
number of ATA hosts connected
|
|
|
|
instance specific:
|
|
baseaddr =
|
|
address of first ATA register
|
|
|
|
irq =
|
|
irq number for this device
|
|
|
|
debug =
|
|
debug level for ata models.
|
|
0: no debug messages
|
|
1: verbose messages
|
|
3: normal messages (more messages than verbose)
|
|
5: debug messages (normal debug messages)
|
|
7: flow control messages (debug statemachine flows)
|
|
9: low priority message (display everything the code does)
|
|
|
|
dev_type0/1 =
|
|
ata device 0 type
|
|
0: NO_CONNeCT: none (not connected)
|
|
1: FILE : simulated harddisk
|
|
2: LOCAL : local system harddisk
|
|
|
|
dev_file0/1 = ""
|
|
filename for simulated ATA device
|
|
valid only if dev_type0 == 1
|
|
|
|
dev_size0/1 =
|
|
size of simulated hard-disk (in MBytes)
|
|
valid only if dev_type0 == 1
|
|
|
|
dev_packet0/1 =
|
|
0: simulated ATA device does NOT implement PACKET command feature set
|
|
1: simulated ATA device does implement PACKET command feature set
|
|
|
|
FIXME: irq number
|
|
*/
|
|
|
|
section ata
|
|
natas = 1
|
|
|
|
device 0
|
|
baseaddr = 0xc8000000
|
|
irq = 21
|
|
|
|
dev_type0 = 1
|
|
dev_file0 = "/tmp/sim_atadev0"
|
|
dev_size0 = 1
|
|
dev_packet0 = 0
|
|
|
|
dev_type1 = 0
|
|
dev_file1 = ""
|
|
dev_size1 = 0
|
|
dev_packet1 = 0
|
|
enddevice
|
|
end
|
|
|
