/* abstract.c -- Abstract entities
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/* abstract.c -- Abstract entities
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 2005 György `nog' Jeney, nog@sdf.lonestar.org
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Copyright (C) 2005 György `nog' Jeney, nog@sdf.lonestar.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* Abstract memory and routines that go with this. I need to
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/* Abstract memory and routines that go with this. I need to
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add all sorts of other abstract entities. Currently we have
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add all sorts of other abstract entities. Currently we have
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only memory. */
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only memory. */
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#include <stdlib.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdio.h>
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#include <ctype.h>
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#include <ctype.h>
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#include <string.h>
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#include <string.h>
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#include "config.h"
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#include "config.h"
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#ifdef HAVE_INTTYPES_H
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#ifdef HAVE_INTTYPES_H
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#include <inttypes.h>
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#include <inttypes.h>
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#endif
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#endif
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#include "port.h"
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#include "port.h"
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#include "arch.h"
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#include "arch.h"
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#include "parse.h"
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#include "parse.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "labels.h"
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#include "labels.h"
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#include "except.h"
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#include "except.h"
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#include "debug_unit.h"
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#include "debug_unit.h"
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#include "opcode/or32.h"
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#include "opcode/or32.h"
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#include "spr_defs.h"
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#include "spr_defs.h"
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#include "execute.h"
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#include "execute.h"
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#include "sprs.h"
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#include "sprs.h"
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#include "support/profile.h"
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#include "support/profile.h"
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#include "dmmu.h"
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#include "dmmu.h"
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#include "immu.h"
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#include "immu.h"
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#include "dcache_model.h"
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#include "dcache_model.h"
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#include "icache_model.h"
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#include "icache_model.h"
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#include "debug.h"
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#include "debug.h"
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#include "stats.h"
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#include "stats.h"
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#if DYNAMIC_EXECUTION
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#if DYNAMIC_EXECUTION
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#include "dyn_rec.h"
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#include "dyn_rec.h"
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#endif
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#endif
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extern char *disassembled;
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extern char *disassembled;
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/* Pointer to memory area descriptions that are assigned to individual
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/* Pointer to memory area descriptions that are assigned to individual
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peripheral devices. */
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peripheral devices. */
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struct dev_memarea *dev_list;
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struct dev_memarea *dev_list;
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/* Temporary variable to increase speed. */
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/* Temporary variable to increase speed. */
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struct dev_memarea *cur_area;
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struct dev_memarea *cur_area;
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/* Pointer to memory controller device descriptor. */
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/* Pointer to memory controller device descriptor. */
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struct dev_memarea *mc_area = NULL;
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struct dev_memarea *mc_area = NULL;
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/* These are set by mmu if cache inhibit bit is set for current acces. */
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/* These are set by mmu if cache inhibit bit is set for current acces. */
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int data_ci, insn_ci;
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int data_ci, insn_ci;
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/* Virtual address of current access. */
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/* Virtual address of current access. */
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static oraddr_t cur_vadd;
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static oraddr_t cur_vadd;
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/* Read functions */
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/* Read functions */
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uint32_t eval_mem_32_inv(oraddr_t, void *);
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uint32_t eval_mem_32_inv(oraddr_t, void *);
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uint16_t eval_mem_16_inv(oraddr_t, void *);
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uint16_t eval_mem_16_inv(oraddr_t, void *);
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uint8_t eval_mem_8_inv(oraddr_t, void *);
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uint8_t eval_mem_8_inv(oraddr_t, void *);
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uint32_t eval_mem_32_inv_direct(oraddr_t, void *);
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uint32_t eval_mem_32_inv_direct(oraddr_t, void *);
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uint16_t eval_mem_16_inv_direct(oraddr_t, void *);
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uint16_t eval_mem_16_inv_direct(oraddr_t, void *);
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uint8_t eval_mem_8_inv_direct(oraddr_t, void *);
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uint8_t eval_mem_8_inv_direct(oraddr_t, void *);
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/* Write functions */
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/* Write functions */
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void set_mem_32_inv(oraddr_t, uint32_t, void *);
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void set_mem_32_inv(oraddr_t, uint32_t, void *);
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void set_mem_16_inv(oraddr_t, uint16_t, void *);
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void set_mem_16_inv(oraddr_t, uint16_t, void *);
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void set_mem_8_inv(oraddr_t, uint8_t, void *);
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void set_mem_8_inv(oraddr_t, uint8_t, void *);
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void set_mem_32_inv_direct(oraddr_t, uint32_t, void *);
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void set_mem_32_inv_direct(oraddr_t, uint32_t, void *);
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void set_mem_16_inv_direct(oraddr_t, uint16_t, void *);
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void set_mem_16_inv_direct(oraddr_t, uint16_t, void *);
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void set_mem_8_inv_direct(oraddr_t, uint8_t, void *);
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void set_mem_8_inv_direct(oraddr_t, uint8_t, void *);
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/* Calculates bit mask to fit the data */
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/* Calculates bit mask to fit the data */
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static unsigned int bit_mask (uint32_t data) {
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static unsigned int bit_mask (uint32_t data) {
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int i = 0;
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int i = 0;
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data--;
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data--;
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while (data >> i)
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while (data >> i)
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data |= 1 << i++;
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data |= 1 << i++;
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return data;
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return data;
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}
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}
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/* Register read and write function for a memory area.
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/* Register read and write function for a memory area.
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addr is inside the area, if addr & addr_mask == addr_compare
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addr is inside the area, if addr & addr_mask == addr_compare
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(used also by peripheral devices like 16450 UART etc.) */
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(used also by peripheral devices like 16450 UART etc.) */
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struct dev_memarea *register_memoryarea_mask(oraddr_t addr_mask,
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struct dev_memarea *register_memoryarea_mask(oraddr_t addr_mask,
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oraddr_t addr_compare,
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oraddr_t addr_compare,
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uint32_t size, unsigned mc_dev)
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uint32_t size, unsigned mc_dev)
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{
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{
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struct dev_memarea **pptmp;
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struct dev_memarea **pptmp;
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unsigned int size_mask = bit_mask (size);
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unsigned int size_mask = bit_mask (size);
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int found_error = 0;
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int found_error = 0;
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addr_compare &= addr_mask;
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addr_compare &= addr_mask;
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debug(5, "addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %08"PRIx32"\n",
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debug(5, "addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %08"PRIx32"\n",
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addr_mask, addr_compare, addr_compare | bit_mask (size), size);
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addr_mask, addr_compare, addr_compare | bit_mask (size), size);
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/* Go to the end of the list. */
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/* Go to the end of the list. */
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for(pptmp = &dev_list; *pptmp; pptmp = &(*pptmp)->next)
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for(pptmp = &dev_list; *pptmp; pptmp = &(*pptmp)->next)
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if (((addr_compare >= (*pptmp)->addr_compare) &&
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if (((addr_compare >= (*pptmp)->addr_compare) &&
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(addr_compare < (*pptmp)->addr_compare + (*pptmp)->size)) ||
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(addr_compare < (*pptmp)->addr_compare + (*pptmp)->size)) ||
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((addr_compare + size > (*pptmp)->addr_compare) &&
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((addr_compare + size > (*pptmp)->addr_compare) &&
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(addr_compare < (*pptmp)->addr_compare + (*pptmp)->size))) {
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(addr_compare < (*pptmp)->addr_compare + (*pptmp)->size))) {
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if (!found_error) {
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if (!found_error) {
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fprintf (stderr, "ERROR: Overlapping memory area(s):\n");
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fprintf (stderr, "ERROR: Overlapping memory area(s):\n");
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fprintf (stderr, "\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR
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fprintf (stderr, "\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR
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", size %08"PRIx32"\n",
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", size %08"PRIx32"\n",
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addr_mask, addr_compare, addr_compare | bit_mask (size), size);
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addr_mask, addr_compare, addr_compare | bit_mask (size), size);
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}
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}
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found_error = 1;
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found_error = 1;
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fprintf (stderr, "and\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR
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fprintf (stderr, "and\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR
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", size %08"PRIx32"\n",
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", size %08"PRIx32"\n",
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(*pptmp)->addr_mask, (*pptmp)->addr_compare,
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(*pptmp)->addr_mask, (*pptmp)->addr_compare,
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(*pptmp)->addr_compare | (*pptmp)->size_mask, (*pptmp)->size);
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(*pptmp)->addr_compare | (*pptmp)->size_mask, (*pptmp)->size);
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}
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}
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if (found_error)
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if (found_error)
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exit (-1);
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exit (-1);
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cur_area = *pptmp = (struct dev_memarea *)malloc(sizeof(struct dev_memarea));
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cur_area = *pptmp = (struct dev_memarea *)malloc(sizeof(struct dev_memarea));
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if (mc_dev)
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if (mc_dev)
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mc_area = *pptmp;
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mc_area = *pptmp;
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(*pptmp)->addr_mask = addr_mask;
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(*pptmp)->addr_mask = addr_mask;
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(*pptmp)->addr_compare = addr_compare;
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(*pptmp)->addr_compare = addr_compare;
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(*pptmp)->size = size;
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(*pptmp)->size = size;
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(*pptmp)->size_mask = size_mask;
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(*pptmp)->size_mask = size_mask;
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(*pptmp)->log = NULL;
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(*pptmp)->log = NULL;
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(*pptmp)->valid = 1;
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(*pptmp)->valid = 1;
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(*pptmp)->next = NULL;
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(*pptmp)->next = NULL;
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return *pptmp;
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return *pptmp;
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}
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}
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/* Register read and write function for a memory area.
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/* Register read and write function for a memory area.
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Memory areas should be aligned. Memory area is rounded up to
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Memory areas should be aligned. Memory area is rounded up to
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fit the nearest 2^n aligment.
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fit the nearest 2^n aligment.
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(used also by peripheral devices like 16450 UART etc.)
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(used also by peripheral devices like 16450 UART etc.)
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If mc_dev is 1, this device will be checked first for a match
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If mc_dev is 1, this device will be checked first for a match
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and will be accessed in case of overlaping memory areas.
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and will be accessed in case of overlaping memory areas.
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Only one device can have this set to 1 (used for memory controller) */
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Only one device can have this set to 1 (used for memory controller) */
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struct dev_memarea *reg_mem_area(oraddr_t addr, uint32_t size, unsigned mc_dev,
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struct dev_memarea *reg_mem_area(oraddr_t addr, uint32_t size, unsigned mc_dev,
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struct mem_ops *ops)
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struct mem_ops *ops)
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{
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{
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unsigned int size_mask = bit_mask (size);
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unsigned int size_mask = bit_mask (size);
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unsigned int addr_mask = ~size_mask;
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unsigned int addr_mask = ~size_mask;
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struct dev_memarea *mem;
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struct dev_memarea *mem;
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mem = register_memoryarea_mask(addr_mask, addr & addr_mask, size_mask + 1,
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mem = register_memoryarea_mask(addr_mask, addr & addr_mask, size_mask + 1,
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mc_dev);
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mc_dev);
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memcpy(&mem->ops, ops, sizeof(struct mem_ops));
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memcpy(&mem->ops, ops, sizeof(struct mem_ops));
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memcpy(&mem->direct_ops, ops, sizeof(struct mem_ops));
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memcpy(&mem->direct_ops, ops, sizeof(struct mem_ops));
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if(!ops->readfunc32) {
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if(!ops->readfunc32) {
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mem->ops.readfunc32 = eval_mem_32_inv;
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mem->ops.readfunc32 = eval_mem_32_inv;
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mem->direct_ops.readfunc32 = eval_mem_32_inv_direct;
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mem->direct_ops.readfunc32 = eval_mem_32_inv_direct;
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mem->direct_ops.read_dat32 = mem;
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mem->direct_ops.read_dat32 = mem;
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}
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}
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if(!ops->readfunc16) {
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if(!ops->readfunc16) {
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mem->ops.readfunc16 = eval_mem_16_inv;
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mem->ops.readfunc16 = eval_mem_16_inv;
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mem->direct_ops.readfunc16 = eval_mem_16_inv_direct;
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mem->direct_ops.readfunc16 = eval_mem_16_inv_direct;
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mem->direct_ops.read_dat16 = mem;
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mem->direct_ops.read_dat16 = mem;
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}
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}
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if(!ops->readfunc8) {
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if(!ops->readfunc8) {
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mem->ops.readfunc8 = eval_mem_8_inv;
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mem->ops.readfunc8 = eval_mem_8_inv;
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mem->direct_ops.readfunc8 = eval_mem_8_inv_direct;
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mem->direct_ops.readfunc8 = eval_mem_8_inv_direct;
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mem->direct_ops.read_dat8 = mem;
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mem->direct_ops.read_dat8 = mem;
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}
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}
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if(!ops->writefunc32) {
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if(!ops->writefunc32) {
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mem->ops.writefunc32 = set_mem_32_inv;
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mem->ops.writefunc32 = set_mem_32_inv;
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mem->direct_ops.writefunc32 = set_mem_32_inv_direct;
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mem->direct_ops.writefunc32 = set_mem_32_inv_direct;
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mem->direct_ops.write_dat32 = mem;
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mem->direct_ops.write_dat32 = mem;
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}
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}
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if(!ops->writefunc16) {
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if(!ops->writefunc16) {
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mem->ops.writefunc16 = set_mem_16_inv;
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mem->ops.writefunc16 = set_mem_16_inv;
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mem->direct_ops.writefunc16 = set_mem_16_inv_direct;
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mem->direct_ops.writefunc16 = set_mem_16_inv_direct;
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mem->direct_ops.write_dat16 = mem;
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mem->direct_ops.write_dat16 = mem;
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}
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}
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if(!ops->writefunc8) {
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if(!ops->writefunc8) {
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mem->ops.writefunc8 = set_mem_8_inv;
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mem->ops.writefunc8 = set_mem_8_inv;
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mem->direct_ops.writefunc8 = set_mem_8_inv_direct;
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mem->direct_ops.writefunc8 = set_mem_8_inv_direct;
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mem->direct_ops.write_dat8 = mem;
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mem->direct_ops.write_dat8 = mem;
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}
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}
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if(!ops->writeprog8) {
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if(!ops->writeprog8) {
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mem->ops.writeprog8 = mem->ops.writefunc8;
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mem->ops.writeprog8 = mem->ops.writefunc8;
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mem->ops.writeprog8_dat = mem->ops.write_dat8;
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mem->ops.writeprog8_dat = mem->ops.write_dat8;
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}
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}
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if(!ops->writeprog32) {
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if(!ops->writeprog32) {
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mem->ops.writeprog32 = mem->ops.writefunc32;
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mem->ops.writeprog32 = mem->ops.writefunc32;
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mem->ops.writeprog32_dat = mem->ops.write_dat32;
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mem->ops.writeprog32_dat = mem->ops.write_dat32;
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}
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}
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if(ops->log) {
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if(ops->log) {
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if(!(mem->log = fopen(ops->log, "w")))
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if(!(mem->log = fopen(ops->log, "w")))
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PRINTF("ERR: Unable to open %s to log memory acesses to\n", ops->log);
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PRINTF("ERR: Unable to open %s to log memory acesses to\n", ops->log);
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}
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}
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return mem;
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return mem;
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}
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}
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/* Check if access is to registered area of memory. */
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/* Check if access is to registered area of memory. */
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inline struct dev_memarea *verify_memoryarea(oraddr_t addr)
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inline struct dev_memarea *verify_memoryarea(oraddr_t addr)
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{
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{
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struct dev_memarea *ptmp;
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struct dev_memarea *ptmp;
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|
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/* Check memory controller space first */
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/* Check memory controller space first */
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if (mc_area && (addr & mc_area->addr_mask) == (mc_area->addr_compare & mc_area->addr_mask))
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if (mc_area && (addr & mc_area->addr_mask) == (mc_area->addr_compare & mc_area->addr_mask))
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return cur_area = mc_area;
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return cur_area = mc_area;
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/* Check cached value */
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/* Check cached value */
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if (cur_area && (addr & cur_area->addr_mask) == (cur_area->addr_compare & cur_area->addr_mask))
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if (cur_area && (addr & cur_area->addr_mask) == (cur_area->addr_compare & cur_area->addr_mask))
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return cur_area;
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return cur_area;
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/* When mc is enabled, we must check valid also, otherwise we assume it is nonzero */
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/* When mc is enabled, we must check valid also, otherwise we assume it is nonzero */
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/* Check list of registered devices. */
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/* Check list of registered devices. */
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for(ptmp = dev_list; ptmp; ptmp = ptmp->next)
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for(ptmp = dev_list; ptmp; ptmp = ptmp->next)
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if ((addr & ptmp->addr_mask) == (ptmp->addr_compare & ptmp->addr_mask) && ptmp->valid)
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if ((addr & ptmp->addr_mask) == (ptmp->addr_compare & ptmp->addr_mask) && ptmp->valid)
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return cur_area = ptmp;
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return cur_area = ptmp;
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return cur_area = NULL;
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return cur_area = NULL;
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}
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}
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/* Sets the valid bit (Used only by memory controllers) */
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/* Sets the valid bit (Used only by memory controllers) */
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void set_mem_valid(struct dev_memarea *mem, int valid)
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void set_mem_valid(struct dev_memarea *mem, int valid)
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{
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{
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mem->valid = valid;
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mem->valid = valid;
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}
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}
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/* Adjusts the read and write delays for the memory area pointed to by mem. */
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/* Adjusts the read and write delays for the memory area pointed to by mem. */
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void adjust_rw_delay(struct dev_memarea *mem, int delayr, int delayw)
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void adjust_rw_delay(struct dev_memarea *mem, int delayr, int delayw)
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{
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{
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mem->ops.delayr = delayr;
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mem->ops.delayr = delayr;
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mem->ops.delayw = delayw;
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mem->ops.delayw = delayw;
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}
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}
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uint8_t eval_mem_8_inv(oraddr_t memaddr, void *dat)
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uint8_t eval_mem_8_inv(oraddr_t memaddr, void *dat)
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{
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{
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except_handle(EXCEPT_BUSERR, cur_vadd);
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except_handle(EXCEPT_BUSERR, cur_vadd);
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return 0;
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return 0;
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}
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}
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uint16_t eval_mem_16_inv(oraddr_t memaddr, void *dat)
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uint16_t eval_mem_16_inv(oraddr_t memaddr, void *dat)
|
{
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{
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except_handle(EXCEPT_BUSERR, cur_vadd);
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except_handle(EXCEPT_BUSERR, cur_vadd);
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return 0;
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return 0;
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}
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}
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uint32_t eval_mem_32_inv(oraddr_t memaddr, void *dat)
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uint32_t eval_mem_32_inv(oraddr_t memaddr, void *dat)
|
{
|
{
|
except_handle(EXCEPT_BUSERR, cur_vadd);
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except_handle(EXCEPT_BUSERR, cur_vadd);
|
return 0;
|
return 0;
|
}
|
}
|
|
|
void set_mem_8_inv(oraddr_t memaddr, uint8_t val, void *dat)
|
void set_mem_8_inv(oraddr_t memaddr, uint8_t val, void *dat)
|
{
|
{
|
except_handle(EXCEPT_BUSERR, cur_vadd);
|
except_handle(EXCEPT_BUSERR, cur_vadd);
|
}
|
}
|
|
|
void set_mem_16_inv(oraddr_t memaddr, uint16_t val, void *dat)
|
void set_mem_16_inv(oraddr_t memaddr, uint16_t val, void *dat)
|
{
|
{
|
except_handle(EXCEPT_BUSERR, cur_vadd);
|
except_handle(EXCEPT_BUSERR, cur_vadd);
|
}
|
}
|
|
|
void set_mem_32_inv(oraddr_t memaddr, uint32_t val, void *dat)
|
void set_mem_32_inv(oraddr_t memaddr, uint32_t val, void *dat)
|
{
|
{
|
except_handle(EXCEPT_BUSERR, cur_vadd);
|
except_handle(EXCEPT_BUSERR, cur_vadd);
|
}
|
}
|
|
|
uint8_t eval_mem_8_inv_direct(oraddr_t memaddr, void *dat)
|
uint8_t eval_mem_8_inv_direct(oraddr_t memaddr, void *dat)
|
{
|
{
|
struct dev_memarea *mem = dat;
|
struct dev_memarea *mem = dat;
|
|
|
PRINTF("ERROR: Invalid 8-bit direct read from memory %"PRIxADDR"\n",
|
PRINTF("ERROR: Invalid 8-bit direct read from memory %"PRIxADDR"\n",
|
mem->addr_compare | memaddr);
|
mem->addr_compare | memaddr);
|
return 0;
|
return 0;
|
}
|
}
|
|
|
uint16_t eval_mem_16_inv_direct(oraddr_t memaddr, void *dat)
|
uint16_t eval_mem_16_inv_direct(oraddr_t memaddr, void *dat)
|
{
|
{
|
struct dev_memarea *mem = dat;
|
struct dev_memarea *mem = dat;
|
|
|
PRINTF("ERROR: Invalid 16-bit direct read from memory %"PRIxADDR"\n",
|
PRINTF("ERROR: Invalid 16-bit direct read from memory %"PRIxADDR"\n",
|
mem->addr_compare | memaddr);
|
mem->addr_compare | memaddr);
|
return 0;
|
return 0;
|
}
|
}
|
|
|
uint32_t eval_mem_32_inv_direct(oraddr_t memaddr, void *dat)
|
uint32_t eval_mem_32_inv_direct(oraddr_t memaddr, void *dat)
|
{
|
{
|
struct dev_memarea *mem = dat;
|
struct dev_memarea *mem = dat;
|
|
|
PRINTF("ERROR: Invalid 32-bit direct read from memory %"PRIxADDR"\n",
|
PRINTF("ERROR: Invalid 32-bit direct read from memory %"PRIxADDR"\n",
|
mem->addr_compare | memaddr);
|
mem->addr_compare | memaddr);
|
return 0;
|
return 0;
|
}
|
}
|
|
|
void set_mem_8_inv_direct(oraddr_t memaddr, uint8_t val, void *dat)
|
void set_mem_8_inv_direct(oraddr_t memaddr, uint8_t val, void *dat)
|
{
|
{
|
struct dev_memarea *mem = dat;
|
struct dev_memarea *mem = dat;
|
|
|
PRINTF("ERROR: Invalid 32-bit direct write to memory %"PRIxADDR"\n",
|
PRINTF("ERROR: Invalid 32-bit direct write to memory %"PRIxADDR"\n",
|
mem->addr_compare | memaddr);
|
mem->addr_compare | memaddr);
|
}
|
}
|
|
|
void set_mem_16_inv_direct(oraddr_t memaddr, uint16_t val, void *dat)
|
void set_mem_16_inv_direct(oraddr_t memaddr, uint16_t val, void *dat)
|
{
|
{
|
struct dev_memarea *mem = dat;
|
struct dev_memarea *mem = dat;
|
|
|
PRINTF("ERROR: Invalid 16-bit direct write to memory %"PRIxADDR"\n",
|
PRINTF("ERROR: Invalid 16-bit direct write to memory %"PRIxADDR"\n",
|
mem->addr_compare | memaddr);
|
mem->addr_compare | memaddr);
|
}
|
}
|
|
|
void set_mem_32_inv_direct(oraddr_t memaddr, uint32_t val, void *dat)
|
void set_mem_32_inv_direct(oraddr_t memaddr, uint32_t val, void *dat)
|
{
|
{
|
struct dev_memarea *mem = dat;
|
struct dev_memarea *mem = dat;
|
|
|
PRINTF("ERROR: Invalid 32-bit direct write to memory %"PRIxADDR"\n",
|
PRINTF("ERROR: Invalid 32-bit direct write to memory %"PRIxADDR"\n",
|
mem->addr_compare | memaddr);
|
mem->addr_compare | memaddr);
|
}
|
}
|
|
|
/* For cpu accesses
|
/* For cpu accesses
|
*
|
*
|
* NOTE: This function _is_ only called from eval_mem32 below and
|
* NOTE: This function _is_ only called from eval_mem32 below and
|
* {i,d}c_simulate_read. _Don't_ call it from anywere else.
|
* {i,d}c_simulate_read. _Don't_ call it from anywere else.
|
*/
|
*/
|
inline uint32_t evalsim_mem32(oraddr_t memaddr, oraddr_t vaddr)
|
inline uint32_t evalsim_mem32(oraddr_t memaddr, oraddr_t vaddr)
|
{
|
{
|
struct dev_memarea *mem;
|
struct dev_memarea *mem;
|
|
|
if((mem = verify_memoryarea(memaddr))) {
|
if((mem = verify_memoryarea(memaddr))) {
|
runtime.sim.mem_cycles += mem->ops.delayr;
|
runtime.sim.mem_cycles += mem->ops.delayr;
|
return mem->ops.readfunc32(memaddr & mem->size_mask, mem->ops.read_dat32);
|
return mem->ops.readfunc32(memaddr & mem->size_mask, mem->ops.read_dat32);
|
} else {
|
} else {
|
PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
|
PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
|
memaddr);
|
memaddr);
|
except_handle(EXCEPT_BUSERR, vaddr);
|
except_handle(EXCEPT_BUSERR, vaddr);
|
}
|
}
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
/* For cpu accesses
|
/* For cpu accesses
|
*
|
*
|
* NOTE: This function _is_ only called from eval_mem16 below and
|
* NOTE: This function _is_ only called from eval_mem16 below and
|
* {i,d}c_simulate_read. _Don't_ call it from anywere else.
|
* {i,d}c_simulate_read. _Don't_ call it from anywere else.
|
*/
|
*/
|
inline uint16_t evalsim_mem16(oraddr_t memaddr, oraddr_t vaddr)
|
inline uint16_t evalsim_mem16(oraddr_t memaddr, oraddr_t vaddr)
|
{
|
{
|
struct dev_memarea *mem;
|
struct dev_memarea *mem;
|
|
|
if((mem = verify_memoryarea(memaddr))) {
|
if((mem = verify_memoryarea(memaddr))) {
|
runtime.sim.mem_cycles += mem->ops.delayr;
|
runtime.sim.mem_cycles += mem->ops.delayr;
|
return mem->ops.readfunc16(memaddr & mem->size_mask, mem->ops.read_dat16);
|
return mem->ops.readfunc16(memaddr & mem->size_mask, mem->ops.read_dat16);
|
} else {
|
} else {
|
PRINTF("EXCEPTION: read out of memory (16-bit access to %"PRIxADDR")\n",
|
PRINTF("EXCEPTION: read out of memory (16-bit access to %"PRIxADDR")\n",
|
memaddr);
|
memaddr);
|
except_handle(EXCEPT_BUSERR, vaddr);
|
except_handle(EXCEPT_BUSERR, vaddr);
|
}
|
}
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
/* For cpu accesses
|
/* For cpu accesses
|
*
|
*
|
* NOTE: This function _is_ only called from eval_mem8 below and
|
* NOTE: This function _is_ only called from eval_mem8 below and
|
* {i,d}c_simulate_read. _Don't_ call it from anywere else.
|
* {i,d}c_simulate_read. _Don't_ call it from anywere else.
|
*/
|
*/
|
inline uint8_t evalsim_mem8(oraddr_t memaddr, oraddr_t vaddr)
|
inline uint8_t evalsim_mem8(oraddr_t memaddr, oraddr_t vaddr)
|
{
|
{
|
struct dev_memarea *mem;
|
struct dev_memarea *mem;
|
|
|
if((mem = verify_memoryarea(memaddr))) {
|
if((mem = verify_memoryarea(memaddr))) {
|
runtime.sim.mem_cycles += mem->ops.delayr;
|
runtime.sim.mem_cycles += mem->ops.delayr;
|
return mem->ops.readfunc8(memaddr & mem->size_mask, mem->ops.read_dat8);
|
return mem->ops.readfunc8(memaddr & mem->size_mask, mem->ops.read_dat8);
|
} else {
|
} else {
|
PRINTF("EXCEPTION: read out of memory (8-bit access to %"PRIxADDR")\n",
|
PRINTF("EXCEPTION: read out of memory (8-bit access to %"PRIxADDR")\n",
|
memaddr);
|
memaddr);
|
except_handle(EXCEPT_BUSERR, vaddr);
|
except_handle(EXCEPT_BUSERR, vaddr);
|
}
|
}
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
/* Returns 32-bit values from mem array. Big endian version.
|
/* Returns 32-bit values from mem array. Big endian version.
|
*
|
*
|
* STATISTICS OK (only used for cpu_access, that is architectural access)
|
* STATISTICS OK (only used for cpu_access, that is architectural access)
|
*/
|
*/
|
uint32_t eval_mem32(oraddr_t memaddr,int* breakpoint)
|
uint32_t eval_mem32(oraddr_t memaddr,int* breakpoint)
|
{
|
{
|
uint32_t temp;
|
uint32_t temp;
|
oraddr_t phys_memaddr;
|
oraddr_t phys_memaddr;
|
|
|
if (config.sim.mprofile)
|
if (config.sim.mprofile)
|
mprofile (memaddr, MPROF_32 | MPROF_READ);
|
mprofile (memaddr, MPROF_32 | MPROF_READ);
|
|
|
if (memaddr & 3) {
|
if (memaddr & 3) {
|
except_handle (EXCEPT_ALIGN, memaddr);
|
except_handle (EXCEPT_ALIGN, memaddr);
|
return 0;
|
return 0;
|
}
|
}
|
|
|
if (config.debug.enabled)
|
if (config.debug.enabled)
|
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
|
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
|
|
|
phys_memaddr = dmmu_translate(memaddr, 0);
|
phys_memaddr = dmmu_translate(memaddr, 0);
|
if (except_pending)
|
if (except_pending)
|
return 0;
|
return 0;
|
|
|
if (config.dc.enabled)
|
if (config.dc.enabled)
|
temp = dc_simulate_read(phys_memaddr, memaddr, 4);
|
temp = dc_simulate_read(phys_memaddr, memaddr, 4);
|
else
|
else
|
temp = evalsim_mem32(phys_memaddr, memaddr);
|
temp = evalsim_mem32(phys_memaddr, memaddr);
|
|
|
if (config.debug.enabled)
|
if (config.debug.enabled)
|
*breakpoint += CheckDebugUnit(DebugLoadData,temp); /* MM170901 */
|
*breakpoint += CheckDebugUnit(DebugLoadData,temp); /* MM170901 */
|
|
|
return temp;
|
return temp;
|
}
|
}
|
|
|
/* for simulator accesses, the ones that cpu wouldn't do
|
/* for simulator accesses, the ones that cpu wouldn't do
|
*
|
*
|
* STATISTICS OK
|
* STATISTICS OK
|
*/
|
*/
|
uint32_t eval_direct32(oraddr_t memaddr, int through_mmu, int through_dc)
|
uint32_t eval_direct32(oraddr_t memaddr, int through_mmu, int through_dc)
|
{
|
{
|
oraddr_t phys_memaddr;
|
oraddr_t phys_memaddr;
|
struct dev_memarea *mem;
|
struct dev_memarea *mem;
|
|
|
if (memaddr & 3) {
|
if (memaddr & 3) {
|
PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
|
PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
|
return 0;
|
return 0;
|
}
|
}
|
|
|
phys_memaddr = memaddr;
|
phys_memaddr = memaddr;
|
|
|
if (through_mmu)
|
if (through_mmu)
|
phys_memaddr = peek_into_dtlb(memaddr, 0, through_dc);
|
phys_memaddr = peek_into_dtlb(memaddr, 0, through_dc);
|
|
|
if (through_dc)
|
if (through_dc)
|
return dc_simulate_read(phys_memaddr, memaddr, 4);
|
return dc_simulate_read(phys_memaddr, memaddr, 4);
|
else {
|
else {
|
if((mem = verify_memoryarea(phys_memaddr)))
|
if((mem = verify_memoryarea(phys_memaddr)))
|
return mem->direct_ops.readfunc32(phys_memaddr & mem->size_mask,
|
return mem->direct_ops.readfunc32(phys_memaddr & mem->size_mask,
|
mem->direct_ops.read_dat32);
|
mem->direct_ops.read_dat32);
|
else
|
else
|
PRINTF("ERR: 32-bit read out of memory area: %"PRIxADDR" (physical: %"
|
PRINTF("ERR: 32-bit read out of memory area: %"PRIxADDR" (physical: %"
|
PRIxADDR"\n", memaddr, phys_memaddr);
|
PRIxADDR"\n", memaddr, phys_memaddr);
|
}
|
}
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
|
|
/* Returns 32-bit values from mem array. Big endian version.
|
/* Returns 32-bit values from mem array. Big endian version.
|
*
|
*
|
* STATISTICS OK (only used for cpu_access, that is architectural access)
|
* STATISTICS OK (only used for cpu_access, that is architectural access)
|
*/
|
*/
|
uint32_t eval_insn(oraddr_t memaddr, int* breakpoint)
|
uint32_t eval_insn(oraddr_t memaddr, int* breakpoint)
|
{
|
{
|
uint32_t temp;
|
uint32_t temp;
|
oraddr_t phys_memaddr;
|
oraddr_t phys_memaddr;
|
|
|
if (config.sim.mprofile)
|
if (config.sim.mprofile)
|
mprofile (memaddr, MPROF_32 | MPROF_FETCH);
|
mprofile (memaddr, MPROF_32 | MPROF_FETCH);
|
// memaddr = simulate_ic_mmu_fetch(memaddr);
|
// memaddr = simulate_ic_mmu_fetch(memaddr);
|
|
|
phys_memaddr = memaddr;
|
phys_memaddr = memaddr;
|
#if !(DYNAMIC_EXECUTION)
|
#if !(DYNAMIC_EXECUTION)
|
phys_memaddr = immu_translate(memaddr);
|
phys_memaddr = immu_translate(memaddr);
|
|
|
if (except_pending)
|
if (except_pending)
|
return 0;
|
return 0;
|
#endif
|
#endif
|
|
|
if (config.debug.enabled)
|
if (config.debug.enabled)
|
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr);
|
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr);
|
|
|
if (config.ic.enabled)
|
if (config.ic.enabled)
|
temp = ic_simulate_fetch(phys_memaddr, memaddr);
|
temp = ic_simulate_fetch(phys_memaddr, memaddr);
|
else
|
else
|
temp = evalsim_mem32(phys_memaddr, memaddr);
|
temp = evalsim_mem32(phys_memaddr, memaddr);
|
|
|
if (config.debug.enabled)
|
if (config.debug.enabled)
|
*breakpoint += CheckDebugUnit(DebugLoadData,temp);
|
*breakpoint += CheckDebugUnit(DebugLoadData,temp);
|
return temp;
|
return temp;
|
}
|
}
|
|
|
/* Returns 32-bit values from mem array. Big endian version.
|
/* Returns 32-bit values from mem array. Big endian version.
|
*
|
*
|
* STATISTICS OK
|
* STATISTICS OK
|
*/
|
*/
|
uint32_t eval_insn_direct(oraddr_t memaddr, int through_mmu)
|
uint32_t eval_insn_direct(oraddr_t memaddr, int through_mmu)
|
{
|
{
|
if(through_mmu)
|
if(through_mmu)
|
memaddr = peek_into_itlb(memaddr);
|
memaddr = peek_into_itlb(memaddr);
|
|
|
return eval_direct32(memaddr, 0, 0);
|
return eval_direct32(memaddr, 0, 0);
|
}
|
}
|
|
|
|
|
/* Returns 16-bit values from mem array. Big endian version.
|
/* Returns 16-bit values from mem array. Big endian version.
|
*
|
*
|
* STATISTICS OK (only used for cpu_access, that is architectural access)
|
* STATISTICS OK (only used for cpu_access, that is architectural access)
|
*/
|
*/
|
uint16_t eval_mem16(oraddr_t memaddr,int* breakpoint)
|
uint16_t eval_mem16(oraddr_t memaddr,int* breakpoint)
|
{
|
{
|
uint16_t temp;
|
uint16_t temp;
|
oraddr_t phys_memaddr;
|
oraddr_t phys_memaddr;
|
|
|
if (config.sim.mprofile)
|
if (config.sim.mprofile)
|
mprofile (memaddr, MPROF_16 | MPROF_READ);
|
mprofile (memaddr, MPROF_16 | MPROF_READ);
|
|
|
if (memaddr & 1) {
|
if (memaddr & 1) {
|
except_handle (EXCEPT_ALIGN, memaddr);
|
except_handle (EXCEPT_ALIGN, memaddr);
|
return 0;
|
return 0;
|
}
|
}
|
|
|
if (config.debug.enabled)
|
if (config.debug.enabled)
|
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
|
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
|
|
|
phys_memaddr = dmmu_translate(memaddr, 0);
|
phys_memaddr = dmmu_translate(memaddr, 0);
|
if (except_pending)
|
if (except_pending)
|
return 0;
|
return 0;
|
|
|
if (config.dc.enabled)
|
if (config.dc.enabled)
|
temp = dc_simulate_read(phys_memaddr, memaddr, 2);
|
temp = dc_simulate_read(phys_memaddr, memaddr, 2);
|
else
|
else
|
temp = evalsim_mem16(phys_memaddr, memaddr);
|
temp = evalsim_mem16(phys_memaddr, memaddr);
|
|
|
if (config.debug.enabled)
|
if (config.debug.enabled)
|
*breakpoint += CheckDebugUnit(DebugLoadData,temp); /* MM170901 */
|
*breakpoint += CheckDebugUnit(DebugLoadData,temp); /* MM170901 */
|
|
|
return temp;
|
return temp;
|
}
|
}
|
|
|
/* for simulator accesses, the ones that cpu wouldn't do
|
/* for simulator accesses, the ones that cpu wouldn't do
|
*
|
*
|
* STATISTICS OK.
|
* STATISTICS OK.
|
*/
|
*/
|
uint16_t eval_direct16(oraddr_t memaddr, int through_mmu, int through_dc)
|
uint16_t eval_direct16(oraddr_t memaddr, int through_mmu, int through_dc)
|
{
|
{
|
oraddr_t phys_memaddr;
|
oraddr_t phys_memaddr;
|
struct dev_memarea *mem;
|
struct dev_memarea *mem;
|
|
|
if (memaddr & 1) {
|
if (memaddr & 1) {
|
PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
|
PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
|
return 0;
|
return 0;
|
}
|
}
|
|
|
phys_memaddr = memaddr;
|
phys_memaddr = memaddr;
|
|
|
if (through_mmu)
|
if (through_mmu)
|
phys_memaddr = peek_into_dtlb(memaddr, 0, through_dc);
|
phys_memaddr = peek_into_dtlb(memaddr, 0, through_dc);
|
|
|
if (through_dc)
|
if (through_dc)
|
return dc_simulate_read(phys_memaddr, memaddr, 2);
|
return dc_simulate_read(phys_memaddr, memaddr, 2);
|
else {
|
else {
|
if((mem = verify_memoryarea(phys_memaddr)))
|
if((mem = verify_memoryarea(phys_memaddr)))
|
return mem->direct_ops.readfunc16(phys_memaddr & mem->size_mask,
|
return mem->direct_ops.readfunc16(phys_memaddr & mem->size_mask,
|
mem->direct_ops.read_dat16);
|
mem->direct_ops.read_dat16);
|
else
|
else
|
PRINTF("ERR: 16-bit read out of memory area: %"PRIxADDR" (physical: %"
|
PRINTF("ERR: 16-bit read out of memory area: %"PRIxADDR" (physical: %"
|
PRIxADDR"\n", memaddr, phys_memaddr);
|
PRIxADDR"\n", memaddr, phys_memaddr);
|
}
|
}
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
/* Returns 8-bit values from mem array.
|
/* Returns 8-bit values from mem array.
|
*
|
*
|
* STATISTICS OK (only used for cpu_access, that is architectural access)
|
* STATISTICS OK (only used for cpu_access, that is architectural access)
|
*/
|
*/
|
uint8_t eval_mem8(oraddr_t memaddr,int* breakpoint)
|
uint8_t eval_mem8(oraddr_t memaddr,int* breakpoint)
|
{
|
{
|
uint8_t temp;
|
uint8_t temp;
|
oraddr_t phys_memaddr;
|
oraddr_t phys_memaddr;
|
|
|
if (config.sim.mprofile)
|
if (config.sim.mprofile)
|
mprofile (memaddr, MPROF_8 | MPROF_READ);
|
mprofile (memaddr, MPROF_8 | MPROF_READ);
|
|
|
if (config.debug.enabled)
|
if (config.debug.enabled)
|
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
|
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
|
|
|
phys_memaddr = dmmu_translate(memaddr, 0);
|
phys_memaddr = dmmu_translate(memaddr, 0);
|
if (except_pending)
|
if (except_pending)
|
return 0;
|
return 0;
|
|
|
if (config.dc.enabled)
|
if (config.dc.enabled)
|
temp = dc_simulate_read(phys_memaddr, memaddr, 1);
|
temp = dc_simulate_read(phys_memaddr, memaddr, 1);
|
else
|
else
|
temp = evalsim_mem8(phys_memaddr, memaddr);
|
temp = evalsim_mem8(phys_memaddr, memaddr);
|
|
|
if (config.debug.enabled)
|
if (config.debug.enabled)
|
*breakpoint += CheckDebugUnit(DebugLoadData,temp); /* MM170901 */
|
*breakpoint += CheckDebugUnit(DebugLoadData,temp); /* MM170901 */
|
return temp;
|
return temp;
|
}
|
}
|
|
|
/* for simulator accesses, the ones that cpu wouldn't do
|
/* for simulator accesses, the ones that cpu wouldn't do
|
*
|
*
|
* STATISTICS OK.
|
* STATISTICS OK.
|
*/
|
*/
|
uint8_t eval_direct8(oraddr_t memaddr, int through_mmu, int through_dc)
|
uint8_t eval_direct8(oraddr_t memaddr, int through_mmu, int through_dc)
|
{
|
{
|
oraddr_t phys_memaddr;
|
oraddr_t phys_memaddr;
|
struct dev_memarea *mem;
|
struct dev_memarea *mem;
|
|
|
phys_memaddr = memaddr;
|
phys_memaddr = memaddr;
|
|
|
if (through_mmu)
|
if (through_mmu)
|
phys_memaddr = peek_into_dtlb(memaddr, 0, through_dc);
|
phys_memaddr = peek_into_dtlb(memaddr, 0, through_dc);
|
|
|
if (through_dc)
|
if (through_dc)
|
return dc_simulate_read(phys_memaddr, memaddr, 1);
|
return dc_simulate_read(phys_memaddr, memaddr, 1);
|
else {
|
else {
|
if((mem = verify_memoryarea(phys_memaddr)))
|
if((mem = verify_memoryarea(phys_memaddr)))
|
return mem->direct_ops.readfunc8(phys_memaddr & mem->size_mask,
|
return mem->direct_ops.readfunc8(phys_memaddr & mem->size_mask,
|
mem->direct_ops.read_dat8);
|
mem->direct_ops.read_dat8);
|
else
|
else
|
PRINTF("ERR: 8-bit read out of memory area: %"PRIxADDR" (physical: %"
|
PRINTF("ERR: 8-bit read out of memory area: %"PRIxADDR" (physical: %"
|
PRIxADDR"\n", memaddr, phys_memaddr);
|
PRIxADDR"\n", memaddr, phys_memaddr);
|
}
|
}
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
/* For cpu accesses
|
/* For cpu accesses
|
*
|
*
|
* NOTE: This function _is_ only called from set_mem32 below and
|
* NOTE: This function _is_ only called from set_mem32 below and
|
* dc_simulate_write. _Don't_ call it from anywere else.
|
* dc_simulate_write. _Don't_ call it from anywere else.
|
*/
|
*/
|
inline void setsim_mem32(oraddr_t memaddr, oraddr_t vaddr, uint32_t value)
|
inline void setsim_mem32(oraddr_t memaddr, oraddr_t vaddr, uint32_t value)
|
{
|
{
|
struct dev_memarea *mem;
|
struct dev_memarea *mem;
|
|
|
if((mem = verify_memoryarea(memaddr))) {
|
if((mem = verify_memoryarea(memaddr))) {
|
cur_vadd = vaddr;
|
cur_vadd = vaddr;
|
runtime.sim.mem_cycles += mem->ops.delayw;
|
runtime.sim.mem_cycles += mem->ops.delayw;
|
mem->ops.writefunc32(memaddr & mem->size_mask, value, mem->ops.write_dat32);
|
mem->ops.writefunc32(memaddr & mem->size_mask, value, mem->ops.write_dat32);
|
#if DYNAMIC_EXECUTION
|
#if DYNAMIC_EXECUTION
|
dyn_checkwrite(memaddr);
|
dyn_checkwrite(memaddr);
|
#endif
|
#endif
|
} else {
|
} else {
|
PRINTF("EXCEPTION: write out of memory (32-bit access to %"PRIxADDR")\n",
|
PRINTF("EXCEPTION: write out of memory (32-bit access to %"PRIxADDR")\n",
|
memaddr);
|
memaddr);
|
except_handle(EXCEPT_BUSERR, vaddr);
|
except_handle(EXCEPT_BUSERR, vaddr);
|
}
|
}
|
}
|
}
|
|
|
/* For cpu accesses
|
/* For cpu accesses
|
*
|
*
|
* NOTE: This function _is_ only called from set_mem16 below and
|
* NOTE: This function _is_ only called from set_mem16 below and
|
* dc_simulate_write. _Don't_ call it from anywere else.
|
* dc_simulate_write. _Don't_ call it from anywere else.
|
*/
|
*/
|
inline void setsim_mem16(oraddr_t memaddr, oraddr_t vaddr, uint16_t value)
|
inline void setsim_mem16(oraddr_t memaddr, oraddr_t vaddr, uint16_t value)
|
{
|
{
|
struct dev_memarea *mem;
|
struct dev_memarea *mem;
|
|
|
if((mem = verify_memoryarea(memaddr))) {
|
if((mem = verify_memoryarea(memaddr))) {
|
cur_vadd = vaddr;
|
cur_vadd = vaddr;
|
runtime.sim.mem_cycles += mem->ops.delayw;
|
runtime.sim.mem_cycles += mem->ops.delayw;
|
mem->ops.writefunc16(memaddr & mem->size_mask, value, mem->ops.write_dat16);
|
mem->ops.writefunc16(memaddr & mem->size_mask, value, mem->ops.write_dat16);
|
#if DYNAMIC_EXECUTION
|
#if DYNAMIC_EXECUTION
|
dyn_checkwrite(memaddr);
|
dyn_checkwrite(memaddr);
|
#endif
|
#endif
|
} else {
|
} else {
|
PRINTF("EXCEPTION: write out of memory (16-bit access to %"PRIxADDR")\n",
|
PRINTF("EXCEPTION: write out of memory (16-bit access to %"PRIxADDR")\n",
|
memaddr);
|
memaddr);
|
except_handle(EXCEPT_BUSERR, vaddr);
|
except_handle(EXCEPT_BUSERR, vaddr);
|
}
|
}
|
}
|
}
|
|
|
/* For cpu accesses
|
/* For cpu accesses
|
*
|
*
|
* NOTE: This function _is_ only called from set_mem8 below and
|
* NOTE: This function _is_ only called from set_mem8 below and
|
* dc_simulate_write. _Don't_ call it from anywere else.
|
* dc_simulate_write. _Don't_ call it from anywere else.
|
*/
|
*/
|
inline void setsim_mem8(oraddr_t memaddr, oraddr_t vaddr, uint8_t value)
|
inline void setsim_mem8(oraddr_t memaddr, oraddr_t vaddr, uint8_t value)
|
{
|
{
|
struct dev_memarea *mem;
|
struct dev_memarea *mem;
|
|
|
if((mem = verify_memoryarea(memaddr))) {
|
if((mem = verify_memoryarea(memaddr))) {
|
cur_vadd = vaddr;
|
cur_vadd = vaddr;
|
runtime.sim.mem_cycles += mem->ops.delayw;
|
runtime.sim.mem_cycles += mem->ops.delayw;
|
mem->ops.writefunc8(memaddr & mem->size_mask, value, mem->ops.write_dat8);
|
mem->ops.writefunc8(memaddr & mem->size_mask, value, mem->ops.write_dat8);
|
#if DYNAMIC_EXECUTION
|
#if DYNAMIC_EXECUTION
|
dyn_checkwrite(memaddr);
|
dyn_checkwrite(memaddr);
|
#endif
|
#endif
|
} else {
|
} else {
|
PRINTF("EXCEPTION: write out of memory (8-bit access to %"PRIxADDR")\n",
|
PRINTF("EXCEPTION: write out of memory (8-bit access to %"PRIxADDR")\n",
|
memaddr);
|
memaddr);
|
except_handle(EXCEPT_BUSERR, vaddr);
|
except_handle(EXCEPT_BUSERR, vaddr);
|
}
|
}
|
}
|
}
|
|
|
/* Set mem, 32-bit. Big endian version.
|
/* Set mem, 32-bit. Big endian version.
|
*
|
*
|
* STATISTICS OK. (the only suspicious usage is in sim-cmd.c,
|
* STATISTICS OK. (the only suspicious usage is in sim-cmd.c,
|
* where this instruction is used for patching memory,
|
* where this instruction is used for patching memory,
|
* wether this is cpu or architectual access is yet to
|
* wether this is cpu or architectual access is yet to
|
* be decided)
|
* be decided)
|
*/
|
*/
|
void set_mem32(oraddr_t memaddr, uint32_t value, int* breakpoint)
|
void set_mem32(oraddr_t memaddr, uint32_t value, int* breakpoint)
|
{
|
{
|
oraddr_t phys_memaddr;
|
oraddr_t phys_memaddr;
|
|
|
if (config.sim.mprofile)
|
if (config.sim.mprofile)
|
mprofile (memaddr, MPROF_32 | MPROF_WRITE);
|
mprofile (memaddr, MPROF_32 | MPROF_WRITE);
|
|
|
if (memaddr & 3) {
|
if (memaddr & 3) {
|
except_handle (EXCEPT_ALIGN, memaddr);
|
except_handle (EXCEPT_ALIGN, memaddr);
|
return;
|
return;
|
}
|
}
|
|
|
phys_memaddr = dmmu_translate(memaddr, 1);;
|
phys_memaddr = dmmu_translate(memaddr, 1);;
|
/* If we produced exception don't set anything */
|
/* If we produced exception don't set anything */
|
if (except_pending)
|
if (except_pending)
|
return;
|
return;
|
|
|
if (config.debug.enabled) {
|
if (config.debug.enabled) {
|
*breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr); /* 28/05/01 CZ */
|
*breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr); /* 28/05/01 CZ */
|
*breakpoint += CheckDebugUnit(DebugStoreData,value);
|
*breakpoint += CheckDebugUnit(DebugStoreData,value);
|
}
|
}
|
|
|
if(config.dc.enabled)
|
if(config.dc.enabled)
|
dc_simulate_write(phys_memaddr, memaddr, value, 4);
|
dc_simulate_write(phys_memaddr, memaddr, value, 4);
|
else
|
else
|
setsim_mem32(phys_memaddr, memaddr, value);
|
setsim_mem32(phys_memaddr, memaddr, value);
|
|
|
if (cur_area && cur_area->log)
|
if (cur_area && cur_area->log)
|
fprintf (cur_area->log, "[%"PRIxADDR"] -> write %08"PRIx32"\n", memaddr,
|
fprintf (cur_area->log, "[%"PRIxADDR"] -> write %08"PRIx32"\n", memaddr,
|
value);
|
value);
|
}
|
}
|
|
|
/*
|
/*
|
* STATISTICS NOT OK.
|
* STATISTICS NOT OK.
|
*/
|
*/
|
void set_direct32(oraddr_t memaddr, uint32_t value, int through_mmu,
|
void set_direct32(oraddr_t memaddr, uint32_t value, int through_mmu,
|
int through_dc)
|
int through_dc)
|
{
|
{
|
oraddr_t phys_memaddr;
|
oraddr_t phys_memaddr;
|
struct dev_memarea *mem;
|
struct dev_memarea *mem;
|
|
|
if (memaddr & 3) {
|
if (memaddr & 3) {
|
PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
|
PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
|
return;
|
return;
|
}
|
}
|
|
|
phys_memaddr = memaddr;
|
phys_memaddr = memaddr;
|
|
|
if (through_mmu) {
|
if (through_mmu) {
|
/* 0 - no write access, we do not want a DPF exception do we ;)
|
/* 0 - no write access, we do not want a DPF exception do we ;)
|
*/
|
*/
|
phys_memaddr = peek_into_dtlb(memaddr, 1, through_dc);
|
phys_memaddr = peek_into_dtlb(memaddr, 1, through_dc);
|
}
|
}
|
|
|
if(through_dc)
|
if(through_dc)
|
dc_simulate_write(memaddr, memaddr, value, 4);
|
dc_simulate_write(memaddr, memaddr, value, 4);
|
else {
|
else {
|
if((mem = verify_memoryarea(phys_memaddr)))
|
if((mem = verify_memoryarea(phys_memaddr)))
|
mem->direct_ops.writefunc32(phys_memaddr & mem->size_mask, value,
|
mem->direct_ops.writefunc32(phys_memaddr & mem->size_mask, value,
|
mem->direct_ops.write_dat32);
|
mem->direct_ops.write_dat32);
|
else
|
else
|
PRINTF("ERR: 32-bit write out of memory area: %"PRIxADDR" (physical: %"
|
PRINTF("ERR: 32-bit write out of memory area: %"PRIxADDR" (physical: %"
|
PRIxADDR")\n", memaddr, phys_memaddr);
|
PRIxADDR")\n", memaddr, phys_memaddr);
|
}
|
}
|
|
|
if (cur_area && cur_area->log)
|
if (cur_area && cur_area->log)
|
fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %08"PRIx32"\n",
|
fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %08"PRIx32"\n",
|
memaddr, value);
|
memaddr, value);
|
}
|
}
|
|
|
|
|
/* Set mem, 16-bit. Big endian version. */
|
/* Set mem, 16-bit. Big endian version. */
|
|
|
void set_mem16(oraddr_t memaddr, uint16_t value, int* breakpoint)
|
void set_mem16(oraddr_t memaddr, uint16_t value, int* breakpoint)
|
{
|
{
|
oraddr_t phys_memaddr;
|
oraddr_t phys_memaddr;
|
|
|
if (config.sim.mprofile)
|
if (config.sim.mprofile)
|
mprofile (memaddr, MPROF_16 | MPROF_WRITE);
|
mprofile (memaddr, MPROF_16 | MPROF_WRITE);
|
|
|
if (memaddr & 1) {
|
if (memaddr & 1) {
|
except_handle (EXCEPT_ALIGN, memaddr);
|
except_handle (EXCEPT_ALIGN, memaddr);
|
return;
|
return;
|
}
|
}
|
|
|
phys_memaddr = dmmu_translate(memaddr, 1);;
|
phys_memaddr = dmmu_translate(memaddr, 1);;
|
/* If we produced exception don't set anything */
|
/* If we produced exception don't set anything */
|
if (except_pending)
|
if (except_pending)
|
return;
|
return;
|
|
|
if (config.debug.enabled) {
|
if (config.debug.enabled) {
|
*breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr); /* 28/05/01 CZ */
|
*breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr); /* 28/05/01 CZ */
|
*breakpoint += CheckDebugUnit(DebugStoreData,value);
|
*breakpoint += CheckDebugUnit(DebugStoreData,value);
|
}
|
}
|
|
|
if(config.dc.enabled)
|
if(config.dc.enabled)
|
dc_simulate_write(phys_memaddr, memaddr, value, 2);
|
dc_simulate_write(phys_memaddr, memaddr, value, 2);
|
else
|
else
|
setsim_mem16(phys_memaddr, memaddr, value);
|
setsim_mem16(phys_memaddr, memaddr, value);
|
|
|
if (cur_area && cur_area->log)
|
if (cur_area && cur_area->log)
|
fprintf (cur_area->log, "[%"PRIxADDR"] -> write %04"PRIx16"\n", memaddr,
|
fprintf (cur_area->log, "[%"PRIxADDR"] -> write %04"PRIx16"\n", memaddr,
|
value);
|
value);
|
}
|
}
|
|
|
/*
|
/*
|
* STATISTICS NOT OK.
|
* STATISTICS NOT OK.
|
*/
|
*/
|
void set_direct16(oraddr_t memaddr, uint16_t value, int through_mmu,
|
void set_direct16(oraddr_t memaddr, uint16_t value, int through_mmu,
|
int through_dc)
|
int through_dc)
|
{
|
{
|
oraddr_t phys_memaddr;
|
oraddr_t phys_memaddr;
|
struct dev_memarea *mem;
|
struct dev_memarea *mem;
|
|
|
if (memaddr & 1) {
|
if (memaddr & 1) {
|
PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
|
PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
|
return;
|
return;
|
}
|
}
|
|
|
phys_memaddr = memaddr;
|
phys_memaddr = memaddr;
|
|
|
if (through_mmu) {
|
if (through_mmu) {
|
/* 0 - no write access, we do not want a DPF exception do we ;)
|
/* 0 - no write access, we do not want a DPF exception do we ;)
|
*/
|
*/
|
phys_memaddr = peek_into_dtlb(memaddr, 0, through_dc);
|
phys_memaddr = peek_into_dtlb(memaddr, 0, through_dc);
|
}
|
}
|
|
|
if(through_dc)
|
if(through_dc)
|
dc_simulate_write(memaddr, memaddr, value, 2);
|
dc_simulate_write(memaddr, memaddr, value, 2);
|
else {
|
else {
|
if((mem = verify_memoryarea(phys_memaddr)))
|
if((mem = verify_memoryarea(phys_memaddr)))
|
mem->direct_ops.writefunc16(phys_memaddr & mem->size_mask, value,
|
mem->direct_ops.writefunc16(phys_memaddr & mem->size_mask, value,
|
mem->direct_ops.write_dat16);
|
mem->direct_ops.write_dat16);
|
else
|
else
|
PRINTF("ERR: 16-bit write out of memory area: %"PRIxADDR" (physical: %"
|
PRINTF("ERR: 16-bit write out of memory area: %"PRIxADDR" (physical: %"
|
PRIxADDR"\n", memaddr, phys_memaddr);
|
PRIxADDR"\n", memaddr, phys_memaddr);
|
}
|
}
|
|
|
if (cur_area && cur_area->log)
|
if (cur_area && cur_area->log)
|
fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %04"PRIx16"\n",
|
fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %04"PRIx16"\n",
|
memaddr, value);
|
memaddr, value);
|
}
|
}
|
|
|
/* Set mem, 8-bit. */
|
/* Set mem, 8-bit. */
|
void set_mem8(oraddr_t memaddr, uint8_t value, int* breakpoint)
|
void set_mem8(oraddr_t memaddr, uint8_t value, int* breakpoint)
|
{
|
{
|
oraddr_t phys_memaddr;
|
oraddr_t phys_memaddr;
|
|
|
if (config.sim.mprofile)
|
if (config.sim.mprofile)
|
mprofile (memaddr, MPROF_8 | MPROF_WRITE);
|
mprofile (memaddr, MPROF_8 | MPROF_WRITE);
|
|
|
phys_memaddr = memaddr;
|
phys_memaddr = memaddr;
|
|
|
phys_memaddr = dmmu_translate(memaddr, 1);;
|
phys_memaddr = dmmu_translate(memaddr, 1);;
|
/* If we produced exception don't set anything */
|
/* If we produced exception don't set anything */
|
if (except_pending) return;
|
if (except_pending) return;
|
|
|
if (config.debug.enabled) {
|
if (config.debug.enabled) {
|
*breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr); /* 28/05/01 CZ */
|
*breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr); /* 28/05/01 CZ */
|
*breakpoint += CheckDebugUnit(DebugStoreData,value);
|
*breakpoint += CheckDebugUnit(DebugStoreData,value);
|
}
|
}
|
|
|
if(config.dc.enabled)
|
if(config.dc.enabled)
|
dc_simulate_write(phys_memaddr, memaddr, value, 1);
|
dc_simulate_write(phys_memaddr, memaddr, value, 1);
|
else
|
else
|
setsim_mem8(phys_memaddr, memaddr, value);
|
setsim_mem8(phys_memaddr, memaddr, value);
|
|
|
if (cur_area && cur_area->log)
|
if (cur_area && cur_area->log)
|
fprintf (cur_area->log, "[%"PRIxADDR"] -> write %02"PRIx8"\n", memaddr,
|
fprintf (cur_area->log, "[%"PRIxADDR"] -> write %02"PRIx8"\n", memaddr,
|
value);
|
value);
|
}
|
}
|
|
|
/*
|
/*
|
* STATISTICS NOT OK.
|
* STATISTICS NOT OK.
|
*/
|
*/
|
void set_direct8(oraddr_t memaddr, uint8_t value, int through_mmu,
|
void set_direct8(oraddr_t memaddr, uint8_t value, int through_mmu,
|
int through_dc)
|
int through_dc)
|
{
|
{
|
oraddr_t phys_memaddr;
|
oraddr_t phys_memaddr;
|
struct dev_memarea *mem;
|
struct dev_memarea *mem;
|
|
|
phys_memaddr = memaddr;
|
phys_memaddr = memaddr;
|
|
|
if (through_mmu) {
|
if (through_mmu) {
|
/* 0 - no write access, we do not want a DPF exception do we ;)
|
/* 0 - no write access, we do not want a DPF exception do we ;)
|
*/
|
*/
|
phys_memaddr = peek_into_dtlb(memaddr, 0, through_dc);
|
phys_memaddr = peek_into_dtlb(memaddr, 0, through_dc);
|
}
|
}
|
|
|
if(through_dc)
|
if(through_dc)
|
dc_simulate_write(phys_memaddr, memaddr, value, 1);
|
dc_simulate_write(phys_memaddr, memaddr, value, 1);
|
else {
|
else {
|
if((mem = verify_memoryarea(phys_memaddr)))
|
if((mem = verify_memoryarea(phys_memaddr)))
|
mem->direct_ops.writefunc8(phys_memaddr & mem->size_mask, value,
|
mem->direct_ops.writefunc8(phys_memaddr & mem->size_mask, value,
|
mem->direct_ops.write_dat8);
|
mem->direct_ops.write_dat8);
|
else
|
else
|
PRINTF("ERR: 8-bit write out of memory area: %"PRIxADDR" (physical: %"
|
PRINTF("ERR: 8-bit write out of memory area: %"PRIxADDR" (physical: %"
|
PRIxADDR"\n", memaddr, phys_memaddr);
|
PRIxADDR"\n", memaddr, phys_memaddr);
|
}
|
}
|
|
|
if (cur_area && cur_area->log)
|
if (cur_area && cur_area->log)
|
fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %02"PRIx8"\n",
|
fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %02"PRIx8"\n",
|
memaddr, value);
|
memaddr, value);
|
}
|
}
|
|
|
|
|
/* set_program32 - same as set_direct32, but it also writes to memory that is
|
/* set_program32 - same as set_direct32, but it also writes to memory that is
|
* non-writeable to the rest of the sim. Used to do program
|
* non-writeable to the rest of the sim. Used to do program
|
* loading.
|
* loading.
|
*/
|
*/
|
void set_program32(oraddr_t memaddr, uint32_t value)
|
void set_program32(oraddr_t memaddr, uint32_t value)
|
{
|
{
|
struct dev_memarea *mem;
|
struct dev_memarea *mem;
|
|
|
if(memaddr & 3) {
|
if(memaddr & 3) {
|
PRINTF("%s(): ERR unaligned 32-bit program write\n", __FUNCTION__);
|
PRINTF("%s(): ERR unaligned 32-bit program write\n", __FUNCTION__);
|
return;
|
return;
|
}
|
}
|
|
|
if((mem = verify_memoryarea(memaddr))) {
|
if((mem = verify_memoryarea(memaddr))) {
|
mem->ops.writeprog32(memaddr & mem->size_mask, value,
|
mem->ops.writeprog32(memaddr & mem->size_mask, value,
|
mem->ops.writeprog32_dat);
|
mem->ops.writeprog32_dat);
|
} else
|
} else
|
PRINTF("ERR: 32-bit program load out of memory area: %"PRIxADDR"\n",
|
PRINTF("ERR: 32-bit program load out of memory area: %"PRIxADDR"\n",
|
memaddr);
|
memaddr);
|
}
|
}
|
|
|
/* set_program8 - same as set_direct8, but it also writes to memory that is
|
/* set_program8 - same as set_direct8, but it also writes to memory that is
|
* non-writeable to the rest of the sim. Used to do program
|
* non-writeable to the rest of the sim. Used to do program
|
* loading.
|
* loading.
|
*/
|
*/
|
void set_program8(oraddr_t memaddr, uint8_t value)
|
void set_program8(oraddr_t memaddr, uint8_t value)
|
{
|
{
|
struct dev_memarea *mem;
|
struct dev_memarea *mem;
|
|
|
if((mem = verify_memoryarea(memaddr))) {
|
if((mem = verify_memoryarea(memaddr))) {
|
mem->ops.writeprog8(memaddr & mem->size_mask, value,
|
mem->ops.writeprog8(memaddr & mem->size_mask, value,
|
mem->ops.writeprog8_dat);
|
mem->ops.writeprog8_dat);
|
} else
|
} else
|
PRINTF("ERR: 8-bit program load out of memory area: %"PRIxADDR"\n",
|
PRINTF("ERR: 8-bit program load out of memory area: %"PRIxADDR"\n",
|
memaddr);
|
memaddr);
|
}
|
}
|
|
|
void dumpmemory(oraddr_t from, oraddr_t to, int disasm, int nl)
|
void dumpmemory(oraddr_t from, oraddr_t to, int disasm, int nl)
|
{
|
{
|
oraddr_t i, j;
|
oraddr_t i, j;
|
struct label_entry *tmp;
|
struct label_entry *tmp;
|
int ilen = disasm ? 4 : 16;
|
int ilen = disasm ? 4 : 16;
|
|
|
for(i = from; i < to; i += ilen) {
|
for(i = from; i < to; i += ilen) {
|
PRINTF("%"PRIxADDR": ", i);
|
|
for (j = 0; j < ilen;) {
|
for (j = 0; j < ilen;) {
|
if (!disasm) {
|
if (!disasm) {
|
tmp = NULL;
|
tmp = NULL;
|
if (verify_memoryarea(i + j)) {
|
if (verify_memoryarea(i + j)) {
|
struct label_entry *entry;
|
struct label_entry *entry;
|
entry = get_label(i + j);
|
entry = get_label(i + j);
|
if (entry)
|
|
PRINTF("(%s)", entry->name);
|
if (entry) {
|
|
PRINTF("\n%"PRIxADDR": ", i);
|
|
PRINTF("\n<%s>:\n", entry->name);
|
|
PRINTF("%"PRIxADDR": ", i);
|
|
} else {
|
|
PRINTF("%"PRIxADDR": ", i);
|
|
}
|
|
|
PRINTF("%02"PRIx8" ", eval_direct8(i + j, 0, 0));
|
PRINTF("%02"PRIx8" ", eval_direct8(i + j, 0, 0));
|
} else PRINTF("XX ");
|
} else PRINTF("XX ");
|
j++;
|
j++;
|
} else {
|
} else {
|
uint32_t _insn = eval_direct32(i, 0, 0);
|
uint32_t _insn = eval_direct32(i, 0, 0);
|
int index = insn_decode (_insn);
|
int index = insn_decode (_insn);
|
int len = insn_len (index);
|
int len = insn_len (index);
|
|
|
tmp = NULL;
|
tmp = NULL;
|
if (verify_memoryarea(i + j)) {
|
if (verify_memoryarea(i + j)) {
|
struct label_entry *entry;
|
struct label_entry *entry;
|
entry = get_label(i + j);
|
entry = get_label(i + j);
|
if (entry)
|
|
PRINTF("(%s)", entry->name);
|
|
|
|
PRINTF(": %08"PRIx32" ", _insn);
|
if (entry) {
|
|
PRINTF("\n%"PRIxADDR": ", i);
|
|
PRINTF("<%s>:\n", entry->name);
|
|
PRINTF("%"PRIxADDR": ", i);
|
|
} else {
|
|
PRINTF("%"PRIxADDR": ", i);
|
|
}
|
|
|
|
PRINTF("%08"PRIx32" ", _insn);
|
if (index >= 0) {
|
if (index >= 0) {
|
disassemble_insn (_insn);
|
disassemble_insn (_insn);
|
PRINTF(" %s", disassembled);
|
PRINTF(" %s", disassembled);
|
} else
|
} else
|
PRINTF("<invalid>");
|
PRINTF("<invalid>");
|
} else PRINTF("XXXXXXXX");
|
} else PRINTF("XXXXXXXX");
|
j += len;
|
j += len;
|
}
|
}
|
}
|
}
|
if (nl)
|
if (nl)
|
PRINTF ("\n");
|
PRINTF ("\n");
|
}
|
}
|
}
|
}
|
|
|
/* Closes files, etc. */
|
/* Closes files, etc. */
|
|
|
void done_memory_table (void)
|
void done_memory_table (void)
|
{
|
{
|
struct dev_memarea *ptmp;
|
struct dev_memarea *ptmp;
|
|
|
/* Check list of registered devices. */
|
/* Check list of registered devices. */
|
for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
|
for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
|
if (ptmp->log)
|
if (ptmp->log)
|
fclose (ptmp->log);
|
fclose (ptmp->log);
|
}
|
}
|
}
|
}
|
|
|
/* Displays current memory configuration */
|
/* Displays current memory configuration */
|
|
|
void memory_table_status (void)
|
void memory_table_status (void)
|
{
|
{
|
struct dev_memarea *ptmp;
|
struct dev_memarea *ptmp;
|
|
|
/* Check list of registered devices. */
|
/* Check list of registered devices. */
|
for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
|
for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
|
PRINTF ("addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %"PRIx32"\n",
|
PRINTF ("addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %"PRIx32"\n",
|
ptmp->addr_mask, ptmp->addr_compare, ptmp->addr_compare | bit_mask (ptmp->size),
|
ptmp->addr_mask, ptmp->addr_compare, ptmp->addr_compare | bit_mask (ptmp->size),
|
ptmp->size);
|
ptmp->size);
|
PRINTF ("\t");
|
PRINTF ("\t");
|
if (ptmp->ops.delayr >= 0)
|
if (ptmp->ops.delayr >= 0)
|
PRINTF ("read delay = %i cycles, ", ptmp->ops.delayr);
|
PRINTF ("read delay = %i cycles, ", ptmp->ops.delayr);
|
else
|
else
|
PRINTF ("reads not possible, ");
|
PRINTF ("reads not possible, ");
|
|
|
if (ptmp->ops.delayw >= 0)
|
if (ptmp->ops.delayw >= 0)
|
PRINTF ("write delay = %i cycles", ptmp->ops.delayw);
|
PRINTF ("write delay = %i cycles", ptmp->ops.delayw);
|
else
|
else
|
PRINTF ("writes not possible");
|
PRINTF ("writes not possible");
|
|
|
if (ptmp->log)
|
if (ptmp->log)
|
PRINTF (", (logged)\n");
|
PRINTF (", (logged)\n");
|
else
|
else
|
PRINTF ("\n");
|
PRINTF ("\n");
|
}
|
}
|
}
|
}
|
|
|
/* Outputs time in pretty form to dest string */
|
/* Outputs time in pretty form to dest string */
|
|
|
char *generate_time_pretty (char *dest, long time_ps)
|
char *generate_time_pretty (char *dest, long time_ps)
|
{
|
{
|
int exp3 = 0;
|
int exp3 = 0;
|
if (time_ps) {
|
if (time_ps) {
|
while ((time_ps % 1000) == 0) {
|
while ((time_ps % 1000) == 0) {
|
time_ps /= 1000;
|
time_ps /= 1000;
|
exp3++;
|
exp3++;
|
}
|
}
|
}
|
}
|
sprintf (dest, "%li%cs", time_ps, "pnum"[exp3]);
|
sprintf (dest, "%li%cs", time_ps, "pnum"[exp3]);
|
return dest;
|
return dest;
|
}
|
}
|
|
|
