/* arch.h -- OR1K architecture specific macros
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/* arch.h -- OR1K architecture specific macros
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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#define LINK_REG "r9"
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#define LINK_REG "r9"
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#define LINK_REGNO (9)
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#define LINK_REGNO (9)
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#define STACK_REG "r1"
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#define STACK_REG "r1"
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#define STACK_REGNO (1)
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#define STACK_REGNO (1)
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#define FRAME_REG "r2"
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#define FRAME_REG "r2"
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#define FRAME_REGNO (2)
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#define FRAME_REGNO (2)
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#define RETURNV_REG "r11"
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#define RETURNV_REG "r11"
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#define RETURNV_REGNO (11)
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#define RETURNV_REGNO (11)
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/* Basic types for openrisc */
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/* Basic types for openrisc */
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typedef uint32_t oraddr_t; /* Address as addressed by openrisc */
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typedef uint32_t oraddr_t; /* Address as addressed by openrisc */
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typedef uint32_t uorreg_t; /* An unsigned register of openrisc */
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typedef uint32_t uorreg_t; /* An unsigned register of openrisc */
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typedef int32_t orreg_t; /* A signed register of openrisc */
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typedef int32_t orreg_t; /* A signed register of openrisc */
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#define PRIxADDR "08" PRIx32 /* How to print an openrisc address in hex */
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#define PRIxADDR "08" PRIx32 /* How to print an openrisc address in hex */
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#define PRIxREG "08" PRIx32 /* How to print an openrisc register in hex */
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#define PRIxREG "08" PRIx32 /* How to print an openrisc register in hex */
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#define PRIdREG PRId32 /* How to print an openrisc register in decimals */
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#define PRIdREG PRId32 /* How to print an openrisc register in decimals */
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#define ADDR_C(c) UINT32_C(c)
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#define ADDR_C(c) UINT32_C(c)
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#define REG_C(c) UINT32_C(c)
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#define REG_C(c) UINT32_C(c)
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/* Should args be passed on stack for simprintf
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/* Should args be passed on stack for simprintf
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*
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*
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* FIXME: do not enable this since it causes problems
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* FIXME: do not enable this since it causes problems
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* in some cases (an example beeing cbasic test
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* in some cases (an example beeing cbasic test
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* from orp testbench). the problems is in
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* from orp testbench). the problems is in
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*
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*
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* or1k/support/simprintf.c
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* or1k/support/simprintf.c
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*
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*
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* #if STACK_ARGS
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* #if STACK_ARGS
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* arg = eval_mem32(argaddr,&breakpoint);
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* arg = eval_mem32(argaddr,&breakpoint);
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* argaddr += 4;
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* argaddr += 4;
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* #else
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* #else
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* sprintf(regstr, "r%u", ++argaddr);
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* sprintf(regstr, "r%u", ++argaddr);
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* arg = evalsim_reg(atoi(regstr));
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* arg = evalsim_reg(atoi(regstr));
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* #endif
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* #endif
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*
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*
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* the access to memory should be without any
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* the access to memory should be without any
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* checks (ie not like or32 application accessed it)
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* checks (ie not like or32 application accessed it)
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*
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*
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*/
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*/
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#define STACK_ARGS 0
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#define STACK_ARGS 0
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