/* 16450.h -- Definition of types and structures for 8250/16450 serial UART
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/* 16450.h -- Definition of types and structures for 8250/16450 serial UART
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Copyright (C) 2000 Damjan Lampret, lampret@opencores.org
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Copyright (C) 2000 Damjan Lampret, lampret@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* Prototypes */
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/* Prototypes */
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void uart_reset();
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void uart_reset();
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void uart_status();
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void uart_status();
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/* Definitions */
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/* Definitions */
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#define UART_ADDR_SPACE (8) /* UART memory address space size in bytes */
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#define UART_ADDR_SPACE (8) /* UART memory address space size in bytes */
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#define UART_MAX_FIFO_LEN (16) /* rx FIFO for uart 16550 */
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#define UART_MAX_FIFO_LEN (16) /* rx FIFO for uart 16550 */
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#define MAX_SKEW (1) /* max. clock skew in subclocks */
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#define MAX_SKEW (1) /* max. clock skew in subclocks */
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#define UART_VAPI_BUF_LEN 128 /* Size of VAPI command buffer - VAPI should not send more
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#define UART_VAPI_BUF_LEN 128 /* Size of VAPI command buffer - VAPI should not send more
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that this amout of char before requesting something back */
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that this amout of char before requesting something back */
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#define UART_CLOCK_DIVIDER 16 /* Uart clock divider */
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#define UART_CLOCK_DIVIDER 16 /* Uart clock divider */
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#define UART_FGETC_SLOWDOWN 100 /* fgetc slowdown factor */
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#define UART_FGETC_SLOWDOWN 100 /* fgetc slowdown factor */
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/* Registers */
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/* Registers */
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struct dev_16450 {
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struct dev_16450 {
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struct {
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struct {
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uint8_t txbuf[UART_MAX_FIFO_LEN];
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uint8_t txbuf[UART_MAX_FIFO_LEN];
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uint16_t rxbuf[UART_MAX_FIFO_LEN]; /* Upper 8-bits is the LCR modifier */
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uint16_t rxbuf[UART_MAX_FIFO_LEN]; /* Upper 8-bits is the LCR modifier */
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uint8_t dll;
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uint8_t dll;
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uint8_t dlh;
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uint8_t dlh;
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uint8_t ier;
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uint8_t ier;
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uint8_t iir;
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uint8_t iir;
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uint8_t fcr;
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uint8_t fcr;
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uint8_t lcr;
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uint8_t lcr;
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uint8_t mcr;
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uint8_t mcr;
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uint8_t lsr;
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uint8_t lsr;
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uint8_t msr;
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uint8_t msr;
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uint8_t scr;
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uint8_t scr;
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} regs; /* Visible registers */
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} regs; /* Visible registers */
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struct {
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struct {
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uint8_t txser; /* Character just sending */
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uint8_t txser; /* Character just sending */
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uint16_t rxser; /* Character just receiving */
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uint16_t rxser; /* Character just receiving */
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uint8_t loopback;
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uint8_t loopback;
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} iregs; /* Internal registers */
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} iregs; /* Internal registers */
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struct {
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struct {
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int txbuf_head;
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int txbuf_head;
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int txbuf_tail;
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int txbuf_tail;
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int rxbuf_head;
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int rxbuf_head;
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int rxbuf_tail;
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int rxbuf_tail;
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unsigned int txbuf_full;
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unsigned int txbuf_full;
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unsigned int rxbuf_full;
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unsigned int rxbuf_full;
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int receiveing; /* Receiveing a char */
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int receiveing; /* Receiveing a char */
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int recv_break; /* Receiveing a break */
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int recv_break; /* Receiveing a break */
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int ints; /* Which interrupts are pending */
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int ints; /* Which interrupts are pending */
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} istat; /* Internal status */
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} istat; /* Internal status */
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/* Clocks per char */
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/* Clocks per char */
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unsigned long char_clks;
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unsigned long char_clks;
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/* VAPI internal registers */
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/* VAPI internal registers */
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struct {
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struct {
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unsigned long char_clks;
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unsigned long char_clks;
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uint8_t dll, dlh;
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uint8_t dll, dlh;
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uint8_t lcr;
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uint8_t lcr;
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int skew;
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int skew;
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} vapi;
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} vapi;
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/* Required by VAPI - circular buffer */
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/* Required by VAPI - circular buffer */
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unsigned long vapi_buf[UART_VAPI_BUF_LEN]; /* Buffer to store incoming characters to,
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unsigned long vapi_buf[UART_VAPI_BUF_LEN]; /* Buffer to store incoming characters to,
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since we cannot handle them so fast - we
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since we cannot handle them so fast - we
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are serial */
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are serial */
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int vapi_buf_head_ptr; /* Where we write to */
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int vapi_buf_head_ptr; /* Where we write to */
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int vapi_buf_tail_ptr; /* Where we read from */
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int vapi_buf_tail_ptr; /* Where we read from */
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/* Length of FIFO, 16 for 16550, 1 for 16450 */
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/* Length of FIFO, 16 for 16550, 1 for 16450 */
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int fifo_len;
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int fifo_len;
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struct channel *channel;
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struct channel *channel;
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/* Configuration */
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/* Configuration */
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int enabled;
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int enabled;
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int jitter;
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int jitter;
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oraddr_t baseaddr;
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oraddr_t baseaddr;
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int irq;
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int irq;
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unsigned long vapi_id;
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unsigned long vapi_id;
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int uart16550;
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int uart16550;
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char *channel_str;
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char *channel_str;
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};
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};
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/*
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/*
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* Addresses of visible registers
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* Addresses of visible registers
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*
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*
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*/
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*/
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#define UART_RXBUF 0 /* R: Rx buffer, DLAB=0 */
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#define UART_RXBUF 0 /* R: Rx buffer, DLAB=0 */
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#define UART_TXBUF 0 /* W: Tx buffer, DLAB=0 */
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#define UART_TXBUF 0 /* W: Tx buffer, DLAB=0 */
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#define UART_DLL 0 /* R/W: Divisor Latch Low, DLAB=1 */
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#define UART_DLL 0 /* R/W: Divisor Latch Low, DLAB=1 */
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#define UART_DLH 1 /* R/W: Divisor Latch High, DLAB=1 */
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#define UART_DLH 1 /* R/W: Divisor Latch High, DLAB=1 */
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#define UART_IER 1 /* R/W: Interrupt Enable Register */
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#define UART_IER 1 /* R/W: Interrupt Enable Register */
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#define UART_IIR 2 /* R: Interrupt ID Register */
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#define UART_IIR 2 /* R: Interrupt ID Register */
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#define UART_FCR 2 /* W: FIFO Control Register */
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#define UART_FCR 2 /* W: FIFO Control Register */
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#define UART_LCR 3 /* R/W: Line Control Register */
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#define UART_LCR 3 /* R/W: Line Control Register */
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#define UART_MCR 4 /* W: Modem Control Register */
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#define UART_MCR 4 /* W: Modem Control Register */
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#define UART_LSR 5 /* R: Line Status Register */
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#define UART_LSR 5 /* R: Line Status Register */
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#define UART_MSR 6 /* R: Modem Status Register */
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#define UART_MSR 6 /* R: Modem Status Register */
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#define UART_SCR 7 /* R/W: Scratch Register */
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#define UART_SCR 7 /* R/W: Scratch Register */
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/*
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/*
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* R/W masks for valid bits in 8250/16450 (mask out 16550 and later bits)
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* R/W masks for valid bits in 8250/16450 (mask out 16550 and later bits)
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*
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*
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*/
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*/
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#define UART_VALID_LCR 0xff
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#define UART_VALID_LCR 0xff
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#define UART_VALID_LSR 0xff
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#define UART_VALID_LSR 0xff
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#define UART_VALID_IIR 0x0f
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#define UART_VALID_IIR 0x0f
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#define UART_VALID_FCR 0xc0
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#define UART_VALID_FCR 0xc0
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#define UART_VALID_IER 0x0f
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#define UART_VALID_IER 0x0f
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#define UART_VALID_MCR 0x1f
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#define UART_VALID_MCR 0x1f
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#define UART_VALID_MSR 0xff
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#define UART_VALID_MSR 0xff
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/*
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/*
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* Bit definitions for the Line Control Register
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* Bit definitions for the Line Control Register
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*
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*
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*/
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*/
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#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
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#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
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#define UART_LCR_SBC 0x40 /* Set break control */
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#define UART_LCR_SBC 0x40 /* Set break control */
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#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
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#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
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#define UART_LCR_EPAR 0x10 /* Even parity select */
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#define UART_LCR_EPAR 0x10 /* Even parity select */
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#define UART_LCR_PARITY 0x08 /* Parity Enable */
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#define UART_LCR_PARITY 0x08 /* Parity Enable */
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#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
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#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
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#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
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#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
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#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
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#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
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#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
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#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
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#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
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#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
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#define UART_LCR_RESET 0x03
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#define UART_LCR_RESET 0x03
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/*
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/*
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* Bit definitions for the Line Status Register
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* Bit definitions for the Line Status Register
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*/
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*/
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#define UART_LSR_RXERR 0x80 /* Error in rx fifo */
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#define UART_LSR_RXERR 0x80 /* Error in rx fifo */
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#define UART_LSR_TXSERE 0x40 /* Transmitter serial register empty */
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#define UART_LSR_TXSERE 0x40 /* Transmitter serial register empty */
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#define UART_LSR_TXBUFE 0x20 /* Transmitter buffer register empty */
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#define UART_LSR_TXBUFE 0x20 /* Transmitter buffer register empty */
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#define UART_LSR_BREAK 0x10 /* Break interrupt indicator */
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#define UART_LSR_BREAK 0x10 /* Break interrupt indicator */
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#define UART_LSR_FRAME 0x08 /* Frame error indicator */
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#define UART_LSR_FRAME 0x08 /* Frame error indicator */
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#define UART_LSR_PARITY 0x04 /* Parity error indicator */
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#define UART_LSR_PARITY 0x04 /* Parity error indicator */
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#define UART_LSR_OVRRUN 0x02 /* Overrun error indicator */
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#define UART_LSR_OVRRUN 0x02 /* Overrun error indicator */
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#define UART_LSR_RDRDY 0x01 /* Receiver data ready */
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#define UART_LSR_RDRDY 0x01 /* Receiver data ready */
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/*
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/*
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* Bit definitions for the Interrupt Identification Register
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* Bit definitions for the Interrupt Identification Register
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*/
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*/
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#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
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#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
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#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
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#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
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#define UART_IIR_MSI 0x00 /* Modem status interrupt (Low priority) */
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#define UART_IIR_MSI 0x00 /* Modem status interrupt (Low priority) */
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#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
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#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
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#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
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#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
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#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt (High p.) */
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#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt (High p.) */
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#define UART_IIR_CTI 0x0c /* Character timeout */
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#define UART_IIR_CTI 0x0c /* Character timeout */
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/*
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/*
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* Bit Definitions for the FIFO Control Register
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* Bit Definitions for the FIFO Control Register
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*/
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*/
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#define UART_FCR_FIE 0x01 /* FIFO enable */
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#define UART_FCR_FIE 0x01 /* FIFO enable */
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#define UART_FCR_RRXFI 0x02 /* Reset rx FIFO */
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#define UART_FCR_RRXFI 0x02 /* Reset rx FIFO */
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#define UART_FCR_RTXFI 0x04 /* Reset tx FIFO */
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#define UART_FCR_RTXFI 0x04 /* Reset tx FIFO */
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#define UART_FIFO_TRIGGER(x) /* Trigger values for indexes 0..3 */\
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#define UART_FIFO_TRIGGER(x) /* Trigger values for indexes 0..3 */\
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((x) == 0 ? 1\
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((x) == 0 ? 1\
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:(x) == 1 ? 4\
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:(x) == 1 ? 4\
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:(x) == 2 ? 8\
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:(x) == 2 ? 8\
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:(x) == 3 ? 14 : 0)
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:(x) == 3 ? 14 : 0)
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/*
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/*
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* Bit definitions for the Interrupt Enable Register
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* Bit definitions for the Interrupt Enable Register
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*/
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*/
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#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
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#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
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#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
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#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
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#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
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#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
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#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
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#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
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/*
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/*
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* Bit definitions for the Modem Control Register
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* Bit definitions for the Modem Control Register
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*/
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*/
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#define UART_MCR_LOOP 0x10 /* Enable loopback mode */
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#define UART_MCR_LOOP 0x10 /* Enable loopback mode */
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#define UART_MCR_AUX2 0x08 /* Auxilary 2 */
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#define UART_MCR_AUX2 0x08 /* Auxilary 2 */
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#define UART_MCR_AUX1 0x04 /* Auxilary 1 */
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#define UART_MCR_AUX1 0x04 /* Auxilary 1 */
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#define UART_MCR_RTS 0x02 /* Force RTS */
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#define UART_MCR_RTS 0x02 /* Force RTS */
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#define UART_MCR_DTR 0x01 /* Force DTR */
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#define UART_MCR_DTR 0x01 /* Force DTR */
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/*
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/*
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* Bit definitions for the Modem Status Register
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* Bit definitions for the Modem Status Register
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*/
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*/
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#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
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#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
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#define UART_MSR_RI 0x40 /* Ring Indicator */
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#define UART_MSR_RI 0x40 /* Ring Indicator */
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#define UART_MSR_DSR 0x20 /* Data Set Ready */
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#define UART_MSR_DSR 0x20 /* Data Set Ready */
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#define UART_MSR_CTS 0x10 /* Clear to Send */
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#define UART_MSR_CTS 0x10 /* Clear to Send */
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#define UART_MSR_DDCD 0x08 /* Delta DCD */
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#define UART_MSR_DDCD 0x08 /* Delta DCD */
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#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
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#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
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#define UART_MSR_DDSR 0x02 /* Delta DSR */
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#define UART_MSR_DDSR 0x02 /* Delta DSR */
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#define UART_MSR_DCTS 0x01 /* Delta CTS */
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#define UART_MSR_DCTS 0x01 /* Delta CTS */
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/*
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/*
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* Various definitions
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* Various definitions
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*/
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*/
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#define UART_BREAK_COUNT (1) /* # of chars to count when performing break */
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#define UART_BREAK_COUNT (1) /* # of chars to count when performing break */
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#define UART_CHAR_TIMEOUT (4) /* # of chars to count when performing timeout int. */
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#define UART_CHAR_TIMEOUT (4) /* # of chars to count when performing timeout int. */
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