/* dma.c -- Simulation of DMA
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/* dma.c -- Simulation of DMA
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Copyright (C) 2001 by Erez Volk, erez@opencores.org
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Copyright (C) 2001 by Erez Volk, erez@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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*/
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/*
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/*
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* This simulation of the DMA core is not meant to be full.
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* This simulation of the DMA core is not meant to be full.
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* It is written only to allow simulating the Ethernet core.
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* It is written only to allow simulating the Ethernet core.
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* Of course, if anyone feels like perfecting it, feel free...
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* Of course, if anyone feels like perfecting it, feel free...
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*/
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*/
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#include "dma.h"
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#include "dma.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "pic.h"
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#include "pic.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "fields.h"
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#include "fields.h"
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/* The representation of the DMA controllers */
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/* The representation of the DMA controllers */
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static struct dma_controller dmas[MAX_DMAS];
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static struct dma_controller dmas[MAX_DMAS];
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static unsigned long dma_read32( unsigned long addr );
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static unsigned long dma_read32( unsigned long addr );
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static void dma_write32( unsigned long addr, unsigned long value );
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static void dma_write32( unsigned long addr, unsigned long value );
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static unsigned long dma_read_ch_csr( struct dma_channel *channel );
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static unsigned long dma_read_ch_csr( struct dma_channel *channel );
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static void dma_write_ch_csr( struct dma_channel *channel, unsigned long value );
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static void dma_write_ch_csr( struct dma_channel *channel, unsigned long value );
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static void dma_controller_clock( struct dma_controller *dma );
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static void dma_controller_clock( struct dma_controller *dma );
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static void dma_load_descriptor( struct dma_channel *channel );
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static void dma_load_descriptor( struct dma_channel *channel );
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static void dma_init_transfer( struct dma_channel *channel );
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static void dma_init_transfer( struct dma_channel *channel );
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static void dma_channel_terminate_transfer( struct dma_channel *channel, int generate_interrupt );
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static void dma_channel_terminate_transfer( struct dma_channel *channel, int generate_interrupt );
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static void masked_increase( unsigned long *value, unsigned long mask );
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static void masked_increase( unsigned long *value, unsigned long mask );
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#define CHANNEL_ND_I(ch) (TEST_FLAG(ch->regs.csr,DMA_CH_CSR,MODE) && TEST_FLAG(ch->regs.csr,DMA_CH_CSR,USE_ED) && ch->dma_nd_i)
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#define CHANNEL_ND_I(ch) (TEST_FLAG(ch->regs.csr,DMA_CH_CSR,MODE) && TEST_FLAG(ch->regs.csr,DMA_CH_CSR,USE_ED) && ch->dma_nd_i)
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/* Reset. Initializes all registers to default and places devices in memory address space. */
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/* Reset. Initializes all registers to default and places devices in memory address space. */
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void dma_reset()
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void dma_reset()
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{
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{
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unsigned i;
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unsigned i;
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memset( dmas, 0, sizeof(dmas) );
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memset( dmas, 0, sizeof(dmas) );
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for ( i = 0; i < config.ndmas; ++ i ) {
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for ( i = 0; i < config.ndmas; ++ i ) {
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struct dma_controller *dma = &(dmas[i]);
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struct dma_controller *dma = &(dmas[i]);
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unsigned channel_number;
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unsigned channel_number;
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dma->baseaddr = config.dmas[i].baseaddr;
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dma->baseaddr = config.dmas[i].baseaddr;
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dma->irq = config.dmas[i].irq;
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dma->irq = config.dmas[i].irq;
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for ( channel_number = 0; channel_number < DMA_NUM_CHANNELS; ++ channel_number ) {
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for ( channel_number = 0; channel_number < DMA_NUM_CHANNELS; ++ channel_number ) {
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dma->ch[channel_number].controller = &(dmas[i]);
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dma->ch[channel_number].controller = &(dmas[i]);
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dma->ch[channel_number].channel_number = channel_number;
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dma->ch[channel_number].channel_number = channel_number;
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dma->ch[channel_number].channel_mask = 1LU << channel_number;
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dma->ch[channel_number].channel_mask = 1LU << channel_number;
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dma->ch[channel_number].regs.am0 = dma->ch[channel_number].regs.am1 = 0xFFFFFFFC;
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dma->ch[channel_number].regs.am0 = dma->ch[channel_number].regs.am1 = 0xFFFFFFFC;
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}
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}
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if ( dma->baseaddr != 0 )
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if ( dma->baseaddr != 0 )
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register_memoryarea( dma->baseaddr, DMA_ADDR_SPACE, 4, dma_read32, dma_write32);
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register_memoryarea( dma->baseaddr, DMA_ADDR_SPACE, 4, 0, dma_read32, dma_write32);
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}
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}
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}
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}
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/* Print register values on stdout */
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/* Print register values on stdout */
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void dma_status( void )
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void dma_status( void )
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{
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{
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unsigned i, j;
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unsigned i, j;
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for ( i = 0; i < config.ndmas; ++ i ) {
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for ( i = 0; i < config.ndmas; ++ i ) {
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struct dma_controller *dma = &(dmas[i]);
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struct dma_controller *dma = &(dmas[i]);
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if ( dma->baseaddr == 0 )
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if ( dma->baseaddr == 0 )
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continue;
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continue;
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printf( "\nDMA controller %u at 0x%08X:\n", i, dma->baseaddr );
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printf( "\nDMA controller %u at 0x%08X:\n", i, dma->baseaddr );
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printf( "CSR : 0x%08lX\n", dma->regs.csr );
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printf( "CSR : 0x%08lX\n", dma->regs.csr );
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printf( "INT_MSK_A : 0x%08lX\n", dma->regs.int_msk_a );
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printf( "INT_MSK_A : 0x%08lX\n", dma->regs.int_msk_a );
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printf( "INT_MSK_B : 0x%08lX\n", dma->regs.int_msk_b );
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printf( "INT_MSK_B : 0x%08lX\n", dma->regs.int_msk_b );
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printf( "INT_SRC_A : 0x%08lX\n", dma->regs.int_src_a );
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printf( "INT_SRC_A : 0x%08lX\n", dma->regs.int_src_a );
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printf( "INT_SRC_B : 0x%08lX\n", dma->regs.int_src_b );
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printf( "INT_SRC_B : 0x%08lX\n", dma->regs.int_src_b );
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for ( j = 0; j < DMA_NUM_CHANNELS; ++ j ) {
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for ( j = 0; j < DMA_NUM_CHANNELS; ++ j ) {
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struct dma_channel *channel = &(dma->ch[j]);
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struct dma_channel *channel = &(dma->ch[j]);
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if ( !channel->referenced )
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if ( !channel->referenced )
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continue;
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continue;
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printf( "CH%u_CSR : 0x%08lX\n", j, channel->regs.csr );
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printf( "CH%u_CSR : 0x%08lX\n", j, channel->regs.csr );
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printf( "CH%u_SZ : 0x%08lX\n", j, channel->regs.sz );
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printf( "CH%u_SZ : 0x%08lX\n", j, channel->regs.sz );
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printf( "CH%u_A0 : 0x%08lX\n", j, channel->regs.a0 );
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printf( "CH%u_A0 : 0x%08lX\n", j, channel->regs.a0 );
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printf( "CH%u_AM0 : 0x%08lX\n", j, channel->regs.am0 );
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printf( "CH%u_AM0 : 0x%08lX\n", j, channel->regs.am0 );
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printf( "CH%u_A1 : 0x%08lX\n", j, channel->regs.a1 );
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printf( "CH%u_A1 : 0x%08lX\n", j, channel->regs.a1 );
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printf( "CH%u_AM1 : 0x%08lX\n", j, channel->regs.am1 );
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printf( "CH%u_AM1 : 0x%08lX\n", j, channel->regs.am1 );
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printf( "CH%u_DESC : 0x%08lX\n", j, channel->regs.desc );
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printf( "CH%u_DESC : 0x%08lX\n", j, channel->regs.desc );
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printf( "CH%u_SWPTR : 0x%08lX\n", j, channel->regs.swptr );
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printf( "CH%u_SWPTR : 0x%08lX\n", j, channel->regs.swptr );
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}
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}
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}
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}
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}
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}
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/* Read a register */
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/* Read a register */
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unsigned long dma_read32( unsigned long addr )
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unsigned long dma_read32( unsigned long addr )
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{
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{
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unsigned i;
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unsigned i;
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struct dma_controller *dma = NULL;
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struct dma_controller *dma = NULL;
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for ( i = 0; i < MAX_DMAS && dma == NULL; ++ i ) {
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for ( i = 0; i < MAX_DMAS && dma == NULL; ++ i ) {
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if ( addr >= dmas[i].baseaddr && addr < dmas[i].baseaddr + DMA_ADDR_SPACE )
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if ( addr >= dmas[i].baseaddr && addr < dmas[i].baseaddr + DMA_ADDR_SPACE )
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dma = &(dmas[i]);
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dma = &(dmas[i]);
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}
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}
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/* verify we found a controller */
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/* verify we found a controller */
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if ( dma == NULL ) {
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if ( dma == NULL ) {
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fprintf( stderr, "dma_read32( 0x%08lX ): Out of range\n", addr );
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fprintf( stderr, "dma_read32( 0x%08lX ): Out of range\n", addr );
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runtime.sim.cont_run = 0;
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runtime.sim.cont_run = 0;
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return 0;
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return 0;
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}
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}
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addr -= dma->baseaddr;
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addr -= dma->baseaddr;
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if ( addr % 4 != 0 ) {
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if ( addr % 4 != 0 ) {
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fprintf( stderr, "dma_read32( 0x%08lX ): Not register-aligned\n", addr + dma->baseaddr );
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fprintf( stderr, "dma_read32( 0x%08lX ): Not register-aligned\n", addr + dma->baseaddr );
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runtime.sim.cont_run = 0;
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runtime.sim.cont_run = 0;
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return 0;
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return 0;
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}
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}
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if ( addr < DMA_CH_BASE ) {
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if ( addr < DMA_CH_BASE ) {
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/* case of global (not per-channel) registers */
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/* case of global (not per-channel) registers */
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switch( addr ) {
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switch( addr ) {
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case DMA_CSR: return dma->regs.csr;
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case DMA_CSR: return dma->regs.csr;
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case DMA_INT_MSK_A: return dma->regs.int_msk_a;
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case DMA_INT_MSK_A: return dma->regs.int_msk_a;
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case DMA_INT_MSK_B: return dma->regs.int_msk_b;
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case DMA_INT_MSK_B: return dma->regs.int_msk_b;
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case DMA_INT_SRC_A: return dma->regs.int_src_a;
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case DMA_INT_SRC_A: return dma->regs.int_src_a;
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case DMA_INT_SRC_B: return dma->regs.int_src_b;
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case DMA_INT_SRC_B: return dma->regs.int_src_b;
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default:
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default:
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fprintf( stderr, "dma_read32( 0x%08lX ): Illegal register\n", addr + dma->baseaddr );
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fprintf( stderr, "dma_read32( 0x%08lX ): Illegal register\n", addr + dma->baseaddr );
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runtime.sim.cont_run = 0;
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runtime.sim.cont_run = 0;
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return 0;
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return 0;
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}
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}
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} else {
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} else {
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/* case of per-channel registers */
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/* case of per-channel registers */
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unsigned chno = (addr - DMA_CH_BASE) / DMA_CH_SIZE;
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unsigned chno = (addr - DMA_CH_BASE) / DMA_CH_SIZE;
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addr = (addr - DMA_CH_BASE) % DMA_CH_SIZE;
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addr = (addr - DMA_CH_BASE) % DMA_CH_SIZE;
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switch( addr ) {
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switch( addr ) {
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case DMA_CH_CSR: return dma_read_ch_csr( &(dma->ch[chno]) );
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case DMA_CH_CSR: return dma_read_ch_csr( &(dma->ch[chno]) );
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case DMA_CH_SZ: return dma->ch[chno].regs.sz;
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case DMA_CH_SZ: return dma->ch[chno].regs.sz;
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case DMA_CH_A0: return dma->ch[chno].regs.a0;
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case DMA_CH_A0: return dma->ch[chno].regs.a0;
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case DMA_CH_AM0: return dma->ch[chno].regs.am0;
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case DMA_CH_AM0: return dma->ch[chno].regs.am0;
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case DMA_CH_A1: return dma->ch[chno].regs.a1;
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case DMA_CH_A1: return dma->ch[chno].regs.a1;
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case DMA_CH_AM1: return dma->ch[chno].regs.am1;
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case DMA_CH_AM1: return dma->ch[chno].regs.am1;
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case DMA_CH_DESC: return dma->ch[chno].regs.desc;
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case DMA_CH_DESC: return dma->ch[chno].regs.desc;
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case DMA_CH_SWPTR: return dma->ch[chno].regs.swptr;
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case DMA_CH_SWPTR: return dma->ch[chno].regs.swptr;
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}
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}
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}
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}
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}
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}
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/* Handle read from a channel CSR */
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/* Handle read from a channel CSR */
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unsigned long dma_read_ch_csr( struct dma_channel *channel )
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unsigned long dma_read_ch_csr( struct dma_channel *channel )
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{
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{
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unsigned long result = channel->regs.csr;
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unsigned long result = channel->regs.csr;
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/* before returning, clear all relevant bits */
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/* before returning, clear all relevant bits */
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CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, INT_CHUNK_DONE );
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CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, INT_CHUNK_DONE );
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CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, INT_DONE );
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CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, INT_DONE );
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CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, INT_ERR );
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CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, INT_ERR );
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CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, ERR );
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CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, ERR );
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return result;
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return result;
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}
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}
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/* Write a register */
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/* Write a register */
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void dma_write32( unsigned long addr, unsigned long value )
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void dma_write32( unsigned long addr, unsigned long value )
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{
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{
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unsigned i;
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unsigned i;
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struct dma_controller *dma = NULL;
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struct dma_controller *dma = NULL;
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/* Find which controller this is */
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/* Find which controller this is */
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for ( i = 0; i < MAX_DMAS && dma == NULL; ++ i ) {
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for ( i = 0; i < MAX_DMAS && dma == NULL; ++ i ) {
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if ( (addr >= dmas[i].baseaddr) && (addr < dmas[i].baseaddr + DMA_ADDR_SPACE) )
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if ( (addr >= dmas[i].baseaddr) && (addr < dmas[i].baseaddr + DMA_ADDR_SPACE) )
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dma = &(dmas[i]);
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dma = &(dmas[i]);
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}
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}
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/* verify we found a controller */
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/* verify we found a controller */
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if ( dma == NULL ) {
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if ( dma == NULL ) {
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fprintf( stderr, "dma_write32( 0x%08lX ): Out of range\n", addr );
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fprintf( stderr, "dma_write32( 0x%08lX ): Out of range\n", addr );
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runtime.sim.cont_run = 0;
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runtime.sim.cont_run = 0;
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return;
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return;
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}
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}
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addr -= dma->baseaddr;
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addr -= dma->baseaddr;
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if ( addr % 4 != 0 ) {
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if ( addr % 4 != 0 ) {
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fprintf( stderr, "dma_write32( 0x%08lX, 0x%08lX ): Not register-aligned\n", addr + dma->baseaddr, value );
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fprintf( stderr, "dma_write32( 0x%08lX, 0x%08lX ): Not register-aligned\n", addr + dma->baseaddr, value );
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runtime.sim.cont_run = 0;
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runtime.sim.cont_run = 0;
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return;
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return;
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}
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}
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/* case of global (not per-channel) registers */
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/* case of global (not per-channel) registers */
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if ( addr < DMA_CH_BASE ) {
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if ( addr < DMA_CH_BASE ) {
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switch( addr ) {
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switch( addr ) {
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case DMA_CSR:
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case DMA_CSR:
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if ( TEST_FLAG( value, DMA_CSR, PAUSE ) )
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if ( TEST_FLAG( value, DMA_CSR, PAUSE ) )
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fprintf( stderr, "dma: PAUSE not implemented\n" );
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fprintf( stderr, "dma: PAUSE not implemented\n" );
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break;
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break;
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case DMA_INT_MSK_A: dma->regs.int_msk_a = value; break;
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case DMA_INT_MSK_A: dma->regs.int_msk_a = value; break;
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case DMA_INT_MSK_B: dma->regs.int_msk_b = value; break;
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case DMA_INT_MSK_B: dma->regs.int_msk_b = value; break;
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case DMA_INT_SRC_A: dma->regs.int_src_a = value; break;
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case DMA_INT_SRC_A: dma->regs.int_src_a = value; break;
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case DMA_INT_SRC_B: dma->regs.int_src_b = value; break;
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case DMA_INT_SRC_B: dma->regs.int_src_b = value; break;
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default:
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default:
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fprintf( stderr, "dma_write32( 0x%08lX ): Illegal register\n", addr + dma->baseaddr );
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fprintf( stderr, "dma_write32( 0x%08lX ): Illegal register\n", addr + dma->baseaddr );
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runtime.sim.cont_run = 0;
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runtime.sim.cont_run = 0;
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return;
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return;
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}
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}
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} else {
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} else {
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/* case of per-channel registers */
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/* case of per-channel registers */
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unsigned chno = (addr - DMA_CH_BASE) / DMA_CH_SIZE;
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unsigned chno = (addr - DMA_CH_BASE) / DMA_CH_SIZE;
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struct dma_channel *channel = &(dma->ch[chno]);
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struct dma_channel *channel = &(dma->ch[chno]);
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channel->referenced = 1;
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channel->referenced = 1;
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addr = (addr - DMA_CH_BASE) % DMA_CH_SIZE;
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addr = (addr - DMA_CH_BASE) % DMA_CH_SIZE;
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switch( addr ) {
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switch( addr ) {
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case DMA_CSR: dma_write_ch_csr( &(dma->ch[chno]), value ); break;
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case DMA_CSR: dma_write_ch_csr( &(dma->ch[chno]), value ); break;
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case DMA_CH_SZ: channel->regs.sz = value; break;
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case DMA_CH_SZ: channel->regs.sz = value; break;
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case DMA_CH_A0: channel->regs.a0 = value; break;
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case DMA_CH_A0: channel->regs.a0 = value; break;
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case DMA_CH_AM0: channel->regs.am0 = value; break;
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case DMA_CH_AM0: channel->regs.am0 = value; break;
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case DMA_CH_A1: channel->regs.a1 = value; break;
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case DMA_CH_A1: channel->regs.a1 = value; break;
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case DMA_CH_AM1: channel->regs.am1 = value; break;
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case DMA_CH_AM1: channel->regs.am1 = value; break;
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case DMA_CH_DESC: channel->regs.desc = value; break;
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case DMA_CH_DESC: channel->regs.desc = value; break;
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case DMA_CH_SWPTR: channel->regs.swptr = value; break;
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case DMA_CH_SWPTR: channel->regs.swptr = value; break;
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}
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}
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}
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}
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}
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}
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/* Write a channel CSR
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/* Write a channel CSR
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* This ensures only the writable bits are modified.
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* This ensures only the writable bits are modified.
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*/
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*/
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void dma_write_ch_csr( struct dma_channel *channel, unsigned long value )
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void dma_write_ch_csr( struct dma_channel *channel, unsigned long value )
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{
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{
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/* Copy the writable bits to the channel CSR */
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/* Copy the writable bits to the channel CSR */
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channel->regs.csr &= ~DMA_CH_CSR_WRITE_MASK;
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channel->regs.csr &= ~DMA_CH_CSR_WRITE_MASK;
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channel->regs.csr |= value & DMA_CH_CSR_WRITE_MASK;
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channel->regs.csr |= value & DMA_CH_CSR_WRITE_MASK;
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}
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}
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/*
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/*
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* Simulation of control signals
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* Simulation of control signals
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* To be used by simulations for other devices, e.g. ethernet
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* To be used by simulations for other devices, e.g. ethernet
|
*/
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*/
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void set_dma_req_i( unsigned dma_controller, unsigned channel )
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void set_dma_req_i( unsigned dma_controller, unsigned channel )
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{
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{
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dmas[dma_controller].ch[channel].dma_req_i = 1;
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dmas[dma_controller].ch[channel].dma_req_i = 1;
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}
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}
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void clear_dma_req_i( unsigned dma_controller, unsigned channel )
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void clear_dma_req_i( unsigned dma_controller, unsigned channel )
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{
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{
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dmas[dma_controller].ch[channel].dma_req_i = 0;
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dmas[dma_controller].ch[channel].dma_req_i = 0;
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}
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}
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void set_dma_nd_i( unsigned dma_controller, unsigned channel )
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void set_dma_nd_i( unsigned dma_controller, unsigned channel )
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{
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{
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dmas[dma_controller].ch[channel].dma_nd_i = 1;
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dmas[dma_controller].ch[channel].dma_nd_i = 1;
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}
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}
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void clear_dma_nd_i( unsigned dma_controller, unsigned channel )
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void clear_dma_nd_i( unsigned dma_controller, unsigned channel )
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{
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{
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dmas[dma_controller].ch[channel].dma_nd_i = 0;
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dmas[dma_controller].ch[channel].dma_nd_i = 0;
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}
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}
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unsigned check_dma_ack_o( unsigned dma_controller, unsigned channel )
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unsigned check_dma_ack_o( unsigned dma_controller, unsigned channel )
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{
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{
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return dmas[dma_controller].ch[channel].dma_ack_o;
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return dmas[dma_controller].ch[channel].dma_ack_o;
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}
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}
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/* Simulation hook. Must be called every clock cycle to simulate DMA. */
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/* Simulation hook. Must be called every clock cycle to simulate DMA. */
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void dma_clock()
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void dma_clock()
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{
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{
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unsigned i;
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unsigned i;
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for ( i = 0; i < MAX_DMAS; ++ i ) {
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for ( i = 0; i < MAX_DMAS; ++ i ) {
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if ( dmas[i].baseaddr != 0 )
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if ( dmas[i].baseaddr != 0 )
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dma_controller_clock( &(dmas[i]) );
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dma_controller_clock( &(dmas[i]) );
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}
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}
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}
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}
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/* Clock tick for one DMA controller.
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/* Clock tick for one DMA controller.
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* This does the actual "DMA" operation.
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* This does the actual "DMA" operation.
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* One chunk is transferred per clock.
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* One chunk is transferred per clock.
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*/
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*/
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void dma_controller_clock( struct dma_controller *dma )
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void dma_controller_clock( struct dma_controller *dma )
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{
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{
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unsigned chno, i;
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unsigned chno, i;
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int breakpoint = 0;
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int breakpoint = 0;
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for ( chno = 0; chno < DMA_NUM_CHANNELS; ++ chno ) {
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for ( chno = 0; chno < DMA_NUM_CHANNELS; ++ chno ) {
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struct dma_channel *channel = &(dma->ch[chno]);
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struct dma_channel *channel = &(dma->ch[chno]);
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/* check if this channel is enabled */
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/* check if this channel is enabled */
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if ( !TEST_FLAG( channel->regs.csr, DMA_CH_CSR, CH_EN ) )
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if ( !TEST_FLAG( channel->regs.csr, DMA_CH_CSR, CH_EN ) )
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continue;
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continue;
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/* Do we need to abort? */
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/* Do we need to abort? */
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if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, STOP ) ) {
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if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, STOP ) ) {
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debug( 3, "DMA: STOP requested\n" );
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debug( 3, "DMA: STOP requested\n" );
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CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, CH_EN );
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CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, CH_EN );
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CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, BUSY );
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CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, BUSY );
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SET_FLAG( channel->regs.csr, DMA_CH_CSR, ERR );
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SET_FLAG( channel->regs.csr, DMA_CH_CSR, ERR );
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|
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if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, INE_ERR ) &&
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if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, INE_ERR ) &&
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(channel->controller->regs.int_msk_a & channel->channel_mask) ) {
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(channel->controller->regs.int_msk_a & channel->channel_mask) ) {
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SET_FLAG( channel->regs.csr, DMA_CH_CSR, INT_ERR );
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SET_FLAG( channel->regs.csr, DMA_CH_CSR, INT_ERR );
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channel->controller->regs.int_src_a = channel->channel_mask;
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channel->controller->regs.int_src_a = channel->channel_mask;
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report_interrupt( channel->controller->irq );
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report_interrupt( channel->controller->irq );
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}
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}
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|
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continue;
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continue;
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}
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}
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|
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/* In HW Handshake mode, only work when dma_req_i asserted */
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/* In HW Handshake mode, only work when dma_req_i asserted */
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if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, MODE ) &&
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if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, MODE ) &&
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!channel->dma_req_i ) {
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!channel->dma_req_i ) {
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continue;
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continue;
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}
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}
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/* If this is the first cycle of the transfer, initialize our state */
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/* If this is the first cycle of the transfer, initialize our state */
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if ( !TEST_FLAG( channel->regs.csr, DMA_CH_CSR, BUSY ) ) {
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if ( !TEST_FLAG( channel->regs.csr, DMA_CH_CSR, BUSY ) ) {
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debug( 4, "DMA: Starting new transfer\n" );
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debug( 4, "DMA: Starting new transfer\n" );
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|
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CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, DONE );
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CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, DONE );
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CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, ERR );
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CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, ERR );
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SET_FLAG( channel->regs.csr, DMA_CH_CSR, BUSY );
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SET_FLAG( channel->regs.csr, DMA_CH_CSR, BUSY );
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|
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/* If using linked lists, copy the appropriate fields to our registers */
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/* If using linked lists, copy the appropriate fields to our registers */
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if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, USE_ED ) )
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if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, USE_ED ) )
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dma_load_descriptor( channel );
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dma_load_descriptor( channel );
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else
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else
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channel->load_next_descriptor_when_done = 0;
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channel->load_next_descriptor_when_done = 0;
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/* Set our internal status */
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/* Set our internal status */
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dma_init_transfer( channel );
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dma_init_transfer( channel );
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/* Might need to skip descriptor */
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/* Might need to skip descriptor */
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if ( CHANNEL_ND_I( channel ) ) {
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if ( CHANNEL_ND_I( channel ) ) {
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debug( 3, "DMA: dma_nd_i asserted before dma_req_i, skipping descriptor\n" );
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debug( 3, "DMA: dma_nd_i asserted before dma_req_i, skipping descriptor\n" );
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dma_channel_terminate_transfer( channel, 0 );
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dma_channel_terminate_transfer( channel, 0 );
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continue;
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continue;
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}
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}
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}
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}
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|
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/* Transfer one word */
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/* Transfer one word */
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set_mem32( channel->destination, eval_mem32( channel->source, &breakpoint ), &breakpoint );
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set_mem32( channel->destination, eval_mem32( channel->source, &breakpoint ), &breakpoint );
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|
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/* Advance the source and destionation pointers */
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/* Advance the source and destionation pointers */
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masked_increase( &(channel->source), channel->source_mask );
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masked_increase( &(channel->source), channel->source_mask );
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masked_increase( &(channel->destination), channel->destination_mask );
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masked_increase( &(channel->destination), channel->destination_mask );
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++ channel->words_transferred;
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++ channel->words_transferred;
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|
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/* Have we finished a whole chunk? */
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/* Have we finished a whole chunk? */
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channel->dma_ack_o = (channel->words_transferred % channel->chunk_size == 0);
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channel->dma_ack_o = (channel->words_transferred % channel->chunk_size == 0);
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|
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/* When done with a chunk, check for dma_nd_i */
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/* When done with a chunk, check for dma_nd_i */
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if ( CHANNEL_ND_I( channel ) ) {
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if ( CHANNEL_ND_I( channel ) ) {
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debug( 3, "DMA: dma_nd_i asserted\n" );
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debug( 3, "DMA: dma_nd_i asserted\n" );
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dma_channel_terminate_transfer( channel, 0 );
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dma_channel_terminate_transfer( channel, 0 );
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continue;
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continue;
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}
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}
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|
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/* Are we done? */
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/* Are we done? */
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if ( channel->words_transferred >= channel->total_size )
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if ( channel->words_transferred >= channel->total_size )
|
dma_channel_terminate_transfer( channel, 1 );
|
dma_channel_terminate_transfer( channel, 1 );
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}
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}
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}
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}
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|
|
|
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/* Copy relevant valued from linked list descriptor to channel registers */
|
/* Copy relevant valued from linked list descriptor to channel registers */
|
void dma_load_descriptor( struct dma_channel *channel )
|
void dma_load_descriptor( struct dma_channel *channel )
|
{
|
{
|
int breakpoint = 0;
|
int breakpoint = 0;
|
unsigned long desc_csr = eval_mem32( channel->regs.desc + DMA_DESC_CSR, &breakpoint );
|
unsigned long desc_csr = eval_mem32( channel->regs.desc + DMA_DESC_CSR, &breakpoint );
|
|
|
channel->load_next_descriptor_when_done = !TEST_FLAG( desc_csr, DMA_DESC_CSR, EOL );
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channel->load_next_descriptor_when_done = !TEST_FLAG( desc_csr, DMA_DESC_CSR, EOL );
|
|
|
ASSIGN_FLAG( channel->regs.csr, DMA_CH_CSR, INC_SRC, TEST_FLAG( desc_csr, DMA_DESC_CSR, INC_SRC ) );
|
ASSIGN_FLAG( channel->regs.csr, DMA_CH_CSR, INC_SRC, TEST_FLAG( desc_csr, DMA_DESC_CSR, INC_SRC ) );
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ASSIGN_FLAG( channel->regs.csr, DMA_CH_CSR, INC_DST, TEST_FLAG( desc_csr, DMA_DESC_CSR, INC_DST ) );
|
ASSIGN_FLAG( channel->regs.csr, DMA_CH_CSR, INC_DST, TEST_FLAG( desc_csr, DMA_DESC_CSR, INC_DST ) );
|
ASSIGN_FLAG( channel->regs.csr, DMA_CH_CSR, SRC_SEL, TEST_FLAG( desc_csr, DMA_DESC_CSR, SRC_SEL ) );
|
ASSIGN_FLAG( channel->regs.csr, DMA_CH_CSR, SRC_SEL, TEST_FLAG( desc_csr, DMA_DESC_CSR, SRC_SEL ) );
|
ASSIGN_FLAG( channel->regs.csr, DMA_CH_CSR, DST_SEL, TEST_FLAG( desc_csr, DMA_DESC_CSR, DST_SEL ) );
|
ASSIGN_FLAG( channel->regs.csr, DMA_CH_CSR, DST_SEL, TEST_FLAG( desc_csr, DMA_DESC_CSR, DST_SEL ) );
|
|
|
SET_FIELD( channel->regs.sz, DMA_CH_SZ, TOT_SZ, GET_FIELD( desc_csr, DMA_DESC_CSR, TOT_SZ ) );
|
SET_FIELD( channel->regs.sz, DMA_CH_SZ, TOT_SZ, GET_FIELD( desc_csr, DMA_DESC_CSR, TOT_SZ ) );
|
|
|
channel->regs.a0 = eval_mem32( channel->regs.desc + DMA_DESC_ADR0, &breakpoint );
|
channel->regs.a0 = eval_mem32( channel->regs.desc + DMA_DESC_ADR0, &breakpoint );
|
channel->regs.a1 = eval_mem32( channel->regs.desc + DMA_DESC_ADR1, &breakpoint );
|
channel->regs.a1 = eval_mem32( channel->regs.desc + DMA_DESC_ADR1, &breakpoint );
|
|
|
channel->current_descriptor = channel->regs.desc;
|
channel->current_descriptor = channel->regs.desc;
|
channel->regs.desc = eval_mem32( channel->regs.desc + DMA_DESC_NEXT, &breakpoint );
|
channel->regs.desc = eval_mem32( channel->regs.desc + DMA_DESC_NEXT, &breakpoint );
|
}
|
}
|
|
|
|
|
/* Initialize internal parameters used to implement transfers */
|
/* Initialize internal parameters used to implement transfers */
|
void dma_init_transfer( struct dma_channel *channel )
|
void dma_init_transfer( struct dma_channel *channel )
|
{
|
{
|
channel->source = channel->regs.a0;
|
channel->source = channel->regs.a0;
|
channel->destination = channel->regs.a1;
|
channel->destination = channel->regs.a1;
|
channel->source_mask = TEST_FLAG( channel->regs.csr, DMA_CH_CSR, INC_SRC ) ? channel->regs.am0 : 0;
|
channel->source_mask = TEST_FLAG( channel->regs.csr, DMA_CH_CSR, INC_SRC ) ? channel->regs.am0 : 0;
|
channel->destination_mask = TEST_FLAG( channel->regs.csr, DMA_CH_CSR, INC_DST ) ? channel->regs.am1 : 0;
|
channel->destination_mask = TEST_FLAG( channel->regs.csr, DMA_CH_CSR, INC_DST ) ? channel->regs.am1 : 0;
|
channel->total_size = GET_FIELD( channel->regs.sz, DMA_CH_SZ, TOT_SZ );
|
channel->total_size = GET_FIELD( channel->regs.sz, DMA_CH_SZ, TOT_SZ );
|
channel->chunk_size = GET_FIELD( channel->regs.sz, DMA_CH_SZ, CHK_SZ );
|
channel->chunk_size = GET_FIELD( channel->regs.sz, DMA_CH_SZ, CHK_SZ );
|
if ( !channel->chunk_size || (channel->chunk_size > channel->total_size) )
|
if ( !channel->chunk_size || (channel->chunk_size > channel->total_size) )
|
channel->chunk_size = channel->total_size;
|
channel->chunk_size = channel->total_size;
|
channel->words_transferred = 0;
|
channel->words_transferred = 0;
|
}
|
}
|
|
|
|
|
/* Take care of transfer termination */
|
/* Take care of transfer termination */
|
void dma_channel_terminate_transfer( struct dma_channel *channel, int generate_interrupt )
|
void dma_channel_terminate_transfer( struct dma_channel *channel, int generate_interrupt )
|
{
|
{
|
debug( 4, "DMA: Terminating transfer\n" );
|
debug( 4, "DMA: Terminating transfer\n" );
|
|
|
/* Might be working in a linked list */
|
/* Might be working in a linked list */
|
if ( channel->load_next_descriptor_when_done ) {
|
if ( channel->load_next_descriptor_when_done ) {
|
dma_load_descriptor( channel );
|
dma_load_descriptor( channel );
|
dma_init_transfer( channel );
|
dma_init_transfer( channel );
|
return;
|
return;
|
}
|
}
|
|
|
/* Might be in auto-restart mode */
|
/* Might be in auto-restart mode */
|
if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, ARS ) ) {
|
if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, ARS ) ) {
|
dma_init_transfer( channel );
|
dma_init_transfer( channel );
|
return;
|
return;
|
}
|
}
|
|
|
/* If needed, write amount of data transferred back to memory */
|
/* If needed, write amount of data transferred back to memory */
|
if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, SZ_WB ) &&
|
if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, SZ_WB ) &&
|
TEST_FLAG( channel->regs.csr, DMA_CH_CSR, USE_ED ) ) {
|
TEST_FLAG( channel->regs.csr, DMA_CH_CSR, USE_ED ) ) {
|
int breakpoint = 0;
|
int breakpoint = 0;
|
unsigned long desc_csr = eval_mem32( channel->regs.desc + DMA_DESC_CSR, &breakpoint );
|
unsigned long desc_csr = eval_mem32( channel->regs.desc + DMA_DESC_CSR, &breakpoint );
|
/* TODO: What should we write back? Doc says "total number of remaining bytes" !? */
|
/* TODO: What should we write back? Doc says "total number of remaining bytes" !? */
|
unsigned long remaining_words = channel->total_size - channel->words_transferred;
|
unsigned long remaining_words = channel->total_size - channel->words_transferred;
|
SET_FIELD( channel->regs.sz, DMA_DESC_CSR, TOT_SZ, remaining_words );
|
SET_FIELD( channel->regs.sz, DMA_DESC_CSR, TOT_SZ, remaining_words );
|
}
|
}
|
|
|
/* Mark end of transfer */
|
/* Mark end of transfer */
|
CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, CH_EN );
|
CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, CH_EN );
|
SET_FLAG( channel->regs.csr, DMA_CH_CSR, DONE );
|
SET_FLAG( channel->regs.csr, DMA_CH_CSR, DONE );
|
CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, ERR );
|
CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, ERR );
|
CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, BUSY );
|
CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, BUSY );
|
|
|
/* If needed, generate interrupt */
|
/* If needed, generate interrupt */
|
if ( generate_interrupt ) {
|
if ( generate_interrupt ) {
|
/* TODO: Which channel should we interrupt? */
|
/* TODO: Which channel should we interrupt? */
|
if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, INE_DONE ) &&
|
if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, INE_DONE ) &&
|
(channel->controller->regs.int_msk_a & channel->channel_mask) ) {
|
(channel->controller->regs.int_msk_a & channel->channel_mask) ) {
|
SET_FLAG( channel->regs.csr, DMA_CH_CSR, INT_DONE );
|
SET_FLAG( channel->regs.csr, DMA_CH_CSR, INT_DONE );
|
channel->controller->regs.int_src_a = channel->channel_mask;
|
channel->controller->regs.int_src_a = channel->channel_mask;
|
report_interrupt( channel->controller->irq );
|
report_interrupt( channel->controller->irq );
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
/* Utility function: Add 4 to a value with a mask */
|
/* Utility function: Add 4 to a value with a mask */
|
void masked_increase( unsigned long *value, unsigned long mask )
|
void masked_increase( unsigned long *value, unsigned long mask )
|
{
|
{
|
*value = (*value & ~mask) | ((*value + 4) & mask);
|
*value = (*value & ~mask) | ((*value + 4) & mask);
|
}
|
}
|
|
|
