/* op_support.c -- Support routines for micro operations
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/* op_support.c -- Support routines for micro operations
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Copyright (C) 2005 György `nog' Jeney, nog@sdf.lonestar.org
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Copyright (C) 2005 György `nog' Jeney, nog@sdf.lonestar.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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#include <stdlib.h>
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#include <stdlib.h>
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#include "config.h"
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#include "config.h"
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#ifdef HAVE_INTTYPES_H
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#ifdef HAVE_INTTYPES_H
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#include <inttypes.h>
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#include <inttypes.h>
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#endif
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#endif
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#include "port.h"
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#include "port.h"
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#include "arch.h"
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#include "arch.h"
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#include "opcode/or32.h"
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#include "opcode/or32.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "spr_defs.h"
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#include "spr_defs.h"
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#include "except.h"
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#include "except.h"
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#include "immu.h"
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#include "immu.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "execute.h"
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#include "execute.h"
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#include "sched.h"
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#include "sched.h"
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#include "i386_regs.h"
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#include "i386_regs.h"
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#include "dyn_rec.h"
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#include "dyn_rec.h"
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#include "op_support.h"
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#include "op_support.h"
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#include "rec_i386.h"
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#include "rec_i386.h"
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/* Stuff that is really a `micro' operation but is rather big (or for some other
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/* Stuff that is really a `micro' operation but is rather big (or for some other
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* reason like calling exit()) */
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* reason like calling exit()) */
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void upd_reg_from_t(oraddr_t pc, int bound)
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void upd_reg_from_t(oraddr_t pc, int bound)
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{
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{
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int reg;
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int reg;
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pc = ((pc & (PAGE_SIZE - 1)) / 4);
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pc = ((pc & (PAGE_SIZE - 1)) / 4);
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if(bound) {
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if(bound) {
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reg = cpu_state.curr_page->ts_bound[pc + 1];
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reg = cpu_state.curr_page->ts_bound[pc + 1];
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} else
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} else
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reg = cpu_state.curr_page->ts_during[pc];
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reg = cpu_state.curr_page->ts_during[pc];
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if(reg & 0x1f)
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if(reg & 0x1f)
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cpu_state.reg[reg & 0x1f] = cpu_state.t0;
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cpu_state.reg[reg & 0x1f] = cpu_state.t0;
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if((reg >> 5) & 0x1f)
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if((reg >> 5) & 0x1f)
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cpu_state.reg[(reg >> 5) & 0x1f] = cpu_state.t1;
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cpu_state.reg[(reg >> 5) & 0x1f] = cpu_state.t1;
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if((reg >> 10) & 0x1f)
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if((reg >> 10) & 0x1f)
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cpu_state.reg[(reg >> 10) & 0x1f] = cpu_state.t2;
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cpu_state.reg[(reg >> 10) & 0x1f] = cpu_state.t2;
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}
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}
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void op_support_nop_exit(void)
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void op_support_nop_exit(void)
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{
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{
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upd_reg_from_t(get_pc(), 0);
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upd_reg_from_t(get_pc(), 0);
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PRINTF("exit(%"PRIxREG")\n", cpu_state.reg[3]);
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PRINTF("exit(%"PRIdREG")\n", cpu_state.reg[3]);
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fprintf(stderr, "@reset : cycles %lld, insn #%lld\n",
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fprintf(stderr, "@reset : cycles %lld, insn #%lld\n",
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runtime.sim.reset_cycles, runtime.cpu.reset_instructions);
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runtime.sim.reset_cycles, runtime.cpu.reset_instructions);
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fprintf(stderr, "@exit : cycles %lld, insn #%lld\n", runtime.sim.cycles,
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fprintf(stderr, "@exit : cycles %lld, insn #%lld\n", runtime.sim.cycles,
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runtime.cpu.instructions);
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runtime.cpu.instructions);
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fprintf(stderr, " diff : cycles %lld, insn #%lld\n",
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fprintf(stderr, " diff : cycles %lld, insn #%lld\n",
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runtime.sim.cycles - runtime.sim.reset_cycles,
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runtime.sim.cycles - runtime.sim.reset_cycles,
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runtime.cpu.instructions - runtime.cpu.reset_instructions);
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runtime.cpu.instructions - runtime.cpu.reset_instructions);
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/* FIXME: Implement emulation of a stalled cpu
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/* FIXME: Implement emulation of a stalled cpu
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if (config.debug.gdb_enabled)
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if (config.debug.gdb_enabled)
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set_stall_state (1);
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set_stall_state (1);
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else {
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else {
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handle_sim_command();
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handle_sim_command();
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sim_done();
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sim_done();
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}
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}
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*/
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*/
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exit(0);
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exit(0);
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}
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}
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void op_support_nop_reset(void)
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void op_support_nop_reset(void)
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{
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{
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PRINTF("****************** counters reset ******************\n");
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PRINTF("****************** counters reset ******************\n");
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PRINTF("cycles %lld, insn #%lld\n", runtime.sim.cycles, runtime.cpu.instructions);
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PRINTF("cycles %lld, insn #%lld\n", runtime.sim.cycles, runtime.cpu.instructions);
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PRINTF("****************** counters reset ******************\n");
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PRINTF("****************** counters reset ******************\n");
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runtime.sim.reset_cycles = runtime.sim.cycles;
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runtime.sim.reset_cycles = runtime.sim.cycles;
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runtime.cpu.reset_instructions = runtime.cpu.instructions;
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runtime.cpu.reset_instructions = runtime.cpu.instructions;
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}
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}
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void op_support_nop_printf(void)
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void op_support_nop_printf(void)
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{
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{
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upd_reg_from_t(get_pc(), 0);
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upd_reg_from_t(get_pc(), 0);
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simprintf(cpu_state.reg[4], cpu_state.reg[3]);
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simprintf(cpu_state.reg[4], cpu_state.reg[3]);
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}
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}
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void op_support_nop_report(void)
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void op_support_nop_report(void)
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{
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{
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upd_reg_from_t(get_pc(), 0);
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upd_reg_from_t(get_pc(), 0);
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PRINTF("report(0x%"PRIxREG");\n", cpu_state.reg[3]);
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PRINTF("report(0x%"PRIxREG");\n", cpu_state.reg[3]);
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}
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}
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void op_support_nop_report_imm(int imm)
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void op_support_nop_report_imm(int imm)
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{
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{
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upd_reg_from_t(get_pc(), 0);
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upd_reg_from_t(get_pc(), 0);
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PRINTF("report %i (0x%"PRIxREG");\n", imm, cpu_state.reg[3]);
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PRINTF("report %i (0x%"PRIxREG");\n", imm, cpu_state.reg[3]);
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}
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}
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/* Handles a jump */
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/* Handles a jump */
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/* addr is a VIRTUAL address */
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/* addr is a VIRTUAL address */
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/* NOTE: We can't use env since this code is compiled like the rest of the
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/* NOTE: We can't use env since this code is compiled like the rest of the
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* simulator (most likely without -fomit-frame-pointer) and thus env will point
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* simulator (most likely without -fomit-frame-pointer) and thus env will point
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* to some bogus value. */
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* to some bogus value. */
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void do_jump(oraddr_t addr)
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void do_jump(oraddr_t addr)
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{
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{
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struct dyn_page *target_dp;
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struct dyn_page *target_dp;
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oraddr_t phys_page;
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oraddr_t phys_page;
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/* Temporaries are always shipped out */
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/* Temporaries are always shipped out */
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cpu_state.ts_current = 1;
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cpu_state.ts_current = 1;
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/* The pc is set to the location of the jump in op_set_pc_preemt(_check) and
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/* The pc is set to the location of the jump in op_set_pc_preemt(_check) and
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* then it is incermented by 4 when the scheduler is run. If a scheduled job
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* then it is incermented by 4 when the scheduler is run. If a scheduled job
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* so happens to raise an exception cpu_state.delay_insn will still be set and
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* so happens to raise an exception cpu_state.delay_insn will still be set and
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* so except_handle will do its pc adjusting magic (ie. -4 from it) and every-
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* so except_handle will do its pc adjusting magic (ie. -4 from it) and every-
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* thing ends up just working right, except when a scheduled job does not
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* thing ends up just working right, except when a scheduled job does not
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* raise an exeception. In that case we set the pc here explicitly */
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* raise an exeception. In that case we set the pc here explicitly */
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set_pc(addr);
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set_pc(addr);
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/* immu_translate must be called after set_pc. If it would be called before
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/* immu_translate must be called after set_pc. If it would be called before
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* it and it issued an ITLB miss then it would appear that the instruction
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* it and it issued an ITLB miss then it would appear that the instruction
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* that faulted was the instruction in the delay slot which is incorrect */
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* that faulted was the instruction in the delay slot which is incorrect */
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phys_page = immu_translate(addr);
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phys_page = immu_translate(addr);
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/* do_jump is called from the delay slot, which is the jump instruction
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/* do_jump is called from the delay slot, which is the jump instruction
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* address + 4. */
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* address + 4. */
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/*
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/*
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printf("Recompiled code jumping out to %"PRIxADDR" from %"PRIxADDR"\n",
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printf("Recompiled code jumping out to %"PRIxADDR" from %"PRIxADDR"\n",
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phys_page, cpu_state.sprs[SPR_PPC] - 4);
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phys_page, cpu_state.sprs[SPR_PPC] - 4);
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*/
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*/
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/* immu_translate() adds the hit delay to runtime.sim.mem_cycles but we add it
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/* immu_translate() adds the hit delay to runtime.sim.mem_cycles but we add it
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* to the cycles when the instruction is executed so if we don't reset it now
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* to the cycles when the instruction is executed so if we don't reset it now
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* it will produce wrong results */
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* it will produce wrong results */
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runtime.sim.mem_cycles = 0;
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runtime.sim.mem_cycles = 0;
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target_dp = find_dynd_page(phys_page);
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target_dp = find_dynd_page(phys_page);
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if(!target_dp)
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if(!target_dp)
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target_dp = new_dp(phys_page);
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target_dp = new_dp(phys_page);
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/* Since writes to the 0x0-0xff range do not dirtyfy a page recompile the 0x0
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/* Since writes to the 0x0-0xff range do not dirtyfy a page recompile the 0x0
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* page if the jump is to that location */
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* page if the jump is to that location */
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if(phys_page < 0x100)
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if(phys_page < 0x100)
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target_dp->dirty = 1;
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target_dp->dirty = 1;
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if(target_dp->dirty)
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if(target_dp->dirty)
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recompile_page(target_dp);
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recompile_page(target_dp);
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cpu_state.curr_page = target_dp;
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cpu_state.curr_page = target_dp;
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/* FIXME: If the page is backed by more than one type of memory, this will
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/* FIXME: If the page is backed by more than one type of memory, this will
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* produce wrong results */
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* produce wrong results */
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if(cpu_state.sprs[SPR_SR] & SPR_SR_IME)
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if(cpu_state.sprs[SPR_SR] & SPR_SR_IME)
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/* Add the mmu hit delay to the cycle counter */
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/* Add the mmu hit delay to the cycle counter */
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upd_cycles_dec(target_dp->delayr - config.immu.hitdelay);
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upd_cycles_dec(target_dp->delayr - config.immu.hitdelay);
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else
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else
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upd_cycles_dec(target_dp->delayr);
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upd_cycles_dec(target_dp->delayr);
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cpu_state.ts_current = 0;
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cpu_state.ts_current = 0;
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/* Initially this returned the address that we should jump to and then the
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/* Initially this returned the address that we should jump to and then the
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* recompiled code performed the jump. This was no problem if the jump was
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* recompiled code performed the jump. This was no problem if the jump was
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* trully an interpage jump or if the location didn't need recompileation. If
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* trully an interpage jump or if the location didn't need recompileation. If
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* the jump is page local and the page needs recompileation there is a very
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* the jump is page local and the page needs recompileation there is a very
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* high probability that the page will move in memory and then the return
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* high probability that the page will move in memory and then the return
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* address that is on the stack will point to memory that has already been
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* address that is on the stack will point to memory that has already been
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* freed, sometimes leading to crashes */
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* freed, sometimes leading to crashes */
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/* This looks like it could really be simpler, but no it can't. The only
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/* This looks like it could really be simpler, but no it can't. The only
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* issue here is the stack: it has to be unwound. This function is called
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* issue here is the stack: it has to be unwound. This function is called
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* from except_handle, which generally ends up quite high on the stack... */
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* from except_handle, which generally ends up quite high on the stack... */
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enter_dyn_code(phys_page, target_dp);
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enter_dyn_code(phys_page, target_dp);
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}
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}
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/* Wrapper around analysis() that contains all the recompiler specific stuff */
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/* Wrapper around analysis() that contains all the recompiler specific stuff */
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void op_support_analysis(void)
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void op_support_analysis(void)
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{
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{
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upd_sim_cycles();
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upd_sim_cycles();
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if(IADDR_PAGE(cpu_state.pc) != cpu_state.pc)
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if(IADDR_PAGE(cpu_state.pc) != cpu_state.pc)
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upd_reg_from_t(cpu_state.pc - (cpu_state.delay_insn ? 4 : 0), 0);
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upd_reg_from_t(cpu_state.pc - (cpu_state.delay_insn ? 4 : 0), 0);
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else
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else
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upd_reg_from_t(cpu_state.pc, 0);
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upd_reg_from_t(cpu_state.pc, 0);
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runtime.cpu.instructions++;
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runtime.cpu.instructions++;
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analysis(&cpu_state.iqueue);
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analysis(&cpu_state.iqueue);
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}
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}
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