/* debug_unit.h -- Simulation of Or1k debug unit
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/* debug_unit.h -- Simulation of Or1k debug unit
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Copyright (C) 2001 Chris Ziomkowski, chris@asics.ws
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Copyright (C) 2001 Chris Ziomkowski, chris@asics.ws
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* Registers */
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/* In general, little endian machines should pack bits from the LSB to
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the MSB, while big endian machines should do the reverse. The bit
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structures are declared in both orders, and we select which structure
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definition to use based on this macro assignment. If your architecture
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is special, you may have to redefine the algorithm defined in the
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SET_REG32 and GET_REG32 macros below. */
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#if (defined (__arm__) && ! defined (__ARMEB__)) || defined (__i386__) || defined (__i860__) || defined (__ns32000__) || defined (__vax__)
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#define LITTLE_ENDIAN_BIT_FILL
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#else
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#define BIG_ENDIAN_BIT_FILL
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#endif
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typedef enum {
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DCR_CT_Disabled = 0,
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DCR_CT_InsnAddress = 1,
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DCR_CT_LoadAddress = 2,
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DCR_CT_StoreAddress = 3,
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DCR_CT_LoadData = 4,
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DCR_CT_StoreData = 5,
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DCR_CT_Reserved1 = 6,
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DCR_CT_Reserved2 = 7,
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} DCR_CT_Settings;
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typedef enum {
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DCR_SC_Signed = 0,
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DCR_SC_Unsigned = 1,
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} DCR_SC_Settings;
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typedef enum {
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DCR_CC_Masked = 0,
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DCR_CC_Equal = 1,
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DCR_CC_LessThan = 2,
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DCR_CC_LessEqual = 3,
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DCR_CC_GreaterThan = 4,
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DCR_CC_GreaterEqual = 5,
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DCR_CC_NotEqual = 6,
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DCR_CC_Reserved = 7,
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} DCR_CC_Settings;
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typedef enum {
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DCR_DP_Absent = 0,
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DCR_DP_Present = 1,
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} DCR_DP_Settings;
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#ifdef LITTLE_ENDIAN_BIT_FILL
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typedef struct {
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DCR_DP_Settings DP:1;
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DCR_CC_Settings CC:3;
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DCR_SC_Settings SC:1;
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DCR_CT_Settings CT:3;
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unsigned int reserved:24;
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} DCRregister;
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typedef struct {
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unsigned int CW0:2;
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unsigned int CW1:2;
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unsigned int CW2:2;
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unsigned int CW3:2;
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unsigned int CW4:2;
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unsigned int CW5:2;
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unsigned int CW6:2;
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unsigned int CW7:2;
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unsigned int CW8:2;
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unsigned int CW9:2;
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unsigned int CW10:2;
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unsigned int ST:1;
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unsigned int BT:1;
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unsigned int DXFW:1;
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unsigned int reserved:7;
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} DMR1register;
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typedef struct {
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unsigned int WCE0:1;
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unsigned int WCE1:1;
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unsigned int AWPC:11;
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unsigned int WGB:11;
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unsigned int reserved:8;
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} DMR2register;
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typedef struct {
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unsigned int COUNT:16;
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unsigned int MATCH:16;
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} DWCRregister;
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typedef struct {
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unsigned int RSTE:1;
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unsigned int BUSEE:1;
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unsigned int DPFE:1;
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unsigned int IPFE:1;
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unsigned int LPINTE:1;
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unsigned int AE:1;
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unsigned int IIE:1;
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unsigned int HPINTE:1;
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unsigned int DME:1;
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unsigned int IME:1;
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unsigned int RE:1;
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unsigned int SCE:1;
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unsigned int BE:1;
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unsigned int TE:1;
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unsigned int reserved:18;
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} DSRregister;
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typedef struct {
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unsigned int RSTE:1;
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unsigned int BUSEE:1;
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unsigned int DPFE:1;
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unsigned int IPFE:1;
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unsigned int LPINTE:1;
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unsigned int AE:1;
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unsigned int IIE:1;
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unsigned int HPINTE:1;
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unsigned int DME:1;
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unsigned int IME:1;
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unsigned int RE:1;
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unsigned int SCE:1;
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unsigned int BE:1;
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unsigned int TE:1;
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unsigned int reserved:18;
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} DRRregister;
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typedef struct {
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unsigned int CONTIN:1;
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unsigned int ENABLE:1;
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unsigned int RECSELDEPEND:1;
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unsigned int reserved:29;
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} MODERregister;
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typedef struct {
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unsigned int WPTRIG:11;
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unsigned int WPTRIGVALID:1;
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unsigned int BPTRIG:1;
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unsigned int BPTRIGVALID:1;
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unsigned int reserved2:2;
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unsigned int LSSTRIG:4;
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unsigned int LSSTRIGVALID:1;
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unsigned int ISTRIG:4;
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unsigned int ISTRIGVALID:1;
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unsigned int reserved1:4;
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unsigned int TRIGOP:2;
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} TSELregister;
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typedef struct {
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unsigned int WPQUALIF:11;
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unsigned int WPQUALIFVALID:1;
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unsigned int BPQUALIF:1;
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unsigned int BPQUALIFVALID:1;
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unsigned int reserved2:2;
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unsigned int LSSQUALIF:4;
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unsigned int LSSQUALIFVALID:1;
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unsigned int ISTQUALIF:4;
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unsigned int ISTQUALIFVALID:1;
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unsigned int reserved1:4;
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unsigned int QUALIFOP:2;
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} QSELregister;
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typedef struct {
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unsigned int WPSTOP:11;
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unsigned int WPSTOPVALID:1;
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unsigned int BPSTOP:1;
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unsigned int BPSTOPVALID:1;
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unsigned int reserved2:2;
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unsigned int LSSSTOP:4;
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unsigned int LSSSTOPVALID:1;
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unsigned int ISTSTOP:4;
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unsigned int ISTSTOPVALID:1;
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unsigned int reserved1:4;
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unsigned int STOPOP:2;
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} SSELregister;
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typedef struct {
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unsigned int RISCSTALL:1;
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volatile unsigned int RESET:1;
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unsigned int reserved:30;
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} RISCOPregister;
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typedef struct {
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unsigned int RECPC:1;
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unsigned int RECLSEA:1;
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unsigned int RECLDATA:1;
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unsigned int RECSDATA:1;
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unsigned int RECREADSPR:1;
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unsigned int RECWRITESPR:1;
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unsigned int RECINSTR:1;
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unsigned int reserved:25;
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} RECWPregister;
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typedef struct {
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unsigned int RECPC:1;
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unsigned int RECLSEA:1;
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unsigned int RECLDATA:1;
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unsigned int RECSDATA:1;
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unsigned int RECREADSPR:1;
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unsigned int RECWRITESPR:1;
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unsigned int RECINSTR:1;
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unsigned int reserved:25;
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} RECBPregister;
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#else /* BIG_ENDIAN_BIT_FILL */
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typedef struct {
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unsigned int reserved:24;
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DCR_CT_Settings CT:3;
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DCR_SC_Settings SC:1;
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DCR_CC_Settings CC:3;
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DCR_DP_Settings DP:1;
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} DCRregister;
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typedef struct {
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unsigned int reserved:7;
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unsigned int DXFW:1;
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unsigned int BT:1;
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unsigned int ST:1;
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unsigned int CW10:2;
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unsigned int CW9:2;
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unsigned int CW8:2;
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unsigned int CW7:2;
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unsigned int CW6:2;
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unsigned int CW5:2;
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unsigned int CW4:2;
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unsigned int CW3:2;
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unsigned int CW2:2;
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unsigned int CW1:2;
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unsigned int CW0:2;
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} DMR1register;
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typedef struct {
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unsigned int reserved:8;
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unsigned int WGB:11;
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unsigned int AWPC:11;
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unsigned int WCE1:1;
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unsigned int WCE0:1;
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} DMR2register;
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typedef struct {
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unsigned int MATCH:16;
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unsigned int COUNT:16;
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} DWCRregister;
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typedef struct {
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unsigned int reserved:18;
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unsigned int TE:1;
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unsigned int BE:1;
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unsigned int SCE:1;
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unsigned int RE:1;
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unsigned int IME:1;
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unsigned int DME:1;
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unsigned int HPINTE:1;
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unsigned int IIE:1;
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unsigned int AE:1;
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unsigned int LPINTE:1;
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unsigned int IPFE:1;
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unsigned int DPFE:1;
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unsigned int BUSEE:1;
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unsigned int RSTE:1;
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} DSRregister;
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typedef struct {
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unsigned int reserved:18;
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unsigned int TE:1;
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unsigned int BE:1;
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unsigned int SCE:1;
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unsigned int RE:1;
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unsigned int IME:1;
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unsigned int DME:1;
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unsigned int HPINTE:1;
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unsigned int IIE:1;
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unsigned int AE:1;
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unsigned int LPINTE:1;
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unsigned int IPFE:1;
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unsigned int DPFE:1;
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unsigned int BUSEE:1;
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unsigned int RSTE:1;
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} DRRregister;
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typedef struct {
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unsigned int reserved:29;
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unsigned int RECSELDEPEND:1;
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unsigned int ENABLE:1;
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unsigned int CONTIN:1;
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} MODERregister;
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typedef struct {
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unsigned int TRIGOP:2;
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unsigned int reserved1:4;
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unsigned int ISTRIGVALID:1;
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unsigned int ISTRIG:4;
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unsigned int LSSTRIGVALID:1;
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unsigned int LSSTRIG:4;
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unsigned int reserved2:2;
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unsigned int BPTRIGVALID:1;
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unsigned int BPTRIG:1;
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unsigned int WPTRIGVALID:1;
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unsigned int WPTRIG:11;
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} TSELregister;
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typedef struct {
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unsigned int QUALIFOP:2;
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unsigned int reserved1:4;
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unsigned int ISTQUALIFVALID:1;
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unsigned int ISTQUALIF:4;
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unsigned int LSSQUALIFVALID:1;
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unsigned int LSSQUALIF:4;
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unsigned int reserved2:2;
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unsigned int BPQUALIFVALID:1;
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unsigned int BPQUALIF:1;
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unsigned int WPQUALIFVALID:1;
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unsigned int WPQUALIF:11;
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} QSELregister;
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typedef struct {
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unsigned int STOPOP:2;
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unsigned int reserved1:4;
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unsigned int ISTSTOPVALID:1;
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unsigned int ISTSTOP:4;
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unsigned int LSSSTOPVALID:1;
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unsigned int LSSSTOP:4;
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unsigned int reserved2:2;
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unsigned int BPSTOPVALID:1;
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unsigned int BPSTOP:1;
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unsigned int WPSTOPVALID:1;
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unsigned int WPSTOP:11;
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} SSELregister;
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typedef struct {
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unsigned int reserved:30;
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unsigned int RESET:1;
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unsigned int RISCSTALL:1;
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} RISCOPregister;
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typedef struct {
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unsigned int reserved:25;
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unsigned int RECINSTR:1;
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unsigned int RECWRITESPR:1;
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unsigned int RECREADSPR:1;
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unsigned int RECSDATA:1;
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unsigned int RECLDATA:1;
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unsigned int RECLSEA:1;
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unsigned int RECPC:1;
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} RECWPregister;
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typedef struct {
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unsigned int reserved:25;
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unsigned int RECINSTR:1;
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unsigned int RECWRITESPR:1;
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unsigned int RECREADSPR:1;
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unsigned int RECSDATA:1;
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unsigned int RECLDATA:1;
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unsigned int RECLSEA:1;
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unsigned int RECPC:1;
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} RECBPregister;
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#endif /* LITTLE_ENDIAN_BIT_FILL */
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typedef struct {
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unsigned int DVR[8];
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DCRregister DCR[8];
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unsigned int DCR_hit;
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unsigned int watchpoint;
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DMR1register DMR1;
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DMR2register DMR2;
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DWCRregister DWCR[2];
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DSRregister DSR;
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DRRregister DRR;
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unsigned int DIR;
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} DebugUnit;
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typedef enum {
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DebugInstructionFetch = 1,
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DebugLoadAddress = 2,
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DebugStoreAddress = 3,
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DebugLoadData = 4,
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DebugStoreData = 5,
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} DebugUnitAction;
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extern DebugUnit debug_unit;
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void InitializeDebugUnit(void);
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void InduceImmediateInstruction(unsigned long);
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void SetCPUStallState(int state);
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typedef enum {
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typedef enum {
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JTAG_CHAIN_GLOBAL = 0,
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JTAG_CHAIN_GLOBAL = 0,
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JTAG_CHAIN_DEBUG_UNIT = 1,
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JTAG_CHAIN_DEBUG_UNIT = 1,
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JTAG_CHAIN_TEST = 2,
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JTAG_CHAIN_TEST = 2,
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JTAG_CHAIN_TRACE = 3,
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JTAG_CHAIN_TRACE = 3,
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JTAG_CHAIN_DEVELOPMENT = 4,
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JTAG_CHAIN_DEVELOPMENT = 4,
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JTAG_CHAIN_WISHBONE = 5,
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JTAG_CHAIN_WISHBONE = 5,
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JTAG_CHAIN_BLOCK1 = 6,
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JTAG_CHAIN_BLOCK1 = 6,
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JTAG_CHAIN_BLOCK2 = 7,
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JTAG_CHAIN_BLOCK2 = 7,
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JTAG_CHAIN_OPTIONAL0 = 8,
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JTAG_CHAIN_OPTIONAL0 = 8,
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JTAG_CHAIN_OPTIONAL1 = 9,
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JTAG_CHAIN_OPTIONAL1 = 9,
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JTAG_CHAIN_OPTIONAL2 = 10,
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JTAG_CHAIN_OPTIONAL2 = 10,
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JTAG_CHAIN_OPTIONAL3 = 11,
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JTAG_CHAIN_OPTIONAL3 = 11,
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JTAG_CHAIN_OPTIONAL4 = 12,
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JTAG_CHAIN_OPTIONAL4 = 12,
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JTAG_CHAIN_OPTIONAL5 = 13,
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JTAG_CHAIN_OPTIONAL5 = 13,
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JTAG_CHAIN_OPTIONAL6 = 14,
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JTAG_CHAIN_OPTIONAL6 = 14,
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JTAG_CHAIN_OPTIONAL7 = 15,
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JTAG_CHAIN_OPTIONAL7 = 15,
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} DebugScanChainIDs;
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} DebugScanChainIDs;
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typedef struct {
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typedef struct {
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MODERregister MODER;
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unsigned int DCR_hit;
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TSELregister TSEL;
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unsigned int watchpoint;
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QSELregister QSEL;
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} DebugUnit;
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SSELregister SSEL;
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RISCOPregister RISCOP;
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typedef enum {
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RECWPregister RECWP[11];
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DebugInstructionFetch = 1,
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RECBPregister RECBP[1];
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DebugLoadAddress = 2,
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DebugStoreAddress = 3,
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DebugLoadData = 4,
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DebugStoreData = 5,
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} DebugUnitAction;
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/* Debug registers and their bits */
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typedef struct {
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unsigned long moder;
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unsigned long tsel;
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unsigned long qsel;
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unsigned long ssel;
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unsigned long riscop;
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unsigned long recwp[11];
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unsigned long recbp;
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} DevelopmentInterface;
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} DevelopmentInterface;
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typedef enum {
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typedef enum {
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DEVELOPINT_MODER = 0,
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DEVELOPINT_MODER = 0,
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DEVELOPINT_TSEL = 1,
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DEVELOPINT_TSEL = 1,
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DEVELOPINT_QSEL = 2,
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DEVELOPINT_QSEL = 2,
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DEVELOPINT_SSEL = 3,
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DEVELOPINT_SSEL = 3,
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DEVELOPINT_RISCOP = 4,
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DEVELOPINT_RISCOP = 4,
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DEVELOPINT_RECWP0 = 16,
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DEVELOPINT_RECWP0 = 16,
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DEVELOPINT_RECWP1 = 17,
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DEVELOPINT_RECWP1 = 17,
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DEVELOPINT_RECWP2 = 18,
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DEVELOPINT_RECWP2 = 18,
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DEVELOPINT_RECWP3 = 19,
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DEVELOPINT_RECWP3 = 19,
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DEVELOPINT_RECWP4 = 20,
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DEVELOPINT_RECWP4 = 20,
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DEVELOPINT_RECWP5 = 21,
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DEVELOPINT_RECWP5 = 21,
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DEVELOPINT_RECWP6 = 22,
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DEVELOPINT_RECWP6 = 22,
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DEVELOPINT_RECWP7 = 23,
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DEVELOPINT_RECWP7 = 23,
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DEVELOPINT_RECWP8 = 24,
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DEVELOPINT_RECWP8 = 24,
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DEVELOPINT_RECWP9 = 25,
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DEVELOPINT_RECWP9 = 25,
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DEVELOPINT_RECWP10 = 26,
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DEVELOPINT_RECWP10 = 26,
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DEVELOPINT_RECBP0 = 27,
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DEVELOPINT_RECBP0 = 27,
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} DevelopmentInterfaceAddressSpace;
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} DevelopmentInterfaceAddressSpace;
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typedef enum {
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#define RISCOP_STALL 0x00000001
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DEBUGINT_DVR0 = 0,
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#define RISCOP_RESET 0x00000002
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DEBUGINT_DVR1 = 1,
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DEBUGINT_DVR2 = 2,
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/* Risc stall state */
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DEBUGINT_DVR3 = 3,
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extern int cpu_stalled;
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DEBUGINT_DVR4 = 4,
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DEBUGINT_DVR5 = 5,
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/* Resets the debug unit */
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DEBUGINT_DVR6 = 6,
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void du_reset(void);
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DEBUGINT_DVR7 = 7,
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DEBUGINT_DCR0 = 8,
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/* set cpu_stalled flag */
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DEBUGINT_DCR1 = 9,
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void set_stall_state (int state);
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DEBUGINT_DCR2 = 10,
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DEBUGINT_DCR3 = 11,
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/* Whether debug unit should ignore exception */
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DEBUGINT_DCR4 = 12,
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int debug_ignore_exception (unsigned long except);
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DEBUGINT_DCR5 = 13,
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DEBUGINT_DCR6 = 14,
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DEBUGINT_DCR7 = 15,
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DEBUGINT_DMR1 = 16,
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DEBUGINT_DMR2 = 17,
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DEBUGINT_DWCR0 = 18,
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DEBUGINT_DWCR1 = 19,
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DEBUGINT_DSR = 20,
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DEBUGINT_DRR = 21,
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DEBUGINT_DIR = 22,
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} DebugInterfaceAddressSpace;
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|
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/* This assumes a pointer to a 32 bit aligned bit field has
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been passed and that the compiler aligns bit fields on
|
|
32 bit boundaries in big endian order. If either one of
|
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these two conditions are not true for your architecture
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you may need to adjust this macro. */
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#define SET_REG32(x,y) *((uint32_t*)&x) = (uint32_t)y
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#define GET_REG32(x,y) y = *((uint32_t*)&x)
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#ifdef DEBUGMOD_OFF
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#ifdef DEBUGMOD_OFF
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#define CheckDebugUnit(x,y) 0
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#define CheckDebugUnit(x,y) 0
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#endif
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#endif
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No newline at end of file
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No newline at end of file
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