#ifndef CYGONCE_DEVS_ADDER_ETH_INL
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#ifndef CYGONCE_DEVS_ADDER_ETH_INL
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#define CYGONCE_DEVS_ADDER_ETH_INL
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#define CYGONCE_DEVS_ADDER_ETH_INL
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//==========================================================================
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//==========================================================================
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//
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//
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// adder_eth.inl
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// adder_eth.inl
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//
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//
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// Hardware specifics for A&M Adder ethernet support
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// Hardware specifics for A&M Adder ethernet support
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//
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//
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//==========================================================================
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//==========================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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// Copyright (C) 2002 Gary Thomas
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// Copyright (C) 2002 Gary Thomas
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//
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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//
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// As a special exception, if other files instantiate templates or use macros
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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// in accordance with section (3) of the GNU General Public License.
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//
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//
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// This exception does not invalidate any other reasons why a work based on
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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// this file might be covered by the GNU General Public License.
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//
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//#####DESCRIPTIONBEGIN####
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//
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//
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// Author(s): gthomas
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// Author(s): gthomas
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// Contributors: gthomas
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// Contributors: gthomas
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// Date: 2002-11-19
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// Date: 2002-11-19
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// Purpose:
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// Purpose:
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// Description:
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// Description:
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//
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//
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//####DESCRIPTIONEND####
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//####DESCRIPTIONEND####
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//
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//
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//==========================================================================
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//==========================================================================
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extern int _adder_get_leds(void);
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extern int _adder_get_leds(void);
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extern void _adder_set_leds(int);
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extern void _adder_set_leds(int);
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extern bool _adder_reset_phy(void);
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extern bool _adder_reset_phy(void);
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#define _get_led() _adder_get_leds()
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#define _get_led() _adder_get_leds()
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#define _set_led(v) _adder_set_leds(v)
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#define _set_led(v) _adder_set_leds(v)
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#define LED_TxACTIVE 2
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#define LED_TxACTIVE 2
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#define LED_RxACTIVE 1
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#define LED_RxACTIVE 1
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// Reset the PHY - analagous to hardware reset
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// Reset the PHY - analagous to hardware reset
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#define QUICC_ETH_RESET_PHY() \
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#define QUICC_ETH_RESET_PHY() \
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if (!_adder_reset_phy()) { \
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if (!_adder_reset_phy()) { \
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diag_printf("Can't reset PHY or get link\n"); \
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diag_printf("Can't reset PHY or get link\n"); \
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}
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}
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// Port layout - uses SCC2
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// Port layout - uses SCC2
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#define QUICC_ETH_INT CYGNUM_HAL_INTERRUPT_CPM_SCC2
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#define QUICC_ETH_INT CYGNUM_HAL_INTERRUPT_CPM_SCC2
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#define QUICC_ETH_SCC 1 // SCC2
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#define QUICC_ETH_SCC 1 // SCC2
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#define QUICC_CPM_SCCx QUICC_CPM_SCC2
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#define QUICC_CPM_SCCx QUICC_CPM_SCC2
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// Fixed bits
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// Fixed bits
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#define QUICC_ETH_PA_RXD 0x0004 // Rx Data on Port A
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#define QUICC_ETH_PA_RXD 0x0004 // Rx Data on Port A
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#define QUICC_ETH_PA_TXD 0x0008 // Tx Data on Port A
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#define QUICC_ETH_PA_TXD 0x0008 // Tx Data on Port A
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#define QUICC_ETH_PC_COLLISION 0x0040 // Collision detect
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#define QUICC_ETH_PC_COLLISION 0x0040 // Collision detect
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#define QUICC_ETH_PC_Rx_ENABLE 0x0080 // Rx Enable (RENA)
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#define QUICC_ETH_PC_Rx_ENABLE 0x0080 // Rx Enable (RENA)
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// These depend on how the PHY is wired to the CPU
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// These depend on how the PHY is wired to the CPU
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#define QUICC_ETH_PA_Tx_CLOCK 0x0200 // Tx Clock = CLK2
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#define QUICC_ETH_PA_Tx_CLOCK 0x0200 // Tx Clock = CLK2
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#define QUICC_ETH_PA_Rx_CLOCK 0x0800 // Rx Clock = CLK4
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#define QUICC_ETH_PA_Rx_CLOCK 0x0800 // Rx Clock = CLK4
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#define QUICC_ETH_SICR_MASK 0xFF00 // SI Clock Route - important bits
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#define QUICC_ETH_SICR_MASK 0xFF00 // SI Clock Route - important bits
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#define QUICC_ETH_SICR_ENET (7<<11)|(5<<8) // Rx=CLK4, Tx=CLK2
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#define QUICC_ETH_SICR_ENET (7<<11)|(5<<8) // Rx=CLK4, Tx=CLK2
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#define QUICC_ETH_SICR_ENABLE 0x4000 // Enable SCC2 to use NMSI
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#define QUICC_ETH_SICR_ENABLE 0x4000 // Enable SCC2 to use NMSI
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// The TENA signal can appear on either port B or C
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// The TENA signal can appear on either port B or C
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//#define QUICC_ETH_PC_Tx_ENABLE 0x0002 // Tx Enable (TENA)
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//#define QUICC_ETH_PC_Tx_ENABLE 0x0002 // Tx Enable (TENA)
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#define QUICC_ETH_PB_Tx_ENABLE 0x2000 // Tx Enable (TENA)
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#define QUICC_ETH_PB_Tx_ENABLE 0x2000 // Tx Enable (TENA)
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#endif // CYGONCE_DEVS_ADDER_ETH_INL
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#endif // CYGONCE_DEVS_ADDER_ETH_INL
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// ------------------------------------------------------------------------
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// ------------------------------------------------------------------------
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