//==========================================================================
|
//==========================================================================
|
//
|
//
|
// adder_eth.c
|
// adder_eth.c
|
//
|
//
|
// Ethernet device driver specifics for Analogue & Micro Adder (PPC850)
|
// Ethernet device driver specifics for Analogue & Micro Adder (PPC850)
|
//
|
//
|
//==========================================================================
|
//==========================================================================
|
//####ECOSGPLCOPYRIGHTBEGIN####
|
//####ECOSGPLCOPYRIGHTBEGIN####
|
// -------------------------------------------
|
// -------------------------------------------
|
// This file is part of eCos, the Embedded Configurable Operating System.
|
// This file is part of eCos, the Embedded Configurable Operating System.
|
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
|
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
|
// Copyright (C) 2002 Gary Thomas
|
// Copyright (C) 2002 Gary Thomas
|
//
|
//
|
// eCos is free software; you can redistribute it and/or modify it under
|
// eCos is free software; you can redistribute it and/or modify it under
|
// the terms of the GNU General Public License as published by the Free
|
// the terms of the GNU General Public License as published by the Free
|
// Software Foundation; either version 2 or (at your option) any later version.
|
// Software Foundation; either version 2 or (at your option) any later version.
|
//
|
//
|
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
|
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
|
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
|
//
|
// You should have received a copy of the GNU General Public License along
|
// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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//
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// As a special exception, if other files instantiate templates or use macros
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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// in accordance with section (3) of the GNU General Public License.
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//
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//
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// This exception does not invalidate any other reasons why a work based on
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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// this file might be covered by the GNU General Public License.
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//
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
|
//####ECOSGPLCOPYRIGHTEND####
|
//####BSDCOPYRIGHTBEGIN####
|
//####BSDCOPYRIGHTBEGIN####
|
//
|
//
|
// -------------------------------------------
|
// -------------------------------------------
|
//
|
//
|
// Portions of this software may have been derived from OpenBSD or other sources,
|
// Portions of this software may have been derived from OpenBSD or other sources,
|
// and are covered by the appropriate copyright disclaimers included herein.
|
// and are covered by the appropriate copyright disclaimers included herein.
|
//
|
//
|
// -------------------------------------------
|
// -------------------------------------------
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//
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//
|
//####BSDCOPYRIGHTEND####
|
//####BSDCOPYRIGHTEND####
|
//==========================================================================
|
//==========================================================================
|
//#####DESCRIPTIONBEGIN####
|
//#####DESCRIPTIONBEGIN####
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//
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//
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// Author(s): gthomas
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// Author(s): gthomas
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// Contributors: gthomas
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// Contributors: gthomas
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// Date: 2002-11-25
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// Date: 2002-11-25
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// Purpose:
|
// Purpose:
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// Description: platform driver specifics for A&M Adder
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// Description: platform driver specifics for A&M Adder
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//
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//
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//
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//
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//####DESCRIPTIONEND####
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//####DESCRIPTIONEND####
|
//
|
//
|
//==========================================================================
|
//==========================================================================
|
|
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// Ethernet device driver support for PHY on Adder/MPC850
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// Ethernet device driver support for PHY on Adder/MPC850
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|
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#include <pkgconf/system.h>
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#include <pkgconf/system.h>
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#include <cyg/infra/cyg_type.h>
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#include <cyg/infra/cyg_type.h>
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#include <cyg/infra/diag.h>
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#include <cyg/infra/diag.h>
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|
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#include <cyg/hal/hal_arch.h>
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#include <cyg/hal/hal_arch.h>
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#include <cyg/hal/hal_cache.h>
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#include <cyg/hal/hal_cache.h>
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#include <cyg/hal/hal_if.h>
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#include <cyg/hal/hal_if.h>
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#include <cyg/hal/drv_api.h>
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#include <cyg/hal/drv_api.h>
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|
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#include CYGDAT_DEVS_QUICC_ETH_INL // Platform specifics
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#include CYGDAT_DEVS_QUICC_ETH_INL // Platform specifics
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#include <cyg/hal/quicc/ppc8xx.h> // QUICC structure definitions
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#include <cyg/hal/quicc/ppc8xx.h> // QUICC structure definitions
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|
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// MII interface
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// MII interface
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#define MII_Start 0x40000000
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#define MII_Start 0x40000000
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#define MII_Read 0x20000000
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#define MII_Read 0x20000000
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#define MII_Write 0x10000000
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#define MII_Write 0x10000000
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#define MII_Cmd 0x30000000
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#define MII_Cmd 0x30000000
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#define MII_Phy(phy) (phy << 23)
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#define MII_Phy(phy) (phy << 23)
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#define MII_Reg(reg) (reg << 18)
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#define MII_Reg(reg) (reg << 18)
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#define MII_TA 0x00020000
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#define MII_TA 0x00020000
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|
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// Transceiver mode
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// Transceiver mode
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#define PHY_BMCR 0x00 // Register number
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#define PHY_BMCR 0x00 // Register number
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#define PHY_BMCR_RESET 0x8000
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#define PHY_BMCR_RESET 0x8000
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#define PHY_BMCR_LOOPBACK 0x4000
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#define PHY_BMCR_LOOPBACK 0x4000
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#define PHY_BMCR_100MB 0x2000
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#define PHY_BMCR_100MB 0x2000
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#define PHY_BMCR_AUTO_NEG 0x1000
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#define PHY_BMCR_AUTO_NEG 0x1000
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#define PHY_BMCR_POWER_DOWN 0x0800
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#define PHY_BMCR_POWER_DOWN 0x0800
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#define PHY_BMCR_ISOLATE 0x0400
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#define PHY_BMCR_ISOLATE 0x0400
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#define PHY_BMCR_RESTART 0x0200
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#define PHY_BMCR_RESTART 0x0200
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#define PHY_BMCR_FULL_DUPLEX 0x0100
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#define PHY_BMCR_FULL_DUPLEX 0x0100
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#define PHY_BMCR_COLL_TEST 0x0080
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#define PHY_BMCR_COLL_TEST 0x0080
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|
|
#define PHY_BMSR 0x01 // Status register
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#define PHY_BMSR 0x01 // Status register
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#define PHY_BMSR_AUTO_NEG 0x0020
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#define PHY_BMSR_AUTO_NEG 0x0020
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#define PHY_BMSR_LINK 0x0004
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#define PHY_BMSR_LINK 0x0004
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|
|
// Bits in port D - used for 2 wire MII interface
|
// Bits in port D - used for 2 wire MII interface
|
#define MII_DATA 0x1000
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#define MII_DATA 0x1000
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#define MII_CLOCK 0x0800
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#define MII_CLOCK 0x0800
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|
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#define MII_SET_DATA(val) \
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#define MII_SET_DATA(val) \
|
if (val) { \
|
if (val) { \
|
eppc->pio_pddat |= MII_DATA; \
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eppc->pio_pddat |= MII_DATA; \
|
} else { \
|
} else { \
|
eppc->pio_pddat &= ~MII_DATA; \
|
eppc->pio_pddat &= ~MII_DATA; \
|
}
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}
|
|
|
#define MII_GET_DATA() \
|
#define MII_GET_DATA() \
|
((eppc->pio_pddat & MII_DATA) != 0)
|
((eppc->pio_pddat & MII_DATA) != 0)
|
|
|
#define MII_SET_CLOCK(val) \
|
#define MII_SET_CLOCK(val) \
|
if (val) { \
|
if (val) { \
|
eppc->pio_pddat |= MII_CLOCK; \
|
eppc->pio_pddat |= MII_CLOCK; \
|
} else { \
|
} else { \
|
eppc->pio_pddat &= ~MII_CLOCK; \
|
eppc->pio_pddat &= ~MII_CLOCK; \
|
}
|
}
|
|
|
static cyg_uint32
|
static cyg_uint32
|
phy_cmd(cyg_uint32 cmd)
|
phy_cmd(cyg_uint32 cmd)
|
{
|
{
|
volatile EPPC *eppc = (volatile EPPC *)eppc_base();
|
volatile EPPC *eppc = (volatile EPPC *)eppc_base();
|
cyg_uint32 retval;
|
cyg_uint32 retval;
|
int i, off;
|
int i, off;
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bool is_read = ((cmd & MII_Cmd) == MII_Read);
|
bool is_read = ((cmd & MII_Cmd) == MII_Read);
|
|
|
// Set both bits as output
|
// Set both bits as output
|
eppc->pio_pddir |= MII_DATA | MII_CLOCK;
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eppc->pio_pddir |= MII_DATA | MII_CLOCK;
|
|
|
// Preamble
|
// Preamble
|
for (i = 0; i < 32; i++) {
|
for (i = 0; i < 32; i++) {
|
MII_SET_CLOCK(0);
|
MII_SET_CLOCK(0);
|
MII_SET_DATA(1);
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MII_SET_DATA(1);
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CYGACC_CALL_IF_DELAY_US(1);
|
CYGACC_CALL_IF_DELAY_US(1);
|
MII_SET_CLOCK(1);
|
MII_SET_CLOCK(1);
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CYGACC_CALL_IF_DELAY_US(1);
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CYGACC_CALL_IF_DELAY_US(1);
|
}
|
}
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|
|
// Command/data
|
// Command/data
|
for (i = 0, off = 31; i < (is_read ? 14 : 32); i++, --off) {
|
for (i = 0, off = 31; i < (is_read ? 14 : 32); i++, --off) {
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MII_SET_CLOCK(0);
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MII_SET_CLOCK(0);
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MII_SET_DATA((cmd >> off) & 0x00000001);
|
MII_SET_DATA((cmd >> off) & 0x00000001);
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CYGACC_CALL_IF_DELAY_US(1);
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CYGACC_CALL_IF_DELAY_US(1);
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MII_SET_CLOCK(1);
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MII_SET_CLOCK(1);
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CYGACC_CALL_IF_DELAY_US(1);
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CYGACC_CALL_IF_DELAY_US(1);
|
}
|
}
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|
|
retval = cmd;
|
retval = cmd;
|
|
|
// If read, fetch data register
|
// If read, fetch data register
|
if (is_read) {
|
if (is_read) {
|
retval >>= 16;
|
retval >>= 16;
|
|
|
MII_SET_CLOCK(0);
|
MII_SET_CLOCK(0);
|
eppc->pio_pddir &= ~MII_DATA; // Data bit is now input
|
eppc->pio_pddir &= ~MII_DATA; // Data bit is now input
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CYGACC_CALL_IF_DELAY_US(1);
|
CYGACC_CALL_IF_DELAY_US(1);
|
MII_SET_CLOCK(1);
|
MII_SET_CLOCK(1);
|
CYGACC_CALL_IF_DELAY_US(1);
|
CYGACC_CALL_IF_DELAY_US(1);
|
MII_SET_CLOCK(0);
|
MII_SET_CLOCK(0);
|
CYGACC_CALL_IF_DELAY_US(1);
|
CYGACC_CALL_IF_DELAY_US(1);
|
|
|
for (i = 0, off = 15; i < 16; i++, off--) {
|
for (i = 0, off = 15; i < 16; i++, off--) {
|
MII_SET_CLOCK(1);
|
MII_SET_CLOCK(1);
|
retval <<= 1;
|
retval <<= 1;
|
retval |= MII_GET_DATA();
|
retval |= MII_GET_DATA();
|
CYGACC_CALL_IF_DELAY_US(1);
|
CYGACC_CALL_IF_DELAY_US(1);
|
MII_SET_CLOCK(0);
|
MII_SET_CLOCK(0);
|
CYGACC_CALL_IF_DELAY_US(1);
|
CYGACC_CALL_IF_DELAY_US(1);
|
}
|
}
|
}
|
}
|
|
|
// Set both bits as output
|
// Set both bits as output
|
eppc->pio_pddir |= MII_DATA | MII_CLOCK;
|
eppc->pio_pddir |= MII_DATA | MII_CLOCK;
|
|
|
// Postamble
|
// Postamble
|
for (i = 0; i < 32; i++) {
|
for (i = 0; i < 32; i++) {
|
MII_SET_CLOCK(0);
|
MII_SET_CLOCK(0);
|
MII_SET_DATA(1);
|
MII_SET_DATA(1);
|
CYGACC_CALL_IF_DELAY_US(1);
|
CYGACC_CALL_IF_DELAY_US(1);
|
MII_SET_CLOCK(1);
|
MII_SET_CLOCK(1);
|
CYGACC_CALL_IF_DELAY_US(1);
|
CYGACC_CALL_IF_DELAY_US(1);
|
}
|
}
|
|
|
return retval;
|
return retval;
|
}
|
}
|
|
|
//
|
//
|
// PHY unit access (via MII channel)
|
// PHY unit access (via MII channel)
|
//
|
//
|
static void
|
static void
|
phy_write(int reg, int addr, unsigned short data)
|
phy_write(int reg, int addr, unsigned short data)
|
{
|
{
|
phy_cmd(MII_Start | MII_Write | MII_Phy(addr) | MII_Reg(reg) | MII_TA | data);
|
phy_cmd(MII_Start | MII_Write | MII_Phy(addr) | MII_Reg(reg) | MII_TA | data);
|
}
|
}
|
|
|
static bool
|
static bool
|
phy_read(int reg, int addr, unsigned short *val)
|
phy_read(int reg, int addr, unsigned short *val)
|
{
|
{
|
cyg_uint32 ret;
|
cyg_uint32 ret;
|
|
|
ret = phy_cmd(MII_Start | MII_Read | MII_Phy(addr) | MII_Reg(reg) | MII_TA);
|
ret = phy_cmd(MII_Start | MII_Read | MII_Phy(addr) | MII_Reg(reg) | MII_TA);
|
*val = ret;
|
*val = ret;
|
return true;
|
return true;
|
}
|
}
|
|
|
bool
|
bool
|
_adder_reset_phy(void)
|
_adder_reset_phy(void)
|
{
|
{
|
volatile EPPC *eppc = (volatile EPPC *)eppc_base();
|
volatile EPPC *eppc = (volatile EPPC *)eppc_base();
|
int phy_timeout = 5*1000; // Wait 5 seconds max for link to clear
|
int phy_timeout = 5*1000; // Wait 5 seconds max for link to clear
|
bool phy_ok;
|
bool phy_ok;
|
unsigned short phy_state = 0;
|
unsigned short phy_state = 0;
|
int phy_unit = -1;
|
int phy_unit = -1;
|
int i;
|
int i;
|
|
|
// Reset PHY (transceiver)
|
// Reset PHY (transceiver)
|
eppc->pip_pbdat &= ~0x00004000; // Reset PHY chip
|
eppc->pip_pbdat &= ~0x00004000; // Reset PHY chip
|
CYGACC_CALL_IF_DELAY_US(15000); // > 10ms
|
CYGACC_CALL_IF_DELAY_US(15000); // > 10ms
|
eppc->pip_pbdat |= 0x00004000; // Enable PHY chip
|
eppc->pip_pbdat |= 0x00004000; // Enable PHY chip
|
|
|
phy_ok = false;
|
phy_ok = false;
|
|
|
// Try and discover how this PHY is wired
|
// Try and discover how this PHY is wired
|
for (i = 0; i < 0x20; i++) {
|
for (i = 0; i < 0x20; i++) {
|
phy_read(PHY_BMCR, i, &phy_state);
|
phy_read(PHY_BMCR, i, &phy_state);
|
if ((phy_state & PHY_BMCR_RESET) == 0) {
|
if ((phy_state & PHY_BMCR_RESET) == 0) {
|
phy_unit = i;
|
phy_unit = i;
|
break;
|
break;
|
}
|
}
|
}
|
}
|
if (phy_unit < 0) {
|
if (phy_unit < 0) {
|
diag_printf("QUICC ETH - Can't locate PHY\n");
|
diag_printf("QUICC ETH - Can't locate PHY\n");
|
return false;
|
return false;
|
} else {
|
} else {
|
#if 0
|
#if 0
|
diag_printf("QUICC ETH - using PHY %d\n", phy_unit);
|
diag_printf("QUICC ETH - using PHY %d\n", phy_unit);
|
#endif
|
#endif
|
}
|
}
|
if (phy_read(PHY_BMSR, phy_unit, &phy_state)) {
|
if (phy_read(PHY_BMSR, phy_unit, &phy_state)) {
|
if ((phy_state & PHY_BMSR_LINK) != PHY_BMSR_LINK) {
|
if ((phy_state & PHY_BMSR_LINK) != PHY_BMSR_LINK) {
|
unsigned short reset_mode;
|
unsigned short reset_mode;
|
phy_write(PHY_BMCR, phy_unit, PHY_BMCR_RESET);
|
phy_write(PHY_BMCR, phy_unit, PHY_BMCR_RESET);
|
for (i = 0; i < 10; i++) {
|
for (i = 0; i < 10; i++) {
|
phy_ok = phy_read(PHY_BMCR, phy_unit, &phy_state);
|
phy_ok = phy_read(PHY_BMCR, phy_unit, &phy_state);
|
if (!phy_ok) break;
|
if (!phy_ok) break;
|
if (!(phy_state & PHY_BMCR_RESET)) break;
|
if (!(phy_state & PHY_BMCR_RESET)) break;
|
}
|
}
|
if (!phy_ok || (phy_state & PHY_BMCR_RESET)) {
|
if (!phy_ok || (phy_state & PHY_BMCR_RESET)) {
|
diag_printf("QUICC/ETH: Can't get PHY unit to soft reset: %x\n", phy_state);
|
diag_printf("QUICC/ETH: Can't get PHY unit to soft reset: %x\n", phy_state);
|
return false;
|
return false;
|
}
|
}
|
reset_mode = PHY_BMCR_RESTART | PHY_BMCR_AUTO_NEG | PHY_BMCR_FULL_DUPLEX;
|
reset_mode = PHY_BMCR_RESTART | PHY_BMCR_AUTO_NEG | PHY_BMCR_FULL_DUPLEX;
|
phy_write(PHY_BMCR, phy_unit, reset_mode);
|
phy_write(PHY_BMCR, phy_unit, reset_mode);
|
while (phy_timeout-- >= 0) {
|
while (phy_timeout-- >= 0) {
|
phy_ok = phy_read(PHY_BMSR, phy_unit, &phy_state);
|
phy_ok = phy_read(PHY_BMSR, phy_unit, &phy_state);
|
if (phy_ok && (phy_state & PHY_BMSR_LINK)) {
|
if (phy_ok && (phy_state & PHY_BMSR_LINK)) {
|
break;
|
break;
|
} else {
|
} else {
|
CYGACC_CALL_IF_DELAY_US(10000); // 10ms
|
CYGACC_CALL_IF_DELAY_US(10000); // 10ms
|
}
|
}
|
}
|
}
|
if (phy_timeout <= 0) {
|
if (phy_timeout <= 0) {
|
diag_printf("** QUICC/ETH Warning: PHY LINK UP failed\n");
|
diag_printf("** QUICC/ETH Warning: PHY LINK UP failed\n");
|
}
|
}
|
}
|
}
|
else {
|
else {
|
diag_printf("** QUICC/ETH Info: PHY LINK already UP \n");
|
diag_printf("** QUICC/ETH Info: PHY LINK already UP \n");
|
}
|
}
|
}
|
}
|
|
|
return phy_ok;
|
return phy_ok;
|
}
|
}
|
|
|
|
|
