//####ECOSGPLCOPYRIGHTBEGIN####
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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// Copyright (C) 2002 Gary Thomas
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// Copyright (C) 2002 Gary Thomas
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//
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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//
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// As a special exception, if other files instantiate templates or use macros
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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// in accordance with section (3) of the GNU General Public License.
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//
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//
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// This exception does not invalidate any other reasons why a work based on
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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// this file might be covered by the GNU General Public License.
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//
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//####ECOSGPLCOPYRIGHTEND####
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/*------------------------------------------------------------------
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/*------------------------------------------------------------------
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*
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*
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* FILE: EnetPHY.c
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* FILE: EnetPHY.c
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*
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*
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* DESCRIPTION: LXT970a driver header file
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* DESCRIPTION: LXT970a driver header file
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*
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*
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*
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*
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* Modified for MPC8260 VADS board
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* Modified for MPC8260 VADS board
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*-------------------------------------------------------------------*/
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*-------------------------------------------------------------------*/
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#ifndef _EnetPHY_H
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#ifndef _EnetPHY_H
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#define _EnetPHY_H
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#define _EnetPHY_H
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#include "types.h"
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#include "types.h"
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// Board control and status registers
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// Board control and status registers
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typedef struct bcsr {
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typedef struct bcsr {
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UINT32 bcsr0;
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UINT32 bcsr0;
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UINT32 bcsr1;
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UINT32 bcsr1;
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UINT32 bcsr2;
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UINT32 bcsr2;
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UINT32 bcsr3;
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UINT32 bcsr3;
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} t_BCSR;
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} t_BCSR;
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// Fast ethernet enable/reset pins on bcsr
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// Fast ethernet enable/reset pins on bcsr
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#define FETHIEN_ 0x08000000
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#define FETHIEN_ 0x08000000
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#define FETHRST_ 0x04000000
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#define FETHRST_ 0x04000000
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/**************************/
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/**************************/
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/* The API for PHY Device */
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/* The API for PHY Device */
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/**************************/
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/**************************/
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void EnableResetPHY(volatile t_BCSR *pBCSR);
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void EnableResetPHY(volatile t_BCSR *pBCSR);
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UINT16 InitEthernetPHY(VUINT32* pdir, VUINT32* pdat, UINT16 link);
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UINT16 InitEthernetPHY(VUINT32* pdir, VUINT32* pdat, UINT16 link);
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UINT16 EthernetPHYInterruptHandler(void);
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UINT16 EthernetPHYInterruptHandler(void);
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void EnablePHYinterrupt(UINT8 enable);
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void EnablePHYinterrupt(UINT8 enable);
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UINT16 LinkTestPHY(void);
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UINT16 LinkTestPHY(void);
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typedef enum MDIORW {READ, WRITE} MDIORW;
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typedef enum MDIORW {READ, WRITE} MDIORW;
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#define LINKERROR 0xFFFF
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#define LINKERROR 0xFFFF
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#define NOTLINKED 0x0000
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#define NOTLINKED 0x0000
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#define TEN_HD 0x0020
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#define TEN_HD 0x0020
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#define TEN_FD 0x0040
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#define TEN_FD 0x0040
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#define HUNDRED_HD 0x0080
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#define HUNDRED_HD 0x0080
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#define HUNDRED_FD 0x0100
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#define HUNDRED_FD 0x0100
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#define MD_TEST_FRAME 0xDEAD
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#define MD_TEST_FRAME 0xDEAD
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//8260 VADS Pin Connections
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//8260 VADS Pin Connections
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#define MDIO_PIN_MASK 0x00400000 //PC9 for 8260 VADS
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#define MDIO_PIN_MASK 0x00400000 //PC9 for 8260 VADS
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#define MDC_PIN_MASK 0x00200000 //PC10 for 8260 VADS
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#define MDC_PIN_MASK 0x00200000 //PC10 for 8260 VADS
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//#define MDIO_PIN_MASK 0x00000200 //PC9 for 8260 VADS
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//#define MDIO_PIN_MASK 0x00000200 //PC9 for 8260 VADS
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//#define MDC_PIN_MASK 0x00000400 //PC10 for 8260 VADS
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//#define MDC_PIN_MASK 0x00000400 //PC10 for 8260 VADS
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//IEEE 802.3 PHY Register Definitions
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//IEEE 802.3 PHY Register Definitions
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#define CONTROL_REG 0
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#define CONTROL_REG 0
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#define STATUS_REG 1
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#define STATUS_REG 1
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#define PHY_ID_REG_A 2
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#define PHY_ID_REG_A 2
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#define PHY_ID_REG_B 3
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#define PHY_ID_REG_B 3
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#define AUTONEG_AD_REG 4
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#define AUTONEG_AD_REG 4
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#define AUTONEG_LINKPARTNER_REG 5
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#define AUTONEG_LINKPARTNER_REG 5
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#define AUTONEG_EXP_REG 6
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#define AUTONEG_EXP_REG 6
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//LXT970a Specific Register Definitions
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//LXT970a Specific Register Definitions
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#define MIRROR_REG 16
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#define MIRROR_REG 16
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#define INT_EN_REG 17
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#define INT_EN_REG 17
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#define INT_STAT_REG 18
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#define INT_STAT_REG 18
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#define CONFIG_REG 19
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#define CONFIG_REG 19
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#define CHIP_STAT_REG 20
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#define CHIP_STAT_REG 20
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//Clock Timing Control
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//Clock Timing Control
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#define MDC_HOLD_TIME 50
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#define MDC_HOLD_TIME 50
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#endif
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#endif
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