/* Common target dependent code for GDB on ARM systems.
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/* Common target dependent code for GDB on ARM systems.
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Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1997, 1998, 1999, 2000
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Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1997, 1998, 1999, 2000
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Free Software Foundation, Inc.
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Free Software Foundation, Inc.
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This file is part of GDB.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330,
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Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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Boston, MA 02111-1307, USA. */
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#include "defs.h"
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#include "defs.h"
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#include "frame.h"
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#include "frame.h"
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#include "inferior.h"
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#include "inferior.h"
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#include "gdbcmd.h"
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#include "gdbcmd.h"
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#include "gdbcore.h"
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#include "gdbcore.h"
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#include "symfile.h"
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#include "symfile.h"
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#include "gdb_string.h"
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#include "gdb_string.h"
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#include "coff/internal.h" /* Internal format of COFF symbols in BFD */
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#include "coff/internal.h" /* Internal format of COFF symbols in BFD */
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#include "dis-asm.h" /* For register flavors. */
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#include "dis-asm.h" /* For register flavors. */
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#include <ctype.h> /* for isupper () */
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#include <ctype.h> /* for isupper () */
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extern void _initialize_arm_tdep (void);
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extern void _initialize_arm_tdep (void);
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/* Number of different reg name sets (options). */
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/* Number of different reg name sets (options). */
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static int num_flavor_options;
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static int num_flavor_options;
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/* We have more registers than the disassembler as gdb can print the value
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/* We have more registers than the disassembler as gdb can print the value
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of special registers as well.
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of special registers as well.
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The general register names are overwritten by whatever is being used by
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The general register names are overwritten by whatever is being used by
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the disassembler at the moment. We also adjust the case of cpsr and fps. */
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the disassembler at the moment. We also adjust the case of cpsr and fps. */
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/* Initial value: Register names used in ARM's ISA documentation. */
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/* Initial value: Register names used in ARM's ISA documentation. */
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static char * arm_register_name_strings[] =
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static char * arm_register_name_strings[] =
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{"r0", "r1", "r2", "r3", /* 0 1 2 3 */
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{"r0", "r1", "r2", "r3", /* 0 1 2 3 */
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"r4", "r5", "r6", "r7", /* 4 5 6 7 */
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"r4", "r5", "r6", "r7", /* 4 5 6 7 */
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"r8", "r9", "r10", "r11", /* 8 9 10 11 */
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"r8", "r9", "r10", "r11", /* 8 9 10 11 */
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"r12", "sp", "lr", "pc", /* 12 13 14 15 */
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"r12", "sp", "lr", "pc", /* 12 13 14 15 */
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"f0", "f1", "f2", "f3", /* 16 17 18 19 */
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"f0", "f1", "f2", "f3", /* 16 17 18 19 */
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"f4", "f5", "f6", "f7", /* 20 21 22 23 */
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"f4", "f5", "f6", "f7", /* 20 21 22 23 */
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"fps", "cpsr" }; /* 24 25 */
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"fps", "cpsr" }; /* 24 25 */
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char **arm_register_names = arm_register_name_strings;
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char **arm_register_names = arm_register_name_strings;
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/* Valid register name flavors. */
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/* Valid register name flavors. */
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static char **valid_flavors;
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static char **valid_flavors;
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/* Disassembly flavor to use. Default to "std" register names. */
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/* Disassembly flavor to use. Default to "std" register names. */
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static char *disassembly_flavor;
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static char *disassembly_flavor;
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static int current_option; /* Index to that option in the opcodes table. */
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static int current_option; /* Index to that option in the opcodes table. */
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/* This is used to keep the bfd arch_info in sync with the disassembly
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/* This is used to keep the bfd arch_info in sync with the disassembly
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flavor. */
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flavor. */
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static void set_disassembly_flavor_sfunc(char *, int,
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static void set_disassembly_flavor_sfunc(char *, int,
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struct cmd_list_element *);
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struct cmd_list_element *);
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static void set_disassembly_flavor (void);
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static void set_disassembly_flavor (void);
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static void convert_from_extended (void *ptr, void *dbl);
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static void convert_from_extended (void *ptr, void *dbl);
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/* Define other aspects of the stack frame. We keep the offsets of
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/* Define other aspects of the stack frame. We keep the offsets of
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all saved registers, 'cause we need 'em a lot! We also keep the
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all saved registers, 'cause we need 'em a lot! We also keep the
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current size of the stack frame, and the offset of the frame
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current size of the stack frame, and the offset of the frame
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pointer from the stack pointer (for frameless functions, and when
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pointer from the stack pointer (for frameless functions, and when
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we're still in the prologue of a function with a frame) */
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we're still in the prologue of a function with a frame) */
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struct frame_extra_info
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struct frame_extra_info
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{
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{
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struct frame_saved_regs fsr;
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struct frame_saved_regs fsr;
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int framesize;
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int framesize;
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int frameoffset;
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int frameoffset;
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int framereg;
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int framereg;
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};
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};
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/* Addresses for calling Thumb functions have the bit 0 set.
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/* Addresses for calling Thumb functions have the bit 0 set.
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Here are some macros to test, set, or clear bit 0 of addresses. */
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Here are some macros to test, set, or clear bit 0 of addresses. */
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#define IS_THUMB_ADDR(addr) ((addr) & 1)
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#define IS_THUMB_ADDR(addr) ((addr) & 1)
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#define MAKE_THUMB_ADDR(addr) ((addr) | 1)
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#define MAKE_THUMB_ADDR(addr) ((addr) | 1)
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#define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
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#define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
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#define SWAP_TARGET_AND_HOST(buffer,len) \
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#define SWAP_TARGET_AND_HOST(buffer,len) \
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do \
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do \
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{ \
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{ \
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if (TARGET_BYTE_ORDER != HOST_BYTE_ORDER) \
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if (TARGET_BYTE_ORDER != HOST_BYTE_ORDER) \
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{ \
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{ \
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char tmp; \
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char tmp; \
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char *p = (char *)(buffer); \
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char *p = (char *)(buffer); \
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char *q = ((char *)(buffer)) + len - 1; \
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char *q = ((char *)(buffer)) + len - 1; \
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for (; p < q; p++, q--) \
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for (; p < q; p++, q--) \
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{ \
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{ \
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tmp = *q; \
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tmp = *q; \
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*q = *p; \
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*q = *p; \
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*p = tmp; \
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*p = tmp; \
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} \
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} \
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} \
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} \
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} \
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} \
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while (0)
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while (0)
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/* Will a function return an aggregate type in memory or in a
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/* Will a function return an aggregate type in memory or in a
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register? Return 0 if an aggregate type can be returned in a
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register? Return 0 if an aggregate type can be returned in a
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register, 1 if it must be returned in memory. */
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register, 1 if it must be returned in memory. */
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int
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int
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arm_use_struct_convention (int gcc_p, struct type *type)
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arm_use_struct_convention (int gcc_p, struct type *type)
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{
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{
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int nRc;
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int nRc;
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register enum type_code code;
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register enum type_code code;
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/* In the ARM ABI, "integer" like aggregate types are returned in
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/* In the ARM ABI, "integer" like aggregate types are returned in
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registers. For an aggregate type to be integer like, its size
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registers. For an aggregate type to be integer like, its size
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must be less than or equal to REGISTER_SIZE and the offset of
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must be less than or equal to REGISTER_SIZE and the offset of
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each addressable subfield must be zero. Note that bit fields are
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each addressable subfield must be zero. Note that bit fields are
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not addressable, and all addressable subfields of unions always
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not addressable, and all addressable subfields of unions always
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start at offset zero.
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start at offset zero.
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This function is based on the behaviour of GCC 2.95.1.
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This function is based on the behaviour of GCC 2.95.1.
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See: gcc/arm.c: arm_return_in_memory() for details.
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See: gcc/arm.c: arm_return_in_memory() for details.
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Note: All versions of GCC before GCC 2.95.2 do not set up the
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Note: All versions of GCC before GCC 2.95.2 do not set up the
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parameters correctly for a function returning the following
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parameters correctly for a function returning the following
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structure: struct { float f;}; This should be returned in memory,
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structure: struct { float f;}; This should be returned in memory,
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not a register. Richard Earnshaw sent me a patch, but I do not
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not a register. Richard Earnshaw sent me a patch, but I do not
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know of any way to detect if a function like the above has been
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know of any way to detect if a function like the above has been
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compiled with the correct calling convention. */
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compiled with the correct calling convention. */
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/* All aggregate types that won't fit in a register must be returned
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/* All aggregate types that won't fit in a register must be returned
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in memory. */
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in memory. */
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if (TYPE_LENGTH (type) > REGISTER_SIZE)
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if (TYPE_LENGTH (type) > REGISTER_SIZE)
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{
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{
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return 1;
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return 1;
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}
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}
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/* The only aggregate types that can be returned in a register are
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/* The only aggregate types that can be returned in a register are
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structs and unions. Arrays must be returned in memory. */
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structs and unions. Arrays must be returned in memory. */
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code = TYPE_CODE (type);
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code = TYPE_CODE (type);
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if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
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if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
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{
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{
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return 1;
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return 1;
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}
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}
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/* Assume all other aggregate types can be returned in a register.
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/* Assume all other aggregate types can be returned in a register.
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Run a check for structures, unions and arrays. */
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Run a check for structures, unions and arrays. */
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nRc = 0;
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nRc = 0;
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if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
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if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
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{
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{
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int i;
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int i;
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/* Need to check if this struct/union is "integer" like. For
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/* Need to check if this struct/union is "integer" like. For
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this to be true, its size must be less than or equal to
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this to be true, its size must be less than or equal to
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REGISTER_SIZE and the offset of each addressable subfield
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REGISTER_SIZE and the offset of each addressable subfield
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must be zero. Note that bit fields are not addressable, and
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must be zero. Note that bit fields are not addressable, and
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unions always start at offset zero. If any of the subfields
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unions always start at offset zero. If any of the subfields
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is a floating point type, the struct/union cannot be an
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is a floating point type, the struct/union cannot be an
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integer type. */
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integer type. */
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/* For each field in the object, check:
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/* For each field in the object, check:
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1) Is it FP? --> yes, nRc = 1;
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1) Is it FP? --> yes, nRc = 1;
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2) Is it addressable (bitpos != 0) and
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2) Is it addressable (bitpos != 0) and
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not packed (bitsize == 0)?
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not packed (bitsize == 0)?
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--> yes, nRc = 1
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--> yes, nRc = 1
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*/
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*/
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for (i = 0; i < TYPE_NFIELDS (type); i++)
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for (i = 0; i < TYPE_NFIELDS (type); i++)
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{
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{
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enum type_code field_type_code;
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enum type_code field_type_code;
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field_type_code = TYPE_CODE (TYPE_FIELD_TYPE (type, i));
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field_type_code = TYPE_CODE (TYPE_FIELD_TYPE (type, i));
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/* Is it a floating point type field? */
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/* Is it a floating point type field? */
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if (field_type_code == TYPE_CODE_FLT)
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if (field_type_code == TYPE_CODE_FLT)
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{
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{
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nRc = 1;
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nRc = 1;
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break;
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break;
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}
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}
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/* If bitpos != 0, then we have to care about it. */
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/* If bitpos != 0, then we have to care about it. */
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if (TYPE_FIELD_BITPOS (type, i) != 0)
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if (TYPE_FIELD_BITPOS (type, i) != 0)
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{
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{
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/* Bitfields are not addressable. If the field bitsize is
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/* Bitfields are not addressable. If the field bitsize is
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zero, then the field is not packed. Hence it cannot be
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zero, then the field is not packed. Hence it cannot be
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a bitfield or any other packed type. */
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a bitfield or any other packed type. */
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if (TYPE_FIELD_BITSIZE (type, i) == 0)
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if (TYPE_FIELD_BITSIZE (type, i) == 0)
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{
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{
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nRc = 1;
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nRc = 1;
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break;
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break;
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}
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}
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}
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}
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}
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}
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}
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}
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return nRc;
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return nRc;
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}
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}
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int
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int
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arm_frame_chain_valid (CORE_ADDR chain, struct frame_info *thisframe)
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arm_frame_chain_valid (CORE_ADDR chain, struct frame_info *thisframe)
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{
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{
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return (chain != 0 && (FRAME_SAVED_PC (thisframe) >= LOWEST_PC));
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return (chain != 0 && (FRAME_SAVED_PC (thisframe) >= LOWEST_PC));
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}
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}
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/* Set to true if the 32-bit mode is in use. */
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/* Set to true if the 32-bit mode is in use. */
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int arm_apcs_32 = 1;
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int arm_apcs_32 = 1;
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/* Flag set by arm_fix_call_dummy that tells whether the target
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/* Flag set by arm_fix_call_dummy that tells whether the target
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function is a Thumb function. This flag is checked by
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function is a Thumb function. This flag is checked by
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arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
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arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
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its use in valops.c) to pass the function address as an additional
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its use in valops.c) to pass the function address as an additional
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parameter. */
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parameter. */
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static int target_is_thumb;
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static int target_is_thumb;
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|
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/* Flag set by arm_fix_call_dummy that tells whether the calling
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/* Flag set by arm_fix_call_dummy that tells whether the calling
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function is a Thumb function. This flag is checked by
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function is a Thumb function. This flag is checked by
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arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */
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arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */
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static int caller_is_thumb;
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static int caller_is_thumb;
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|
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/* Determine if the program counter specified in MEMADDR is in a Thumb
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/* Determine if the program counter specified in MEMADDR is in a Thumb
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function. */
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function. */
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int
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int
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arm_pc_is_thumb (bfd_vma memaddr)
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arm_pc_is_thumb (bfd_vma memaddr)
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{
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{
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struct minimal_symbol *sym;
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struct minimal_symbol *sym;
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/* If bit 0 of the address is set, assume this is a Thumb address. */
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/* If bit 0 of the address is set, assume this is a Thumb address. */
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if (IS_THUMB_ADDR (memaddr))
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if (IS_THUMB_ADDR (memaddr))
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return 1;
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return 1;
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|
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/* Thumb functions have a "special" bit set in minimal symbols. */
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/* Thumb functions have a "special" bit set in minimal symbols. */
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sym = lookup_minimal_symbol_by_pc (memaddr);
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sym = lookup_minimal_symbol_by_pc (memaddr);
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if (sym)
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if (sym)
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{
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{
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return (MSYMBOL_IS_SPECIAL (sym));
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return (MSYMBOL_IS_SPECIAL (sym));
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}
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}
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else
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else
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{
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{
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return 0;
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return 0;
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}
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}
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}
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}
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/* Determine if the program counter specified in MEMADDR is in a call
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/* Determine if the program counter specified in MEMADDR is in a call
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dummy being called from a Thumb function. */
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dummy being called from a Thumb function. */
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|
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int
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int
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arm_pc_is_thumb_dummy (bfd_vma memaddr)
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arm_pc_is_thumb_dummy (bfd_vma memaddr)
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{
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{
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CORE_ADDR sp = read_sp ();
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CORE_ADDR sp = read_sp ();
|
|
|
/* FIXME: Until we switch for the new call dummy macros, this heuristic
|
/* FIXME: Until we switch for the new call dummy macros, this heuristic
|
is the best we can do. We are trying to determine if the pc is on
|
is the best we can do. We are trying to determine if the pc is on
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the stack, which (hopefully) will only happen in a call dummy.
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the stack, which (hopefully) will only happen in a call dummy.
|
We hope the current stack pointer is not so far alway from the dummy
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We hope the current stack pointer is not so far alway from the dummy
|
frame location (true if we have not pushed large data structures or
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frame location (true if we have not pushed large data structures or
|
gone too many levels deep) and that our 1024 is not enough to consider
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gone too many levels deep) and that our 1024 is not enough to consider
|
code regions as part of the stack (true for most practical purposes) */
|
code regions as part of the stack (true for most practical purposes) */
|
if (PC_IN_CALL_DUMMY (memaddr, sp, sp + 1024))
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if (PC_IN_CALL_DUMMY (memaddr, sp, sp + 1024))
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return caller_is_thumb;
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return caller_is_thumb;
|
else
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else
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return 0;
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return 0;
|
}
|
}
|
|
|
CORE_ADDR
|
CORE_ADDR
|
arm_addr_bits_remove (CORE_ADDR val)
|
arm_addr_bits_remove (CORE_ADDR val)
|
{
|
{
|
if (arm_pc_is_thumb (val))
|
if (arm_pc_is_thumb (val))
|
return (val & (arm_apcs_32 ? 0xfffffffe : 0x03fffffe));
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return (val & (arm_apcs_32 ? 0xfffffffe : 0x03fffffe));
|
else
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else
|
return (val & (arm_apcs_32 ? 0xfffffffc : 0x03fffffc));
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return (val & (arm_apcs_32 ? 0xfffffffc : 0x03fffffc));
|
}
|
}
|
|
|
CORE_ADDR
|
CORE_ADDR
|
arm_saved_pc_after_call (struct frame_info *frame)
|
arm_saved_pc_after_call (struct frame_info *frame)
|
{
|
{
|
return ADDR_BITS_REMOVE (read_register (LR_REGNUM));
|
return ADDR_BITS_REMOVE (read_register (LR_REGNUM));
|
}
|
}
|
|
|
int
|
int
|
arm_frameless_function_invocation (struct frame_info *fi)
|
arm_frameless_function_invocation (struct frame_info *fi)
|
{
|
{
|
CORE_ADDR func_start, after_prologue;
|
CORE_ADDR func_start, after_prologue;
|
int frameless;
|
int frameless;
|
|
|
func_start = (get_pc_function_start ((fi)->pc) + FUNCTION_START_OFFSET);
|
func_start = (get_pc_function_start ((fi)->pc) + FUNCTION_START_OFFSET);
|
after_prologue = SKIP_PROLOGUE (func_start);
|
after_prologue = SKIP_PROLOGUE (func_start);
|
|
|
/* There are some frameless functions whose first two instructions
|
/* There are some frameless functions whose first two instructions
|
follow the standard APCS form, in which case after_prologue will
|
follow the standard APCS form, in which case after_prologue will
|
be func_start + 8. */
|
be func_start + 8. */
|
|
|
frameless = (after_prologue < func_start + 12);
|
frameless = (after_prologue < func_start + 12);
|
return frameless;
|
return frameless;
|
}
|
}
|
|
|
/* A typical Thumb prologue looks like this:
|
/* A typical Thumb prologue looks like this:
|
push {r7, lr}
|
push {r7, lr}
|
add sp, sp, #-28
|
add sp, sp, #-28
|
add r7, sp, #12
|
add r7, sp, #12
|
Sometimes the latter instruction may be replaced by:
|
Sometimes the latter instruction may be replaced by:
|
mov r7, sp
|
mov r7, sp
|
|
|
or like this:
|
or like this:
|
push {r7, lr}
|
push {r7, lr}
|
mov r7, sp
|
mov r7, sp
|
sub sp, #12
|
sub sp, #12
|
|
|
or, on tpcs, like this:
|
or, on tpcs, like this:
|
sub sp,#16
|
sub sp,#16
|
push {r7, lr}
|
push {r7, lr}
|
(many instructions)
|
(many instructions)
|
mov r7, sp
|
mov r7, sp
|
sub sp, #12
|
sub sp, #12
|
|
|
There is always one instruction of three classes:
|
There is always one instruction of three classes:
|
1 - push
|
1 - push
|
2 - setting of r7
|
2 - setting of r7
|
3 - adjusting of sp
|
3 - adjusting of sp
|
|
|
When we have found at least one of each class we are done with the prolog.
|
When we have found at least one of each class we are done with the prolog.
|
Note that the "sub sp, #NN" before the push does not count.
|
Note that the "sub sp, #NN" before the push does not count.
|
*/
|
*/
|
|
|
static CORE_ADDR
|
static CORE_ADDR
|
thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end)
|
thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end)
|
{
|
{
|
CORE_ADDR current_pc;
|
CORE_ADDR current_pc;
|
int findmask = 0; /* findmask:
|
int findmask = 0; /* findmask:
|
bit 0 - push { rlist }
|
bit 0 - push { rlist }
|
bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
|
bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
|
bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
|
bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
|
*/
|
*/
|
|
|
for (current_pc = pc; current_pc + 2 < func_end && current_pc < pc + 40; current_pc += 2)
|
for (current_pc = pc; current_pc + 2 < func_end && current_pc < pc + 40; current_pc += 2)
|
{
|
{
|
unsigned short insn = read_memory_unsigned_integer (current_pc, 2);
|
unsigned short insn = read_memory_unsigned_integer (current_pc, 2);
|
|
|
if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
|
if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
|
{
|
{
|
findmask |= 1; /* push found */
|
findmask |= 1; /* push found */
|
}
|
}
|
else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
|
else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
|
{
|
{
|
if ((findmask & 1) == 0) /* before push ? */
|
if ((findmask & 1) == 0) /* before push ? */
|
continue;
|
continue;
|
else
|
else
|
findmask |= 4; /* add/sub sp found */
|
findmask |= 4; /* add/sub sp found */
|
}
|
}
|
else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
|
else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
|
{
|
{
|
findmask |= 2; /* setting of r7 found */
|
findmask |= 2; /* setting of r7 found */
|
}
|
}
|
else if (insn == 0x466f) /* mov r7, sp */
|
else if (insn == 0x466f) /* mov r7, sp */
|
{
|
{
|
findmask |= 2; /* setting of r7 found */
|
findmask |= 2; /* setting of r7 found */
|
}
|
}
|
else
|
else
|
continue; /* something in the prolog that we don't care about or some
|
continue; /* something in the prolog that we don't care about or some
|
instruction from outside the prolog scheduled here for optimization */
|
instruction from outside the prolog scheduled here for optimization */
|
}
|
}
|
|
|
return current_pc;
|
return current_pc;
|
}
|
}
|
|
|
/* The APCS (ARM Procedure Call Standard) defines the following
|
/* The APCS (ARM Procedure Call Standard) defines the following
|
prologue:
|
prologue:
|
|
|
mov ip, sp
|
mov ip, sp
|
[stmfd sp!, {a1,a2,a3,a4}]
|
[stmfd sp!, {a1,a2,a3,a4}]
|
stmfd sp!, {...,fp,ip,lr,pc}
|
stmfd sp!, {...,fp,ip,lr,pc}
|
[stfe f7, [sp, #-12]!]
|
[stfe f7, [sp, #-12]!]
|
[stfe f6, [sp, #-12]!]
|
[stfe f6, [sp, #-12]!]
|
[stfe f5, [sp, #-12]!]
|
[stfe f5, [sp, #-12]!]
|
[stfe f4, [sp, #-12]!]
|
[stfe f4, [sp, #-12]!]
|
sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
|
sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
|
|
|
CORE_ADDR
|
CORE_ADDR
|
arm_skip_prologue (CORE_ADDR pc)
|
arm_skip_prologue (CORE_ADDR pc)
|
{
|
{
|
unsigned long inst;
|
unsigned long inst;
|
CORE_ADDR skip_pc;
|
CORE_ADDR skip_pc;
|
CORE_ADDR func_addr, func_end;
|
CORE_ADDR func_addr, func_end;
|
struct symtab_and_line sal;
|
struct symtab_and_line sal;
|
|
|
/* See what the symbol table says. */
|
/* See what the symbol table says. */
|
|
|
if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
|
if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
|
{
|
{
|
sal = find_pc_line (func_addr, 0);
|
sal = find_pc_line (func_addr, 0);
|
if ((sal.line != 0) && (sal.end < func_end))
|
if ((sal.line != 0) && (sal.end < func_end))
|
return sal.end;
|
return sal.end;
|
}
|
}
|
|
|
/* Check if this is Thumb code. */
|
/* Check if this is Thumb code. */
|
if (arm_pc_is_thumb (pc))
|
if (arm_pc_is_thumb (pc))
|
return thumb_skip_prologue (pc, func_end);
|
return thumb_skip_prologue (pc, func_end);
|
|
|
/* Can't find the prologue end in the symbol table, try it the hard way
|
/* Can't find the prologue end in the symbol table, try it the hard way
|
by disassembling the instructions. */
|
by disassembling the instructions. */
|
skip_pc = pc;
|
skip_pc = pc;
|
inst = read_memory_integer (skip_pc, 4);
|
inst = read_memory_integer (skip_pc, 4);
|
if (inst != 0xe1a0c00d) /* mov ip, sp */
|
if (inst != 0xe1a0c00d) /* mov ip, sp */
|
return pc;
|
return pc;
|
|
|
skip_pc += 4;
|
skip_pc += 4;
|
inst = read_memory_integer (skip_pc, 4);
|
inst = read_memory_integer (skip_pc, 4);
|
if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
|
if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
|
{
|
{
|
skip_pc += 4;
|
skip_pc += 4;
|
inst = read_memory_integer (skip_pc, 4);
|
inst = read_memory_integer (skip_pc, 4);
|
}
|
}
|
|
|
if ((inst & 0xfffff800) != 0xe92dd800) /* stmfd sp!,{...,fp,ip,lr,pc} */
|
if ((inst & 0xfffff800) != 0xe92dd800) /* stmfd sp!,{...,fp,ip,lr,pc} */
|
return pc;
|
return pc;
|
|
|
skip_pc += 4;
|
skip_pc += 4;
|
inst = read_memory_integer (skip_pc, 4);
|
inst = read_memory_integer (skip_pc, 4);
|
|
|
/* Any insns after this point may float into the code, if it makes
|
/* Any insns after this point may float into the code, if it makes
|
for better instruction scheduling, so we skip them only if we
|
for better instruction scheduling, so we skip them only if we
|
find them, but still consdier the function to be frame-ful. */
|
find them, but still consdier the function to be frame-ful. */
|
|
|
/* We may have either one sfmfd instruction here, or several stfe
|
/* We may have either one sfmfd instruction here, or several stfe
|
insns, depending on the version of floating point code we
|
insns, depending on the version of floating point code we
|
support. */
|
support. */
|
if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
|
if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
|
{
|
{
|
skip_pc += 4;
|
skip_pc += 4;
|
inst = read_memory_integer (skip_pc, 4);
|
inst = read_memory_integer (skip_pc, 4);
|
}
|
}
|
else
|
else
|
{
|
{
|
while ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
|
while ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
|
{
|
{
|
skip_pc += 4;
|
skip_pc += 4;
|
inst = read_memory_integer (skip_pc, 4);
|
inst = read_memory_integer (skip_pc, 4);
|
}
|
}
|
}
|
}
|
|
|
if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
|
if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
|
skip_pc += 4;
|
skip_pc += 4;
|
|
|
return skip_pc;
|
return skip_pc;
|
}
|
}
|
/* *INDENT-OFF* */
|
/* *INDENT-OFF* */
|
/* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
|
/* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
|
This function decodes a Thumb function prologue to determine:
|
This function decodes a Thumb function prologue to determine:
|
1) the size of the stack frame
|
1) the size of the stack frame
|
2) which registers are saved on it
|
2) which registers are saved on it
|
3) the offsets of saved regs
|
3) the offsets of saved regs
|
4) the offset from the stack pointer to the frame pointer
|
4) the offset from the stack pointer to the frame pointer
|
This information is stored in the "extra" fields of the frame_info.
|
This information is stored in the "extra" fields of the frame_info.
|
|
|
A typical Thumb function prologue would create this stack frame
|
A typical Thumb function prologue would create this stack frame
|
(offsets relative to FP)
|
(offsets relative to FP)
|
old SP -> 24 stack parameters
|
old SP -> 24 stack parameters
|
20 LR
|
20 LR
|
16 R7
|
16 R7
|
R7 -> 0 local variables (16 bytes)
|
R7 -> 0 local variables (16 bytes)
|
SP -> -12 additional stack space (12 bytes)
|
SP -> -12 additional stack space (12 bytes)
|
The frame size would thus be 36 bytes, and the frame offset would be
|
The frame size would thus be 36 bytes, and the frame offset would be
|
12 bytes. The frame register is R7.
|
12 bytes. The frame register is R7.
|
|
|
The comments for thumb_skip_prolog() describe the algorithm we use to detect
|
The comments for thumb_skip_prolog() describe the algorithm we use to detect
|
the end of the prolog */
|
the end of the prolog */
|
/* *INDENT-ON* */
|
/* *INDENT-ON* */
|
|
|
static void
|
static void
|
thumb_scan_prologue (struct frame_info *fi)
|
thumb_scan_prologue (struct frame_info *fi)
|
{
|
{
|
CORE_ADDR prologue_start;
|
CORE_ADDR prologue_start;
|
CORE_ADDR prologue_end;
|
CORE_ADDR prologue_end;
|
CORE_ADDR current_pc;
|
CORE_ADDR current_pc;
|
int saved_reg[16]; /* which register has been copied to register n? */
|
int saved_reg[16]; /* which register has been copied to register n? */
|
int findmask = 0; /* findmask:
|
int findmask = 0; /* findmask:
|
bit 0 - push { rlist }
|
bit 0 - push { rlist }
|
bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
|
bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
|
bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
|
bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
|
*/
|
*/
|
int i;
|
int i;
|
|
|
if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end))
|
if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end))
|
{
|
{
|
struct symtab_and_line sal = find_pc_line (prologue_start, 0);
|
struct symtab_and_line sal = find_pc_line (prologue_start, 0);
|
|
|
if (sal.line == 0) /* no line info, use current PC */
|
if (sal.line == 0) /* no line info, use current PC */
|
prologue_end = fi->pc;
|
prologue_end = fi->pc;
|
else if (sal.end < prologue_end) /* next line begins after fn end */
|
else if (sal.end < prologue_end) /* next line begins after fn end */
|
prologue_end = sal.end; /* (probably means no prologue) */
|
prologue_end = sal.end; /* (probably means no prologue) */
|
}
|
}
|
else
|
else
|
prologue_end = prologue_start + 40; /* We're in the boondocks: allow for */
|
prologue_end = prologue_start + 40; /* We're in the boondocks: allow for */
|
/* 16 pushes, an add, and "mv fp,sp" */
|
/* 16 pushes, an add, and "mv fp,sp" */
|
|
|
prologue_end = min (prologue_end, fi->pc);
|
prologue_end = min (prologue_end, fi->pc);
|
|
|
/* Initialize the saved register map. When register H is copied to
|
/* Initialize the saved register map. When register H is copied to
|
register L, we will put H in saved_reg[L]. */
|
register L, we will put H in saved_reg[L]. */
|
for (i = 0; i < 16; i++)
|
for (i = 0; i < 16; i++)
|
saved_reg[i] = i;
|
saved_reg[i] = i;
|
|
|
/* Search the prologue looking for instructions that set up the
|
/* Search the prologue looking for instructions that set up the
|
frame pointer, adjust the stack pointer, and save registers.
|
frame pointer, adjust the stack pointer, and save registers.
|
Do this until all basic prolog instructions are found. */
|
Do this until all basic prolog instructions are found. */
|
|
|
fi->framesize = 0;
|
fi->framesize = 0;
|
for (current_pc = prologue_start;
|
for (current_pc = prologue_start;
|
(current_pc < prologue_end) && ((findmask & 7) != 7);
|
(current_pc < prologue_end) && ((findmask & 7) != 7);
|
current_pc += 2)
|
current_pc += 2)
|
{
|
{
|
unsigned short insn;
|
unsigned short insn;
|
int regno;
|
int regno;
|
int offset;
|
int offset;
|
|
|
insn = read_memory_unsigned_integer (current_pc, 2);
|
insn = read_memory_unsigned_integer (current_pc, 2);
|
|
|
if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
|
if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
|
{
|
{
|
int mask;
|
int mask;
|
findmask |= 1; /* push found */
|
findmask |= 1; /* push found */
|
/* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
|
/* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
|
whether to save LR (R14). */
|
whether to save LR (R14). */
|
mask = (insn & 0xff) | ((insn & 0x100) << 6);
|
mask = (insn & 0xff) | ((insn & 0x100) << 6);
|
|
|
/* Calculate offsets of saved R0-R7 and LR. */
|
/* Calculate offsets of saved R0-R7 and LR. */
|
for (regno = LR_REGNUM; regno >= 0; regno--)
|
for (regno = LR_REGNUM; regno >= 0; regno--)
|
if (mask & (1 << regno))
|
if (mask & (1 << regno))
|
{
|
{
|
fi->framesize += 4;
|
fi->framesize += 4;
|
fi->fsr.regs[saved_reg[regno]] = -(fi->framesize);
|
fi->fsr.regs[saved_reg[regno]] = -(fi->framesize);
|
saved_reg[regno] = regno; /* reset saved register map */
|
saved_reg[regno] = regno; /* reset saved register map */
|
}
|
}
|
}
|
}
|
else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
|
else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
|
{
|
{
|
if ((findmask & 1) == 0) /* before push ? */
|
if ((findmask & 1) == 0) /* before push ? */
|
continue;
|
continue;
|
else
|
else
|
findmask |= 4; /* add/sub sp found */
|
findmask |= 4; /* add/sub sp found */
|
|
|
offset = (insn & 0x7f) << 2; /* get scaled offset */
|
offset = (insn & 0x7f) << 2; /* get scaled offset */
|
if (insn & 0x80) /* is it signed? (==subtracting) */
|
if (insn & 0x80) /* is it signed? (==subtracting) */
|
{
|
{
|
fi->frameoffset += offset;
|
fi->frameoffset += offset;
|
offset = -offset;
|
offset = -offset;
|
}
|
}
|
fi->framesize -= offset;
|
fi->framesize -= offset;
|
}
|
}
|
else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
|
else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
|
{
|
{
|
findmask |= 2; /* setting of r7 found */
|
findmask |= 2; /* setting of r7 found */
|
fi->framereg = THUMB_FP_REGNUM;
|
fi->framereg = THUMB_FP_REGNUM;
|
fi->frameoffset = (insn & 0xff) << 2; /* get scaled offset */
|
fi->frameoffset = (insn & 0xff) << 2; /* get scaled offset */
|
}
|
}
|
else if (insn == 0x466f) /* mov r7, sp */
|
else if (insn == 0x466f) /* mov r7, sp */
|
{
|
{
|
findmask |= 2; /* setting of r7 found */
|
findmask |= 2; /* setting of r7 found */
|
fi->framereg = THUMB_FP_REGNUM;
|
fi->framereg = THUMB_FP_REGNUM;
|
fi->frameoffset = 0;
|
fi->frameoffset = 0;
|
saved_reg[THUMB_FP_REGNUM] = SP_REGNUM;
|
saved_reg[THUMB_FP_REGNUM] = SP_REGNUM;
|
}
|
}
|
else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
|
else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
|
{
|
{
|
int lo_reg = insn & 7; /* dest. register (r0-r7) */
|
int lo_reg = insn & 7; /* dest. register (r0-r7) */
|
int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */
|
int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */
|
saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */
|
saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */
|
}
|
}
|
else
|
else
|
continue; /* something in the prolog that we don't care about or some
|
continue; /* something in the prolog that we don't care about or some
|
instruction from outside the prolog scheduled here for optimization */
|
instruction from outside the prolog scheduled here for optimization */
|
}
|
}
|
}
|
}
|
|
|
/* Check if prologue for this frame's PC has already been scanned. If
|
/* Check if prologue for this frame's PC has already been scanned. If
|
it has, copy the relevant information about that prologue and
|
it has, copy the relevant information about that prologue and
|
return non-zero. Otherwise do not copy anything and return zero.
|
return non-zero. Otherwise do not copy anything and return zero.
|
|
|
The information saved in the cache includes:
|
The information saved in the cache includes:
|
* the frame register number;
|
* the frame register number;
|
* the size of the stack frame;
|
* the size of the stack frame;
|
* the offsets of saved regs (relative to the old SP); and
|
* the offsets of saved regs (relative to the old SP); and
|
* the offset from the stack pointer to the frame pointer
|
* the offset from the stack pointer to the frame pointer
|
|
|
The cache contains only one entry, since this is adequate for the
|
The cache contains only one entry, since this is adequate for the
|
typical sequence of prologue scan requests we get. When performing
|
typical sequence of prologue scan requests we get. When performing
|
a backtrace, GDB will usually ask to scan the same function twice
|
a backtrace, GDB will usually ask to scan the same function twice
|
in a row (once to get the frame chain, and once to fill in the
|
in a row (once to get the frame chain, and once to fill in the
|
extra frame information). */
|
extra frame information). */
|
|
|
static struct frame_info prologue_cache;
|
static struct frame_info prologue_cache;
|
|
|
static int
|
static int
|
check_prologue_cache (struct frame_info *fi)
|
check_prologue_cache (struct frame_info *fi)
|
{
|
{
|
int i;
|
int i;
|
|
|
if (fi->pc == prologue_cache.pc)
|
if (fi->pc == prologue_cache.pc)
|
{
|
{
|
fi->framereg = prologue_cache.framereg;
|
fi->framereg = prologue_cache.framereg;
|
fi->framesize = prologue_cache.framesize;
|
fi->framesize = prologue_cache.framesize;
|
fi->frameoffset = prologue_cache.frameoffset;
|
fi->frameoffset = prologue_cache.frameoffset;
|
for (i = 0; i <= NUM_REGS; i++)
|
for (i = 0; i <= NUM_REGS; i++)
|
fi->fsr.regs[i] = prologue_cache.fsr.regs[i];
|
fi->fsr.regs[i] = prologue_cache.fsr.regs[i];
|
return 1;
|
return 1;
|
}
|
}
|
else
|
else
|
return 0;
|
return 0;
|
}
|
}
|
|
|
|
|
/* Copy the prologue information from fi to the prologue cache. */
|
/* Copy the prologue information from fi to the prologue cache. */
|
|
|
static void
|
static void
|
save_prologue_cache (struct frame_info *fi)
|
save_prologue_cache (struct frame_info *fi)
|
{
|
{
|
int i;
|
int i;
|
|
|
prologue_cache.pc = fi->pc;
|
prologue_cache.pc = fi->pc;
|
prologue_cache.framereg = fi->framereg;
|
prologue_cache.framereg = fi->framereg;
|
prologue_cache.framesize = fi->framesize;
|
prologue_cache.framesize = fi->framesize;
|
prologue_cache.frameoffset = fi->frameoffset;
|
prologue_cache.frameoffset = fi->frameoffset;
|
|
|
for (i = 0; i <= NUM_REGS; i++)
|
for (i = 0; i <= NUM_REGS; i++)
|
prologue_cache.fsr.regs[i] = fi->fsr.regs[i];
|
prologue_cache.fsr.regs[i] = fi->fsr.regs[i];
|
}
|
}
|
|
|
|
|
/* This function decodes an ARM function prologue to determine:
|
/* This function decodes an ARM function prologue to determine:
|
1) the size of the stack frame
|
1) the size of the stack frame
|
2) which registers are saved on it
|
2) which registers are saved on it
|
3) the offsets of saved regs
|
3) the offsets of saved regs
|
4) the offset from the stack pointer to the frame pointer
|
4) the offset from the stack pointer to the frame pointer
|
This information is stored in the "extra" fields of the frame_info.
|
This information is stored in the "extra" fields of the frame_info.
|
|
|
There are two basic forms for the ARM prologue. The fixed argument
|
There are two basic forms for the ARM prologue. The fixed argument
|
function call will look like:
|
function call will look like:
|
|
|
mov ip, sp
|
mov ip, sp
|
stmfd sp!, {fp, ip, lr, pc}
|
stmfd sp!, {fp, ip, lr, pc}
|
sub fp, ip, #4
|
sub fp, ip, #4
|
[sub sp, sp, #4]
|
[sub sp, sp, #4]
|
|
|
Which would create this stack frame (offsets relative to FP):
|
Which would create this stack frame (offsets relative to FP):
|
IP -> 4 (caller's stack)
|
IP -> 4 (caller's stack)
|
FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
|
FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
|
-4 LR (return address in caller)
|
-4 LR (return address in caller)
|
-8 IP (copy of caller's SP)
|
-8 IP (copy of caller's SP)
|
-12 FP (caller's FP)
|
-12 FP (caller's FP)
|
SP -> -28 Local variables
|
SP -> -28 Local variables
|
|
|
The frame size would thus be 32 bytes, and the frame offset would be
|
The frame size would thus be 32 bytes, and the frame offset would be
|
28 bytes. The stmfd call can also save any of the vN registers it
|
28 bytes. The stmfd call can also save any of the vN registers it
|
plans to use, which increases the frame size accordingly.
|
plans to use, which increases the frame size accordingly.
|
|
|
Note: The stored PC is 8 off of the STMFD instruction that stored it
|
Note: The stored PC is 8 off of the STMFD instruction that stored it
|
because the ARM Store instructions always store PC + 8 when you read
|
because the ARM Store instructions always store PC + 8 when you read
|
the PC register.
|
the PC register.
|
|
|
A variable argument function call will look like:
|
A variable argument function call will look like:
|
|
|
mov ip, sp
|
mov ip, sp
|
stmfd sp!, {a1, a2, a3, a4}
|
stmfd sp!, {a1, a2, a3, a4}
|
stmfd sp!, {fp, ip, lr, pc}
|
stmfd sp!, {fp, ip, lr, pc}
|
sub fp, ip, #20
|
sub fp, ip, #20
|
|
|
Which would create this stack frame (offsets relative to FP):
|
Which would create this stack frame (offsets relative to FP):
|
IP -> 20 (caller's stack)
|
IP -> 20 (caller's stack)
|
16 A4
|
16 A4
|
12 A3
|
12 A3
|
8 A2
|
8 A2
|
4 A1
|
4 A1
|
FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
|
FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
|
-4 LR (return address in caller)
|
-4 LR (return address in caller)
|
-8 IP (copy of caller's SP)
|
-8 IP (copy of caller's SP)
|
-12 FP (caller's FP)
|
-12 FP (caller's FP)
|
SP -> -28 Local variables
|
SP -> -28 Local variables
|
|
|
The frame size would thus be 48 bytes, and the frame offset would be
|
The frame size would thus be 48 bytes, and the frame offset would be
|
28 bytes.
|
28 bytes.
|
|
|
There is another potential complication, which is that the optimizer
|
There is another potential complication, which is that the optimizer
|
will try to separate the store of fp in the "stmfd" instruction from
|
will try to separate the store of fp in the "stmfd" instruction from
|
the "sub fp, ip, #NN" instruction. Almost anything can be there, so
|
the "sub fp, ip, #NN" instruction. Almost anything can be there, so
|
we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
|
we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
|
|
|
Also, note, the original version of the ARM toolchain claimed that there
|
Also, note, the original version of the ARM toolchain claimed that there
|
should be an
|
should be an
|
|
|
instruction at the end of the prologue. I have never seen GCC produce
|
instruction at the end of the prologue. I have never seen GCC produce
|
this, and the ARM docs don't mention it. We still test for it below in
|
this, and the ARM docs don't mention it. We still test for it below in
|
case it happens...
|
case it happens...
|
|
|
*/
|
*/
|
|
|
static void
|
static void
|
arm_scan_prologue (struct frame_info *fi)
|
arm_scan_prologue (struct frame_info *fi)
|
{
|
{
|
int regno, sp_offset, fp_offset;
|
int regno, sp_offset, fp_offset;
|
CORE_ADDR prologue_start, prologue_end, current_pc;
|
CORE_ADDR prologue_start, prologue_end, current_pc;
|
|
|
/* Check if this function is already in the cache of frame information. */
|
/* Check if this function is already in the cache of frame information. */
|
if (check_prologue_cache (fi))
|
if (check_prologue_cache (fi))
|
return;
|
return;
|
|
|
/* Assume there is no frame until proven otherwise. */
|
/* Assume there is no frame until proven otherwise. */
|
fi->framereg = SP_REGNUM;
|
fi->framereg = SP_REGNUM;
|
fi->framesize = 0;
|
fi->framesize = 0;
|
fi->frameoffset = 0;
|
fi->frameoffset = 0;
|
|
|
/* Check for Thumb prologue. */
|
/* Check for Thumb prologue. */
|
if (arm_pc_is_thumb (fi->pc))
|
if (arm_pc_is_thumb (fi->pc))
|
{
|
{
|
thumb_scan_prologue (fi);
|
thumb_scan_prologue (fi);
|
save_prologue_cache (fi);
|
save_prologue_cache (fi);
|
return;
|
return;
|
}
|
}
|
|
|
/* Find the function prologue. If we can't find the function in
|
/* Find the function prologue. If we can't find the function in
|
the symbol table, peek in the stack frame to find the PC. */
|
the symbol table, peek in the stack frame to find the PC. */
|
if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end))
|
if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end))
|
{
|
{
|
/* Assume the prologue is everything between the first instruction
|
/* Assume the prologue is everything between the first instruction
|
in the function and the first source line. */
|
in the function and the first source line. */
|
struct symtab_and_line sal = find_pc_line (prologue_start, 0);
|
struct symtab_and_line sal = find_pc_line (prologue_start, 0);
|
|
|
if (sal.line == 0) /* no line info, use current PC */
|
if (sal.line == 0) /* no line info, use current PC */
|
prologue_end = fi->pc;
|
prologue_end = fi->pc;
|
else if (sal.end < prologue_end) /* next line begins after fn end */
|
else if (sal.end < prologue_end) /* next line begins after fn end */
|
prologue_end = sal.end; /* (probably means no prologue) */
|
prologue_end = sal.end; /* (probably means no prologue) */
|
}
|
}
|
else
|
else
|
{
|
{
|
/* Get address of the stmfd in the prologue of the callee; the saved
|
/* Get address of the stmfd in the prologue of the callee; the saved
|
PC is the address of the stmfd + 8. */
|
PC is the address of the stmfd + 8. */
|
prologue_start = ADDR_BITS_REMOVE (read_memory_integer (fi->frame, 4))
|
prologue_start = ADDR_BITS_REMOVE (read_memory_integer (fi->frame, 4))
|
- 8;
|
- 8;
|
prologue_end = prologue_start + 64; /* This is all the insn's
|
prologue_end = prologue_start + 64; /* This is all the insn's
|
that could be in the prologue,
|
that could be in the prologue,
|
plus room for 5 insn's inserted
|
plus room for 5 insn's inserted
|
by the scheduler. */
|
by the scheduler. */
|
}
|
}
|
|
|
/* Now search the prologue looking for instructions that set up the
|
/* Now search the prologue looking for instructions that set up the
|
frame pointer, adjust the stack pointer, and save registers.
|
frame pointer, adjust the stack pointer, and save registers.
|
|
|
Be careful, however, and if it doesn't look like a prologue,
|
Be careful, however, and if it doesn't look like a prologue,
|
don't try to scan it. If, for instance, a frameless function
|
don't try to scan it. If, for instance, a frameless function
|
begins with stmfd sp!, then we will tell ourselves there is
|
begins with stmfd sp!, then we will tell ourselves there is
|
a frame, which will confuse stack traceback, as well ad"finish"
|
a frame, which will confuse stack traceback, as well ad"finish"
|
and other operations that rely on a knowledge of the stack
|
and other operations that rely on a knowledge of the stack
|
traceback.
|
traceback.
|
|
|
In the APCS, the prologue should start with "mov ip, sp" so
|
In the APCS, the prologue should start with "mov ip, sp" so
|
if we don't see this as the first insn, we will stop. */
|
if we don't see this as the first insn, we will stop. */
|
|
|
sp_offset = fp_offset = 0;
|
sp_offset = fp_offset = 0;
|
|
|
if (read_memory_unsigned_integer (prologue_start, 4)
|
if (read_memory_unsigned_integer (prologue_start, 4)
|
== 0xe1a0c00d) /* mov ip, sp */
|
== 0xe1a0c00d) /* mov ip, sp */
|
{
|
{
|
for (current_pc = prologue_start + 4; current_pc < prologue_end;
|
for (current_pc = prologue_start + 4; current_pc < prologue_end;
|
current_pc += 4)
|
current_pc += 4)
|
{
|
{
|
unsigned int insn = read_memory_unsigned_integer (current_pc, 4);
|
unsigned int insn = read_memory_unsigned_integer (current_pc, 4);
|
|
|
if ((insn & 0xffff0000) == 0xe92d0000)
|
if ((insn & 0xffff0000) == 0xe92d0000)
|
/* stmfd sp!, {..., fp, ip, lr, pc}
|
/* stmfd sp!, {..., fp, ip, lr, pc}
|
or
|
or
|
stmfd sp!, {a1, a2, a3, a4} */
|
stmfd sp!, {a1, a2, a3, a4} */
|
{
|
{
|
int mask = insn & 0xffff;
|
int mask = insn & 0xffff;
|
|
|
/* Calculate offsets of saved registers. */
|
/* Calculate offsets of saved registers. */
|
for (regno = PC_REGNUM; regno >= 0; regno--)
|
for (regno = PC_REGNUM; regno >= 0; regno--)
|
if (mask & (1 << regno))
|
if (mask & (1 << regno))
|
{
|
{
|
sp_offset -= 4;
|
sp_offset -= 4;
|
fi->fsr.regs[regno] = sp_offset;
|
fi->fsr.regs[regno] = sp_offset;
|
}
|
}
|
}
|
}
|
else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
|
else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
|
{
|
{
|
unsigned imm = insn & 0xff; /* immediate value */
|
unsigned imm = insn & 0xff; /* immediate value */
|
unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
|
unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
|
imm = (imm >> rot) | (imm << (32 - rot));
|
imm = (imm >> rot) | (imm << (32 - rot));
|
fp_offset = -imm;
|
fp_offset = -imm;
|
fi->framereg = FP_REGNUM;
|
fi->framereg = FP_REGNUM;
|
}
|
}
|
else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
|
else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
|
{
|
{
|
unsigned imm = insn & 0xff; /* immediate value */
|
unsigned imm = insn & 0xff; /* immediate value */
|
unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
|
unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
|
imm = (imm >> rot) | (imm << (32 - rot));
|
imm = (imm >> rot) | (imm << (32 - rot));
|
sp_offset -= imm;
|
sp_offset -= imm;
|
}
|
}
|
else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
|
else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
|
{
|
{
|
sp_offset -= 12;
|
sp_offset -= 12;
|
regno = F0_REGNUM + ((insn >> 12) & 0x07);
|
regno = F0_REGNUM + ((insn >> 12) & 0x07);
|
fi->fsr.regs[regno] = sp_offset;
|
fi->fsr.regs[regno] = sp_offset;
|
}
|
}
|
else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
|
else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
|
{
|
{
|
int n_saved_fp_regs;
|
int n_saved_fp_regs;
|
unsigned int fp_start_reg, fp_bound_reg;
|
unsigned int fp_start_reg, fp_bound_reg;
|
|
|
if ((insn & 0x800) == 0x800) /* N0 is set */
|
if ((insn & 0x800) == 0x800) /* N0 is set */
|
{
|
{
|
if ((insn & 0x40000) == 0x40000) /* N1 is set */
|
if ((insn & 0x40000) == 0x40000) /* N1 is set */
|
n_saved_fp_regs = 3;
|
n_saved_fp_regs = 3;
|
else
|
else
|
n_saved_fp_regs = 1;
|
n_saved_fp_regs = 1;
|
}
|
}
|
else
|
else
|
{
|
{
|
if ((insn & 0x40000) == 0x40000) /* N1 is set */
|
if ((insn & 0x40000) == 0x40000) /* N1 is set */
|
n_saved_fp_regs = 2;
|
n_saved_fp_regs = 2;
|
else
|
else
|
n_saved_fp_regs = 4;
|
n_saved_fp_regs = 4;
|
}
|
}
|
|
|
fp_start_reg = F0_REGNUM + ((insn >> 12) & 0x7);
|
fp_start_reg = F0_REGNUM + ((insn >> 12) & 0x7);
|
fp_bound_reg = fp_start_reg + n_saved_fp_regs;
|
fp_bound_reg = fp_start_reg + n_saved_fp_regs;
|
for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
|
for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
|
{
|
{
|
sp_offset -= 12;
|
sp_offset -= 12;
|
fi->fsr.regs[fp_start_reg++] = sp_offset;
|
fi->fsr.regs[fp_start_reg++] = sp_offset;
|
}
|
}
|
}
|
}
|
else
|
else
|
/* The optimizer might shove anything into the prologue,
|
/* The optimizer might shove anything into the prologue,
|
so we just skip what we don't recognize. */
|
so we just skip what we don't recognize. */
|
continue;
|
continue;
|
}
|
}
|
}
|
}
|
|
|
/* The frame size is just the negative of the offset (from the original SP)
|
/* The frame size is just the negative of the offset (from the original SP)
|
of the last thing thing we pushed on the stack. The frame offset is
|
of the last thing thing we pushed on the stack. The frame offset is
|
[new FP] - [new SP]. */
|
[new FP] - [new SP]. */
|
fi->framesize = -sp_offset;
|
fi->framesize = -sp_offset;
|
fi->frameoffset = fp_offset - sp_offset;
|
fi->frameoffset = fp_offset - sp_offset;
|
|
|
save_prologue_cache (fi);
|
save_prologue_cache (fi);
|
}
|
}
|
|
|
/* Find REGNUM on the stack. Otherwise, it's in an active register.
|
/* Find REGNUM on the stack. Otherwise, it's in an active register.
|
One thing we might want to do here is to check REGNUM against the
|
One thing we might want to do here is to check REGNUM against the
|
clobber mask, and somehow flag it as invalid if it isn't saved on
|
clobber mask, and somehow flag it as invalid if it isn't saved on
|
the stack somewhere. This would provide a graceful failure mode
|
the stack somewhere. This would provide a graceful failure mode
|
when trying to get the value of caller-saves registers for an inner
|
when trying to get the value of caller-saves registers for an inner
|
frame. */
|
frame. */
|
|
|
static CORE_ADDR
|
static CORE_ADDR
|
arm_find_callers_reg (struct frame_info *fi, int regnum)
|
arm_find_callers_reg (struct frame_info *fi, int regnum)
|
{
|
{
|
for (; fi; fi = fi->next)
|
for (; fi; fi = fi->next)
|
|
|
#if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
|
#if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
|
if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
|
if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
|
return generic_read_register_dummy (fi->pc, fi->frame, regnum);
|
return generic_read_register_dummy (fi->pc, fi->frame, regnum);
|
else
|
else
|
#endif
|
#endif
|
if (fi->fsr.regs[regnum] != 0)
|
if (fi->fsr.regs[regnum] != 0)
|
return read_memory_integer (fi->fsr.regs[regnum],
|
return read_memory_integer (fi->fsr.regs[regnum],
|
REGISTER_RAW_SIZE (regnum));
|
REGISTER_RAW_SIZE (regnum));
|
return read_register (regnum);
|
return read_register (regnum);
|
}
|
}
|
/* *INDENT-OFF* */
|
/* *INDENT-OFF* */
|
/* Function: frame_chain
|
/* Function: frame_chain
|
Given a GDB frame, determine the address of the calling function's frame.
|
Given a GDB frame, determine the address of the calling function's frame.
|
This will be used to create a new GDB frame struct, and then
|
This will be used to create a new GDB frame struct, and then
|
INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
|
INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
|
For ARM, we save the frame size when we initialize the frame_info.
|
For ARM, we save the frame size when we initialize the frame_info.
|
|
|
The original definition of this function was a macro in tm-arm.h:
|
The original definition of this function was a macro in tm-arm.h:
|
{ In the case of the ARM, the frame's nominal address is the FP value,
|
{ In the case of the ARM, the frame's nominal address is the FP value,
|
and 12 bytes before comes the saved previous FP value as a 4-byte word. }
|
and 12 bytes before comes the saved previous FP value as a 4-byte word. }
|
|
|
#define FRAME_CHAIN(thisframe) \
|
#define FRAME_CHAIN(thisframe) \
|
((thisframe)->pc >= LOWEST_PC ? \
|
((thisframe)->pc >= LOWEST_PC ? \
|
read_memory_integer ((thisframe)->frame - 12, 4) :\
|
read_memory_integer ((thisframe)->frame - 12, 4) :\
|
0)
|
0)
|
*/
|
*/
|
/* *INDENT-ON* */
|
/* *INDENT-ON* */
|
|
|
CORE_ADDR
|
CORE_ADDR
|
arm_frame_chain (struct frame_info *fi)
|
arm_frame_chain (struct frame_info *fi)
|
{
|
{
|
#if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
|
#if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
|
CORE_ADDR fn_start, callers_pc, fp;
|
CORE_ADDR fn_start, callers_pc, fp;
|
|
|
/* is this a dummy frame? */
|
/* is this a dummy frame? */
|
if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
|
if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
|
return fi->frame; /* dummy frame same as caller's frame */
|
return fi->frame; /* dummy frame same as caller's frame */
|
|
|
/* is caller-of-this a dummy frame? */
|
/* is caller-of-this a dummy frame? */
|
callers_pc = FRAME_SAVED_PC (fi); /* find out who called us: */
|
callers_pc = FRAME_SAVED_PC (fi); /* find out who called us: */
|
fp = arm_find_callers_reg (fi, FP_REGNUM);
|
fp = arm_find_callers_reg (fi, FP_REGNUM);
|
if (PC_IN_CALL_DUMMY (callers_pc, fp, fp))
|
if (PC_IN_CALL_DUMMY (callers_pc, fp, fp))
|
return fp; /* dummy frame's frame may bear no relation to ours */
|
return fp; /* dummy frame's frame may bear no relation to ours */
|
|
|
if (find_pc_partial_function (fi->pc, 0, &fn_start, 0))
|
if (find_pc_partial_function (fi->pc, 0, &fn_start, 0))
|
if (fn_start == entry_point_address ())
|
if (fn_start == entry_point_address ())
|
return 0; /* in _start fn, don't chain further */
|
return 0; /* in _start fn, don't chain further */
|
#endif
|
#endif
|
CORE_ADDR caller_pc, fn_start;
|
CORE_ADDR caller_pc, fn_start;
|
struct frame_info caller_fi;
|
struct frame_info caller_fi;
|
int framereg = fi->framereg;
|
int framereg = fi->framereg;
|
|
|
if (fi->pc < LOWEST_PC)
|
if (fi->pc < LOWEST_PC)
|
return 0;
|
return 0;
|
|
|
/* If the caller is the startup code, we're at the end of the chain. */
|
/* If the caller is the startup code, we're at the end of the chain. */
|
caller_pc = FRAME_SAVED_PC (fi);
|
caller_pc = FRAME_SAVED_PC (fi);
|
if (find_pc_partial_function (caller_pc, 0, &fn_start, 0))
|
if (find_pc_partial_function (caller_pc, 0, &fn_start, 0))
|
if (fn_start == entry_point_address ())
|
if (fn_start == entry_point_address ())
|
return 0;
|
return 0;
|
|
|
/* If the caller is Thumb and the caller is ARM, or vice versa,
|
/* If the caller is Thumb and the caller is ARM, or vice versa,
|
the frame register of the caller is different from ours.
|
the frame register of the caller is different from ours.
|
So we must scan the prologue of the caller to determine its
|
So we must scan the prologue of the caller to determine its
|
frame register number. */
|
frame register number. */
|
if (arm_pc_is_thumb (caller_pc) != arm_pc_is_thumb (fi->pc))
|
if (arm_pc_is_thumb (caller_pc) != arm_pc_is_thumb (fi->pc))
|
{
|
{
|
memset (&caller_fi, 0, sizeof (caller_fi));
|
memset (&caller_fi, 0, sizeof (caller_fi));
|
caller_fi.pc = caller_pc;
|
caller_fi.pc = caller_pc;
|
arm_scan_prologue (&caller_fi);
|
arm_scan_prologue (&caller_fi);
|
framereg = caller_fi.framereg;
|
framereg = caller_fi.framereg;
|
}
|
}
|
|
|
/* If the caller used a frame register, return its value.
|
/* If the caller used a frame register, return its value.
|
Otherwise, return the caller's stack pointer. */
|
Otherwise, return the caller's stack pointer. */
|
if (framereg == FP_REGNUM || framereg == THUMB_FP_REGNUM)
|
if (framereg == FP_REGNUM || framereg == THUMB_FP_REGNUM)
|
return arm_find_callers_reg (fi, framereg);
|
return arm_find_callers_reg (fi, framereg);
|
else
|
else
|
return fi->frame + fi->framesize;
|
return fi->frame + fi->framesize;
|
}
|
}
|
|
|
/* This function actually figures out the frame address for a given pc
|
/* This function actually figures out the frame address for a given pc
|
and sp. This is tricky because we sometimes don't use an explicit
|
and sp. This is tricky because we sometimes don't use an explicit
|
frame pointer, and the previous stack pointer isn't necessarily
|
frame pointer, and the previous stack pointer isn't necessarily
|
recorded on the stack. The only reliable way to get this info is
|
recorded on the stack. The only reliable way to get this info is
|
to examine the prologue. FROMLEAF is a little confusing, it means
|
to examine the prologue. FROMLEAF is a little confusing, it means
|
this is the next frame up the chain AFTER a frameless function. If
|
this is the next frame up the chain AFTER a frameless function. If
|
this is true, then the frame value for this frame is still in the
|
this is true, then the frame value for this frame is still in the
|
fp register. */
|
fp register. */
|
|
|
void
|
void
|
arm_init_extra_frame_info (int fromleaf, struct frame_info *fi)
|
arm_init_extra_frame_info (int fromleaf, struct frame_info *fi)
|
{
|
{
|
int reg;
|
int reg;
|
|
|
if (fi->next)
|
if (fi->next)
|
fi->pc = FRAME_SAVED_PC (fi->next);
|
fi->pc = FRAME_SAVED_PC (fi->next);
|
|
|
memset (fi->fsr.regs, '\000', sizeof fi->fsr.regs);
|
memset (fi->fsr.regs, '\000', sizeof fi->fsr.regs);
|
|
|
#if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
|
#if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
|
if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
|
if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
|
{
|
{
|
/* We need to setup fi->frame here because run_stack_dummy gets it wrong
|
/* We need to setup fi->frame here because run_stack_dummy gets it wrong
|
by assuming it's always FP. */
|
by assuming it's always FP. */
|
fi->frame = generic_read_register_dummy (fi->pc, fi->frame, SP_REGNUM);
|
fi->frame = generic_read_register_dummy (fi->pc, fi->frame, SP_REGNUM);
|
fi->framesize = 0;
|
fi->framesize = 0;
|
fi->frameoffset = 0;
|
fi->frameoffset = 0;
|
return;
|
return;
|
}
|
}
|
else
|
else
|
#endif
|
#endif
|
{
|
{
|
arm_scan_prologue (fi);
|
arm_scan_prologue (fi);
|
|
|
if (!fi->next)
|
if (!fi->next)
|
/* this is the innermost frame? */
|
/* this is the innermost frame? */
|
fi->frame = read_register (fi->framereg);
|
fi->frame = read_register (fi->framereg);
|
else if (fi->framereg == FP_REGNUM || fi->framereg == THUMB_FP_REGNUM)
|
else if (fi->framereg == FP_REGNUM || fi->framereg == THUMB_FP_REGNUM)
|
{
|
{
|
/* not the innermost frame */
|
/* not the innermost frame */
|
/* If we have an FP, the callee saved it. */
|
/* If we have an FP, the callee saved it. */
|
if (fi->next->fsr.regs[fi->framereg] != 0)
|
if (fi->next->fsr.regs[fi->framereg] != 0)
|
fi->frame =
|
fi->frame =
|
read_memory_integer (fi->next->fsr.regs[fi->framereg], 4);
|
read_memory_integer (fi->next->fsr.regs[fi->framereg], 4);
|
else if (fromleaf)
|
else if (fromleaf)
|
/* If we were called by a frameless fn. then our frame is
|
/* If we were called by a frameless fn. then our frame is
|
still in the frame pointer register on the board... */
|
still in the frame pointer register on the board... */
|
fi->frame = read_fp ();
|
fi->frame = read_fp ();
|
}
|
}
|
|
|
/* Calculate actual addresses of saved registers using offsets
|
/* Calculate actual addresses of saved registers using offsets
|
determined by arm_scan_prologue. */
|
determined by arm_scan_prologue. */
|
for (reg = 0; reg < NUM_REGS; reg++)
|
for (reg = 0; reg < NUM_REGS; reg++)
|
if (fi->fsr.regs[reg] != 0)
|
if (fi->fsr.regs[reg] != 0)
|
fi->fsr.regs[reg] += fi->frame + fi->framesize - fi->frameoffset;
|
fi->fsr.regs[reg] += fi->frame + fi->framesize - fi->frameoffset;
|
}
|
}
|
}
|
}
|
|
|
|
|
/* Find the caller of this frame. We do this by seeing if LR_REGNUM
|
/* Find the caller of this frame. We do this by seeing if LR_REGNUM
|
is saved in the stack anywhere, otherwise we get it from the
|
is saved in the stack anywhere, otherwise we get it from the
|
registers.
|
registers.
|
|
|
The old definition of this function was a macro:
|
The old definition of this function was a macro:
|
#define FRAME_SAVED_PC(FRAME) \
|
#define FRAME_SAVED_PC(FRAME) \
|
ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */
|
ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */
|
|
|
CORE_ADDR
|
CORE_ADDR
|
arm_frame_saved_pc (struct frame_info *fi)
|
arm_frame_saved_pc (struct frame_info *fi)
|
{
|
{
|
#if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
|
#if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
|
if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
|
if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
|
return generic_read_register_dummy (fi->pc, fi->frame, PC_REGNUM);
|
return generic_read_register_dummy (fi->pc, fi->frame, PC_REGNUM);
|
else
|
else
|
#endif
|
#endif
|
{
|
{
|
CORE_ADDR pc = arm_find_callers_reg (fi, LR_REGNUM);
|
CORE_ADDR pc = arm_find_callers_reg (fi, LR_REGNUM);
|
return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc;
|
return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc;
|
}
|
}
|
}
|
}
|
|
|
/* Return the frame address. On ARM, it is R11; on Thumb it is R7.
|
/* Return the frame address. On ARM, it is R11; on Thumb it is R7.
|
Examine the Program Status Register to decide which state we're in. */
|
Examine the Program Status Register to decide which state we're in. */
|
|
|
CORE_ADDR
|
CORE_ADDR
|
arm_target_read_fp (void)
|
arm_target_read_fp (void)
|
{
|
{
|
if (read_register (PS_REGNUM) & 0x20) /* Bit 5 is Thumb state bit */
|
if (read_register (PS_REGNUM) & 0x20) /* Bit 5 is Thumb state bit */
|
return read_register (THUMB_FP_REGNUM); /* R7 if Thumb */
|
return read_register (THUMB_FP_REGNUM); /* R7 if Thumb */
|
else
|
else
|
return read_register (FP_REGNUM); /* R11 if ARM */
|
return read_register (FP_REGNUM); /* R11 if ARM */
|
}
|
}
|
|
|
/* Calculate the frame offsets of the saved registers (ARM version). */
|
/* Calculate the frame offsets of the saved registers (ARM version). */
|
|
|
void
|
void
|
arm_frame_find_saved_regs (struct frame_info *fi,
|
arm_frame_find_saved_regs (struct frame_info *fi,
|
struct frame_saved_regs *regaddr)
|
struct frame_saved_regs *regaddr)
|
{
|
{
|
memcpy (regaddr, &fi->fsr, sizeof (struct frame_saved_regs));
|
memcpy (regaddr, &fi->fsr, sizeof (struct frame_saved_regs));
|
}
|
}
|
|
|
void
|
void
|
arm_push_dummy_frame (void)
|
arm_push_dummy_frame (void)
|
{
|
{
|
CORE_ADDR old_sp = read_register (SP_REGNUM);
|
CORE_ADDR old_sp = read_register (SP_REGNUM);
|
CORE_ADDR sp = old_sp;
|
CORE_ADDR sp = old_sp;
|
CORE_ADDR fp, prologue_start;
|
CORE_ADDR fp, prologue_start;
|
int regnum;
|
int regnum;
|
|
|
/* Push the two dummy prologue instructions in reverse order,
|
/* Push the two dummy prologue instructions in reverse order,
|
so that they'll be in the correct low-to-high order in memory. */
|
so that they'll be in the correct low-to-high order in memory. */
|
/* sub fp, ip, #4 */
|
/* sub fp, ip, #4 */
|
sp = push_word (sp, 0xe24cb004);
|
sp = push_word (sp, 0xe24cb004);
|
/* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
|
/* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
|
prologue_start = sp = push_word (sp, 0xe92ddfff);
|
prologue_start = sp = push_word (sp, 0xe92ddfff);
|
|
|
/* Push a pointer to the dummy prologue + 12, because when stm
|
/* Push a pointer to the dummy prologue + 12, because when stm
|
instruction stores the PC, it stores the address of the stm
|
instruction stores the PC, it stores the address of the stm
|
instruction itself plus 12. */
|
instruction itself plus 12. */
|
fp = sp = push_word (sp, prologue_start + 12);
|
fp = sp = push_word (sp, prologue_start + 12);
|
sp = push_word (sp, read_register (PC_REGNUM)); /* FIXME: was PS_REGNUM */
|
sp = push_word (sp, read_register (PC_REGNUM)); /* FIXME: was PS_REGNUM */
|
sp = push_word (sp, old_sp);
|
sp = push_word (sp, old_sp);
|
sp = push_word (sp, read_register (FP_REGNUM));
|
sp = push_word (sp, read_register (FP_REGNUM));
|
|
|
for (regnum = 10; regnum >= 0; regnum--)
|
for (regnum = 10; regnum >= 0; regnum--)
|
sp = push_word (sp, read_register (regnum));
|
sp = push_word (sp, read_register (regnum));
|
|
|
write_register (FP_REGNUM, fp);
|
write_register (FP_REGNUM, fp);
|
write_register (THUMB_FP_REGNUM, fp);
|
write_register (THUMB_FP_REGNUM, fp);
|
write_register (SP_REGNUM, sp);
|
write_register (SP_REGNUM, sp);
|
}
|
}
|
|
|
/* Fix up the call dummy, based on whether the processor is currently
|
/* Fix up the call dummy, based on whether the processor is currently
|
in Thumb or ARM mode, and whether the target function is Thumb or
|
in Thumb or ARM mode, and whether the target function is Thumb or
|
ARM. There are three different situations requiring three
|
ARM. There are three different situations requiring three
|
different dummies:
|
different dummies:
|
|
|
* ARM calling ARM: uses the call dummy in tm-arm.h, which has already
|
* ARM calling ARM: uses the call dummy in tm-arm.h, which has already
|
been copied into the dummy parameter to this function.
|
been copied into the dummy parameter to this function.
|
* ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
|
* ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
|
"mov pc,r4" instruction patched to be a "bx r4" instead.
|
"mov pc,r4" instruction patched to be a "bx r4" instead.
|
* Thumb calling anything: uses the Thumb dummy defined below, which
|
* Thumb calling anything: uses the Thumb dummy defined below, which
|
works for calling both ARM and Thumb functions.
|
works for calling both ARM and Thumb functions.
|
|
|
All three call dummies expect to receive the target function
|
All three call dummies expect to receive the target function
|
address in R4, with the low bit set if it's a Thumb function. */
|
address in R4, with the low bit set if it's a Thumb function. */
|
|
|
void
|
void
|
arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs,
|
arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs,
|
value_ptr *args, struct type *type, int gcc_p)
|
value_ptr *args, struct type *type, int gcc_p)
|
{
|
{
|
static short thumb_dummy[4] =
|
static short thumb_dummy[4] =
|
{
|
{
|
0xf000, 0xf801, /* bl label */
|
0xf000, 0xf801, /* bl label */
|
0xdf18, /* swi 24 */
|
0xdf18, /* swi 24 */
|
0x4720, /* label: bx r4 */
|
0x4720, /* label: bx r4 */
|
};
|
};
|
static unsigned long arm_bx_r4 = 0xe12fff14; /* bx r4 instruction */
|
static unsigned long arm_bx_r4 = 0xe12fff14; /* bx r4 instruction */
|
|
|
/* Set flag indicating whether the current PC is in a Thumb function. */
|
/* Set flag indicating whether the current PC is in a Thumb function. */
|
caller_is_thumb = arm_pc_is_thumb (read_pc ());
|
caller_is_thumb = arm_pc_is_thumb (read_pc ());
|
|
|
/* If the target function is Thumb, set the low bit of the function
|
/* If the target function is Thumb, set the low bit of the function
|
address. And if the CPU is currently in ARM mode, patch the
|
address. And if the CPU is currently in ARM mode, patch the
|
second instruction of call dummy to use a BX instruction to
|
second instruction of call dummy to use a BX instruction to
|
switch to Thumb mode. */
|
switch to Thumb mode. */
|
target_is_thumb = arm_pc_is_thumb (fun);
|
target_is_thumb = arm_pc_is_thumb (fun);
|
if (target_is_thumb)
|
if (target_is_thumb)
|
{
|
{
|
fun |= 1;
|
fun |= 1;
|
if (!caller_is_thumb)
|
if (!caller_is_thumb)
|
store_unsigned_integer (dummy + 4, sizeof (arm_bx_r4), arm_bx_r4);
|
store_unsigned_integer (dummy + 4, sizeof (arm_bx_r4), arm_bx_r4);
|
}
|
}
|
|
|
/* If the CPU is currently in Thumb mode, use the Thumb call dummy
|
/* If the CPU is currently in Thumb mode, use the Thumb call dummy
|
instead of the ARM one that's already been copied. This will
|
instead of the ARM one that's already been copied. This will
|
work for both Thumb and ARM target functions. */
|
work for both Thumb and ARM target functions. */
|
if (caller_is_thumb)
|
if (caller_is_thumb)
|
{
|
{
|
int i;
|
int i;
|
char *p = dummy;
|
char *p = dummy;
|
int len = sizeof (thumb_dummy) / sizeof (thumb_dummy[0]);
|
int len = sizeof (thumb_dummy) / sizeof (thumb_dummy[0]);
|
|
|
for (i = 0; i < len; i++)
|
for (i = 0; i < len; i++)
|
{
|
{
|
store_unsigned_integer (p, sizeof (thumb_dummy[0]), thumb_dummy[i]);
|
store_unsigned_integer (p, sizeof (thumb_dummy[0]), thumb_dummy[i]);
|
p += sizeof (thumb_dummy[0]);
|
p += sizeof (thumb_dummy[0]);
|
}
|
}
|
}
|
}
|
|
|
/* Put the target address in r4; the call dummy will copy this to
|
/* Put the target address in r4; the call dummy will copy this to
|
the PC. */
|
the PC. */
|
write_register (4, fun);
|
write_register (4, fun);
|
}
|
}
|
|
|
/* Return the offset in the call dummy of the instruction that needs
|
/* Return the offset in the call dummy of the instruction that needs
|
to have a breakpoint placed on it. This is the offset of the 'swi
|
to have a breakpoint placed on it. This is the offset of the 'swi
|
24' instruction, which is no longer actually used, but simply acts
|
24' instruction, which is no longer actually used, but simply acts
|
as a place-holder now.
|
as a place-holder now.
|
|
|
This implements the CALL_DUMMY_BREAK_OFFSET macro. */
|
This implements the CALL_DUMMY_BREAK_OFFSET macro. */
|
|
|
int
|
int
|
arm_call_dummy_breakpoint_offset (void)
|
arm_call_dummy_breakpoint_offset (void)
|
{
|
{
|
if (caller_is_thumb)
|
if (caller_is_thumb)
|
return 4;
|
return 4;
|
else
|
else
|
return 8;
|
return 8;
|
}
|
}
|
|
|
/* Note: ScottB
|
/* Note: ScottB
|
|
|
This function does not support passing parameters using the FPA
|
This function does not support passing parameters using the FPA
|
variant of the APCS. It passes any floating point arguments in the
|
variant of the APCS. It passes any floating point arguments in the
|
general registers and/or on the stack. */
|
general registers and/or on the stack. */
|
|
|
CORE_ADDR
|
CORE_ADDR
|
arm_push_arguments (int nargs, value_ptr * args, CORE_ADDR sp,
|
arm_push_arguments (int nargs, value_ptr * args, CORE_ADDR sp,
|
int struct_return, CORE_ADDR struct_addr)
|
int struct_return, CORE_ADDR struct_addr)
|
{
|
{
|
char *fp;
|
char *fp;
|
int argnum, argreg, nstack_size;
|
int argnum, argreg, nstack_size;
|
|
|
/* Walk through the list of args and determine how large a temporary
|
/* Walk through the list of args and determine how large a temporary
|
stack is required. Need to take care here as structs may be
|
stack is required. Need to take care here as structs may be
|
passed on the stack, and we have to to push them. */
|
passed on the stack, and we have to to push them. */
|
nstack_size = -4 * REGISTER_SIZE; /* Some arguments go into A1-A4. */
|
nstack_size = -4 * REGISTER_SIZE; /* Some arguments go into A1-A4. */
|
if (struct_return) /* The struct address goes in A1. */
|
if (struct_return) /* The struct address goes in A1. */
|
nstack_size += REGISTER_SIZE;
|
nstack_size += REGISTER_SIZE;
|
|
|
/* Walk through the arguments and add their size to nstack_size. */
|
/* Walk through the arguments and add their size to nstack_size. */
|
for (argnum = 0; argnum < nargs; argnum++)
|
for (argnum = 0; argnum < nargs; argnum++)
|
{
|
{
|
int len;
|
int len;
|
struct type *arg_type;
|
struct type *arg_type;
|
|
|
arg_type = check_typedef (VALUE_TYPE (args[argnum]));
|
arg_type = check_typedef (VALUE_TYPE (args[argnum]));
|
len = TYPE_LENGTH (arg_type);
|
len = TYPE_LENGTH (arg_type);
|
|
|
/* ANSI C code passes float arguments as integers, K&R code
|
/* ANSI C code passes float arguments as integers, K&R code
|
passes float arguments as doubles. Correct for this here. */
|
passes float arguments as doubles. Correct for this here. */
|
if (TYPE_CODE_FLT == TYPE_CODE (arg_type) && REGISTER_SIZE == len)
|
if (TYPE_CODE_FLT == TYPE_CODE (arg_type) && REGISTER_SIZE == len)
|
nstack_size += FP_REGISTER_VIRTUAL_SIZE;
|
nstack_size += FP_REGISTER_VIRTUAL_SIZE;
|
else
|
else
|
nstack_size += len;
|
nstack_size += len;
|
}
|
}
|
|
|
/* Allocate room on the stack, and initialize our stack frame
|
/* Allocate room on the stack, and initialize our stack frame
|
pointer. */
|
pointer. */
|
fp = NULL;
|
fp = NULL;
|
if (nstack_size > 0)
|
if (nstack_size > 0)
|
{
|
{
|
sp -= nstack_size;
|
sp -= nstack_size;
|
fp = (char *) sp;
|
fp = (char *) sp;
|
}
|
}
|
|
|
/* Initialize the integer argument register pointer. */
|
/* Initialize the integer argument register pointer. */
|
argreg = A1_REGNUM;
|
argreg = A1_REGNUM;
|
|
|
/* The struct_return pointer occupies the first parameter passing
|
/* The struct_return pointer occupies the first parameter passing
|
register. */
|
register. */
|
if (struct_return)
|
if (struct_return)
|
write_register (argreg++, struct_addr);
|
write_register (argreg++, struct_addr);
|
|
|
/* Process arguments from left to right. Store as many as allowed
|
/* Process arguments from left to right. Store as many as allowed
|
in the parameter passing registers (A1-A4), and save the rest on
|
in the parameter passing registers (A1-A4), and save the rest on
|
the temporary stack. */
|
the temporary stack. */
|
for (argnum = 0; argnum < nargs; argnum++)
|
for (argnum = 0; argnum < nargs; argnum++)
|
{
|
{
|
int len;
|
int len;
|
char *val;
|
char *val;
|
double dbl_arg;
|
double dbl_arg;
|
CORE_ADDR regval;
|
CORE_ADDR regval;
|
enum type_code typecode;
|
enum type_code typecode;
|
struct type *arg_type, *target_type;
|
struct type *arg_type, *target_type;
|
|
|
arg_type = check_typedef (VALUE_TYPE (args[argnum]));
|
arg_type = check_typedef (VALUE_TYPE (args[argnum]));
|
target_type = TYPE_TARGET_TYPE (arg_type);
|
target_type = TYPE_TARGET_TYPE (arg_type);
|
len = TYPE_LENGTH (arg_type);
|
len = TYPE_LENGTH (arg_type);
|
typecode = TYPE_CODE (arg_type);
|
typecode = TYPE_CODE (arg_type);
|
val = (char *) VALUE_CONTENTS (args[argnum]);
|
val = (char *) VALUE_CONTENTS (args[argnum]);
|
|
|
/* ANSI C code passes float arguments as integers, K&R code
|
/* ANSI C code passes float arguments as integers, K&R code
|
passes float arguments as doubles. The .stabs record for
|
passes float arguments as doubles. The .stabs record for
|
for ANSI prototype floating point arguments records the
|
for ANSI prototype floating point arguments records the
|
type as FP_INTEGER, while a K&R style (no prototype)
|
type as FP_INTEGER, while a K&R style (no prototype)
|
.stabs records the type as FP_FLOAT. In this latter case
|
.stabs records the type as FP_FLOAT. In this latter case
|
the compiler converts the float arguments to double before
|
the compiler converts the float arguments to double before
|
calling the function. */
|
calling the function. */
|
if (TYPE_CODE_FLT == typecode && REGISTER_SIZE == len)
|
if (TYPE_CODE_FLT == typecode && REGISTER_SIZE == len)
|
{
|
{
|
float f;
|
float f;
|
double d;
|
double d;
|
char * bufo = (char *) &d;
|
char * bufo = (char *) &d;
|
char * bufd = (char *) &dbl_arg;
|
char * bufd = (char *) &dbl_arg;
|
|
|
len = sizeof (double);
|
len = sizeof (double);
|
f = *(float *) val;
|
f = *(float *) val;
|
SWAP_TARGET_AND_HOST (&f, sizeof (float)); /* adjust endianess */
|
SWAP_TARGET_AND_HOST (&f, sizeof (float)); /* adjust endianess */
|
d = f;
|
d = f;
|
/* We must revert the longwords so they get loaded into the
|
/* We must revert the longwords so they get loaded into the
|
the right registers. */
|
the right registers. */
|
memcpy (bufd, bufo + len / 2, len / 2);
|
memcpy (bufd, bufo + len / 2, len / 2);
|
SWAP_TARGET_AND_HOST (bufd, len / 2); /* adjust endianess */
|
SWAP_TARGET_AND_HOST (bufd, len / 2); /* adjust endianess */
|
memcpy (bufd + len / 2, bufo, len / 2);
|
memcpy (bufd + len / 2, bufo, len / 2);
|
SWAP_TARGET_AND_HOST (bufd + len / 2, len / 2); /* adjust endianess */
|
SWAP_TARGET_AND_HOST (bufd + len / 2, len / 2); /* adjust endianess */
|
val = (char *) &dbl_arg;
|
val = (char *) &dbl_arg;
|
}
|
}
|
#if 1
|
#if 1
|
/* I don't know why this code was disable. The only logical use
|
/* I don't know why this code was disable. The only logical use
|
for a function pointer is to call that function, so setting
|
for a function pointer is to call that function, so setting
|
the mode bit is perfectly fine. FN */
|
the mode bit is perfectly fine. FN */
|
/* If the argument is a pointer to a function, and it is a Thumb
|
/* If the argument is a pointer to a function, and it is a Thumb
|
function, set the low bit of the pointer. */
|
function, set the low bit of the pointer. */
|
if (TYPE_CODE_PTR == typecode
|
if (TYPE_CODE_PTR == typecode
|
&& NULL != target_type
|
&& NULL != target_type
|
&& TYPE_CODE_FUNC == TYPE_CODE (target_type))
|
&& TYPE_CODE_FUNC == TYPE_CODE (target_type))
|
{
|
{
|
CORE_ADDR regval = extract_address (val, len);
|
CORE_ADDR regval = extract_address (val, len);
|
if (arm_pc_is_thumb (regval))
|
if (arm_pc_is_thumb (regval))
|
store_address (val, len, MAKE_THUMB_ADDR (regval));
|
store_address (val, len, MAKE_THUMB_ADDR (regval));
|
}
|
}
|
#endif
|
#endif
|
/* Copy the argument to general registers or the stack in
|
/* Copy the argument to general registers or the stack in
|
register-sized pieces. Large arguments are split between
|
register-sized pieces. Large arguments are split between
|
registers and stack. */
|
registers and stack. */
|
while (len > 0)
|
while (len > 0)
|
{
|
{
|
int partial_len = len < REGISTER_SIZE ? len : REGISTER_SIZE;
|
int partial_len = len < REGISTER_SIZE ? len : REGISTER_SIZE;
|
|
|
if (argreg <= ARM_LAST_ARG_REGNUM)
|
if (argreg <= ARM_LAST_ARG_REGNUM)
|
{
|
{
|
/* It's an argument being passed in a general register. */
|
/* It's an argument being passed in a general register. */
|
regval = extract_address (val, partial_len);
|
regval = extract_address (val, partial_len);
|
write_register (argreg++, regval);
|
write_register (argreg++, regval);
|
}
|
}
|
else
|
else
|
{
|
{
|
/* Push the arguments onto the stack. */
|
/* Push the arguments onto the stack. */
|
write_memory ((CORE_ADDR) fp, val, REGISTER_SIZE);
|
write_memory ((CORE_ADDR) fp, val, REGISTER_SIZE);
|
fp += REGISTER_SIZE;
|
fp += REGISTER_SIZE;
|
}
|
}
|
|
|
len -= partial_len;
|
len -= partial_len;
|
val += partial_len;
|
val += partial_len;
|
}
|
}
|
}
|
}
|
|
|
/* Return adjusted stack pointer. */
|
/* Return adjusted stack pointer. */
|
return sp;
|
return sp;
|
}
|
}
|
|
|
void
|
void
|
arm_pop_frame (void)
|
arm_pop_frame (void)
|
{
|
{
|
int regnum;
|
int regnum;
|
struct frame_info *frame = get_current_frame ();
|
struct frame_info *frame = get_current_frame ();
|
|
|
if (!PC_IN_CALL_DUMMY(frame->pc, frame->frame, read_fp()))
|
if (!PC_IN_CALL_DUMMY(frame->pc, frame->frame, read_fp()))
|
{
|
{
|
CORE_ADDR old_SP;
|
CORE_ADDR old_SP;
|
|
|
old_SP = read_register (frame->framereg);
|
old_SP = read_register (frame->framereg);
|
for (regnum = 0; regnum < NUM_REGS; regnum++)
|
for (regnum = 0; regnum < NUM_REGS; regnum++)
|
if (frame->fsr.regs[regnum] != 0)
|
if (frame->fsr.regs[regnum] != 0)
|
write_register (regnum,
|
write_register (regnum,
|
read_memory_integer (frame->fsr.regs[regnum], 4));
|
read_memory_integer (frame->fsr.regs[regnum], 4));
|
|
|
write_register (PC_REGNUM, FRAME_SAVED_PC (frame));
|
write_register (PC_REGNUM, FRAME_SAVED_PC (frame));
|
write_register (SP_REGNUM, old_SP);
|
write_register (SP_REGNUM, old_SP);
|
}
|
}
|
else
|
else
|
{
|
{
|
CORE_ADDR sp;
|
CORE_ADDR sp;
|
|
|
sp = read_register (FP_REGNUM);
|
sp = read_register (FP_REGNUM);
|
sp -= sizeof(CORE_ADDR); /* we don't care about this first word */
|
sp -= sizeof(CORE_ADDR); /* we don't care about this first word */
|
|
|
write_register (PC_REGNUM, read_memory_integer (sp, 4));
|
write_register (PC_REGNUM, read_memory_integer (sp, 4));
|
sp -= sizeof(CORE_ADDR);
|
sp -= sizeof(CORE_ADDR);
|
write_register (SP_REGNUM, read_memory_integer (sp, 4));
|
write_register (SP_REGNUM, read_memory_integer (sp, 4));
|
sp -= sizeof(CORE_ADDR);
|
sp -= sizeof(CORE_ADDR);
|
write_register (FP_REGNUM, read_memory_integer (sp, 4));
|
write_register (FP_REGNUM, read_memory_integer (sp, 4));
|
sp -= sizeof(CORE_ADDR);
|
sp -= sizeof(CORE_ADDR);
|
|
|
for (regnum = 10; regnum >= 0; regnum--)
|
for (regnum = 10; regnum >= 0; regnum--)
|
{
|
{
|
write_register (regnum, read_memory_integer (sp, 4));
|
write_register (regnum, read_memory_integer (sp, 4));
|
sp -= sizeof(CORE_ADDR);
|
sp -= sizeof(CORE_ADDR);
|
}
|
}
|
}
|
}
|
|
|
flush_cached_frames ();
|
flush_cached_frames ();
|
}
|
}
|
|
|
static void
|
static void
|
print_fpu_flags (int flags)
|
print_fpu_flags (int flags)
|
{
|
{
|
if (flags & (1 << 0))
|
if (flags & (1 << 0))
|
fputs ("IVO ", stdout);
|
fputs ("IVO ", stdout);
|
if (flags & (1 << 1))
|
if (flags & (1 << 1))
|
fputs ("DVZ ", stdout);
|
fputs ("DVZ ", stdout);
|
if (flags & (1 << 2))
|
if (flags & (1 << 2))
|
fputs ("OFL ", stdout);
|
fputs ("OFL ", stdout);
|
if (flags & (1 << 3))
|
if (flags & (1 << 3))
|
fputs ("UFL ", stdout);
|
fputs ("UFL ", stdout);
|
if (flags & (1 << 4))
|
if (flags & (1 << 4))
|
fputs ("INX ", stdout);
|
fputs ("INX ", stdout);
|
putchar ('\n');
|
putchar ('\n');
|
}
|
}
|
|
|
void
|
void
|
arm_float_info (void)
|
arm_float_info (void)
|
{
|
{
|
register unsigned long status = read_register (FPS_REGNUM);
|
register unsigned long status = read_register (FPS_REGNUM);
|
int type;
|
int type;
|
|
|
type = (status >> 24) & 127;
|
type = (status >> 24) & 127;
|
printf ("%s FPU type %d\n",
|
printf ("%s FPU type %d\n",
|
(status & (1 << 31)) ? "Hardware" : "Software",
|
(status & (1 << 31)) ? "Hardware" : "Software",
|
type);
|
type);
|
fputs ("mask: ", stdout);
|
fputs ("mask: ", stdout);
|
print_fpu_flags (status >> 16);
|
print_fpu_flags (status >> 16);
|
fputs ("flags: ", stdout);
|
fputs ("flags: ", stdout);
|
print_fpu_flags (status);
|
print_fpu_flags (status);
|
}
|
}
|
|
|
#if 0
|
#if 0
|
/* FIXME: The generated assembler works but sucks. Instead of using
|
/* FIXME: The generated assembler works but sucks. Instead of using
|
r0, r1 it pushes them on the stack, then loads them into r3, r4 and
|
r0, r1 it pushes them on the stack, then loads them into r3, r4 and
|
uses those registers. I must be missing something. ScottB */
|
uses those registers. I must be missing something. ScottB */
|
|
|
void
|
void
|
convert_from_extended (void *ptr, void *dbl)
|
convert_from_extended (void *ptr, void *dbl)
|
{
|
{
|
__asm__ ("
|
__asm__ ("
|
ldfe f0,[%0]
|
ldfe f0,[%0]
|
stfd f0,[%1] "
|
stfd f0,[%1] "
|
: /* no output */
|
: /* no output */
|
: "r" (ptr), "r" (dbl));
|
: "r" (ptr), "r" (dbl));
|
}
|
}
|
|
|
void
|
void
|
convert_to_extended (void *dbl, void *ptr)
|
convert_to_extended (void *dbl, void *ptr)
|
{
|
{
|
__asm__ ("
|
__asm__ ("
|
ldfd f0,[%0]
|
ldfd f0,[%0]
|
stfe f0,[%1] "
|
stfe f0,[%1] "
|
: /* no output */
|
: /* no output */
|
: "r" (dbl), "r" (ptr));
|
: "r" (dbl), "r" (ptr));
|
}
|
}
|
#else
|
#else
|
static void
|
static void
|
convert_from_extended (void *ptr, void *dbl)
|
convert_from_extended (void *ptr, void *dbl)
|
{
|
{
|
*(double *) dbl = *(double *) ptr;
|
*(double *) dbl = *(double *) ptr;
|
}
|
}
|
|
|
void
|
void
|
convert_to_extended (void *dbl, void *ptr)
|
convert_to_extended (void *dbl, void *ptr)
|
{
|
{
|
*(double *) ptr = *(double *) dbl;
|
*(double *) ptr = *(double *) dbl;
|
}
|
}
|
#endif
|
#endif
|
|
|
/* Nonzero if register N requires conversion from raw format to
|
/* Nonzero if register N requires conversion from raw format to
|
virtual format. */
|
virtual format. */
|
|
|
int
|
int
|
arm_register_convertible (unsigned int regnum)
|
arm_register_convertible (unsigned int regnum)
|
{
|
{
|
return ((regnum - F0_REGNUM) < 8);
|
return ((regnum - F0_REGNUM) < 8);
|
}
|
}
|
|
|
/* Convert data from raw format for register REGNUM in buffer FROM to
|
/* Convert data from raw format for register REGNUM in buffer FROM to
|
virtual format with type TYPE in buffer TO. */
|
virtual format with type TYPE in buffer TO. */
|
|
|
void
|
void
|
arm_register_convert_to_virtual (unsigned int regnum, struct type *type,
|
arm_register_convert_to_virtual (unsigned int regnum, struct type *type,
|
void *from, void *to)
|
void *from, void *to)
|
{
|
{
|
double val;
|
double val;
|
|
|
convert_from_extended (from, &val);
|
convert_from_extended (from, &val);
|
store_floating (to, TYPE_LENGTH (type), val);
|
store_floating (to, TYPE_LENGTH (type), val);
|
}
|
}
|
|
|
/* Convert data from virtual format with type TYPE in buffer FROM to
|
/* Convert data from virtual format with type TYPE in buffer FROM to
|
raw format for register REGNUM in buffer TO. */
|
raw format for register REGNUM in buffer TO. */
|
|
|
void
|
void
|
arm_register_convert_to_raw (unsigned int regnum, struct type *type,
|
arm_register_convert_to_raw (unsigned int regnum, struct type *type,
|
void *from, void *to)
|
void *from, void *to)
|
{
|
{
|
double val = extract_floating (from, TYPE_LENGTH (type));
|
double val = extract_floating (from, TYPE_LENGTH (type));
|
|
|
convert_to_extended (&val, to);
|
convert_to_extended (&val, to);
|
}
|
}
|
|
|
static int
|
static int
|
condition_true (unsigned long cond, unsigned long status_reg)
|
condition_true (unsigned long cond, unsigned long status_reg)
|
{
|
{
|
if (cond == INST_AL || cond == INST_NV)
|
if (cond == INST_AL || cond == INST_NV)
|
return 1;
|
return 1;
|
|
|
switch (cond)
|
switch (cond)
|
{
|
{
|
case INST_EQ:
|
case INST_EQ:
|
return ((status_reg & FLAG_Z) != 0);
|
return ((status_reg & FLAG_Z) != 0);
|
case INST_NE:
|
case INST_NE:
|
return ((status_reg & FLAG_Z) == 0);
|
return ((status_reg & FLAG_Z) == 0);
|
case INST_CS:
|
case INST_CS:
|
return ((status_reg & FLAG_C) != 0);
|
return ((status_reg & FLAG_C) != 0);
|
case INST_CC:
|
case INST_CC:
|
return ((status_reg & FLAG_C) == 0);
|
return ((status_reg & FLAG_C) == 0);
|
case INST_MI:
|
case INST_MI:
|
return ((status_reg & FLAG_N) != 0);
|
return ((status_reg & FLAG_N) != 0);
|
case INST_PL:
|
case INST_PL:
|
return ((status_reg & FLAG_N) == 0);
|
return ((status_reg & FLAG_N) == 0);
|
case INST_VS:
|
case INST_VS:
|
return ((status_reg & FLAG_V) != 0);
|
return ((status_reg & FLAG_V) != 0);
|
case INST_VC:
|
case INST_VC:
|
return ((status_reg & FLAG_V) == 0);
|
return ((status_reg & FLAG_V) == 0);
|
case INST_HI:
|
case INST_HI:
|
return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
|
return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
|
case INST_LS:
|
case INST_LS:
|
return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
|
return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
|
case INST_GE:
|
case INST_GE:
|
return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
|
return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
|
case INST_LT:
|
case INST_LT:
|
return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
|
return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
|
case INST_GT:
|
case INST_GT:
|
return (((status_reg & FLAG_Z) == 0) &&
|
return (((status_reg & FLAG_Z) == 0) &&
|
(((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)));
|
(((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)));
|
case INST_LE:
|
case INST_LE:
|
return (((status_reg & FLAG_Z) != 0) ||
|
return (((status_reg & FLAG_Z) != 0) ||
|
(((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)));
|
(((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)));
|
}
|
}
|
return 1;
|
return 1;
|
}
|
}
|
|
|
#define submask(x) ((1L << ((x) + 1)) - 1)
|
#define submask(x) ((1L << ((x) + 1)) - 1)
|
#define bit(obj,st) (((obj) >> (st)) & 1)
|
#define bit(obj,st) (((obj) >> (st)) & 1)
|
#define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
|
#define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
|
#define sbits(obj,st,fn) \
|
#define sbits(obj,st,fn) \
|
((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
|
((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
|
#define BranchDest(addr,instr) \
|
#define BranchDest(addr,instr) \
|
((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
|
((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
|
#define ARM_PC_32 1
|
#define ARM_PC_32 1
|
|
|
static unsigned long
|
static unsigned long
|
shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val,
|
shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val,
|
unsigned long status_reg)
|
unsigned long status_reg)
|
{
|
{
|
unsigned long res, shift;
|
unsigned long res, shift;
|
int rm = bits (inst, 0, 3);
|
int rm = bits (inst, 0, 3);
|
unsigned long shifttype = bits (inst, 5, 6);
|
unsigned long shifttype = bits (inst, 5, 6);
|
|
|
if (bit (inst, 4))
|
if (bit (inst, 4))
|
{
|
{
|
int rs = bits (inst, 8, 11);
|
int rs = bits (inst, 8, 11);
|
shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF;
|
shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF;
|
}
|
}
|
else
|
else
|
shift = bits (inst, 7, 11);
|
shift = bits (inst, 7, 11);
|
|
|
res = (rm == 15
|
res = (rm == 15
|
? ((pc_val | (ARM_PC_32 ? 0 : status_reg))
|
? ((pc_val | (ARM_PC_32 ? 0 : status_reg))
|
+ (bit (inst, 4) ? 12 : 8))
|
+ (bit (inst, 4) ? 12 : 8))
|
: read_register (rm));
|
: read_register (rm));
|
|
|
switch (shifttype)
|
switch (shifttype)
|
{
|
{
|
case 0: /* LSL */
|
case 0: /* LSL */
|
res = shift >= 32 ? 0 : res << shift;
|
res = shift >= 32 ? 0 : res << shift;
|
break;
|
break;
|
|
|
case 1: /* LSR */
|
case 1: /* LSR */
|
res = shift >= 32 ? 0 : res >> shift;
|
res = shift >= 32 ? 0 : res >> shift;
|
break;
|
break;
|
|
|
case 2: /* ASR */
|
case 2: /* ASR */
|
if (shift >= 32)
|
if (shift >= 32)
|
shift = 31;
|
shift = 31;
|
res = ((res & 0x80000000L)
|
res = ((res & 0x80000000L)
|
? ~((~res) >> shift) : res >> shift);
|
? ~((~res) >> shift) : res >> shift);
|
break;
|
break;
|
|
|
case 3: /* ROR/RRX */
|
case 3: /* ROR/RRX */
|
shift &= 31;
|
shift &= 31;
|
if (shift == 0)
|
if (shift == 0)
|
res = (res >> 1) | (carry ? 0x80000000L : 0);
|
res = (res >> 1) | (carry ? 0x80000000L : 0);
|
else
|
else
|
res = (res >> shift) | (res << (32 - shift));
|
res = (res >> shift) | (res << (32 - shift));
|
break;
|
break;
|
}
|
}
|
|
|
return res & 0xffffffff;
|
return res & 0xffffffff;
|
}
|
}
|
|
|
/* Return number of 1-bits in VAL. */
|
/* Return number of 1-bits in VAL. */
|
|
|
static int
|
static int
|
bitcount (unsigned long val)
|
bitcount (unsigned long val)
|
{
|
{
|
int nbits;
|
int nbits;
|
for (nbits = 0; val != 0; nbits++)
|
for (nbits = 0; val != 0; nbits++)
|
val &= val - 1; /* delete rightmost 1-bit in val */
|
val &= val - 1; /* delete rightmost 1-bit in val */
|
return nbits;
|
return nbits;
|
}
|
}
|
|
|
static CORE_ADDR
|
static CORE_ADDR
|
thumb_get_next_pc (CORE_ADDR pc)
|
thumb_get_next_pc (CORE_ADDR pc)
|
{
|
{
|
unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
|
unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
|
unsigned short inst1 = read_memory_integer (pc, 2);
|
unsigned short inst1 = read_memory_integer (pc, 2);
|
CORE_ADDR nextpc = pc + 2; /* default is next instruction */
|
CORE_ADDR nextpc = pc + 2; /* default is next instruction */
|
unsigned long offset;
|
unsigned long offset;
|
|
|
if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
|
if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
|
{
|
{
|
CORE_ADDR sp;
|
CORE_ADDR sp;
|
|
|
/* Fetch the saved PC from the stack. It's stored above
|
/* Fetch the saved PC from the stack. It's stored above
|
all of the other registers. */
|
all of the other registers. */
|
offset = bitcount (bits (inst1, 0, 7)) * REGISTER_SIZE;
|
offset = bitcount (bits (inst1, 0, 7)) * REGISTER_SIZE;
|
sp = read_register (SP_REGNUM);
|
sp = read_register (SP_REGNUM);
|
nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4);
|
nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4);
|
nextpc = ADDR_BITS_REMOVE (nextpc);
|
nextpc = ADDR_BITS_REMOVE (nextpc);
|
if (nextpc == pc)
|
if (nextpc == pc)
|
error ("Infinite loop detected");
|
error ("Infinite loop detected");
|
}
|
}
|
else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
|
else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
|
{
|
{
|
unsigned long status = read_register (PS_REGNUM);
|
unsigned long status = read_register (PS_REGNUM);
|
unsigned long cond = bits (inst1, 8, 11);
|
unsigned long cond = bits (inst1, 8, 11);
|
if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */
|
if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */
|
nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
|
nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
|
}
|
}
|
else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
|
else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
|
{
|
{
|
nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
|
nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
|
}
|
}
|
else if ((inst1 & 0xf800) == 0xf000) /* long branch with link */
|
else if ((inst1 & 0xf800) == 0xf000) /* long branch with link */
|
{
|
{
|
unsigned short inst2 = read_memory_integer (pc + 2, 2);
|
unsigned short inst2 = read_memory_integer (pc + 2, 2);
|
offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1);
|
offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1);
|
nextpc = pc_val + offset;
|
nextpc = pc_val + offset;
|
}
|
}
|
|
|
return nextpc;
|
return nextpc;
|
}
|
}
|
|
|
CORE_ADDR
|
CORE_ADDR
|
arm_get_next_pc (CORE_ADDR pc)
|
arm_get_next_pc (CORE_ADDR pc)
|
{
|
{
|
unsigned long pc_val;
|
unsigned long pc_val;
|
unsigned long this_instr;
|
unsigned long this_instr;
|
unsigned long status;
|
unsigned long status;
|
CORE_ADDR nextpc;
|
CORE_ADDR nextpc;
|
|
|
if (arm_pc_is_thumb (pc))
|
if (arm_pc_is_thumb (pc))
|
return thumb_get_next_pc (pc);
|
return thumb_get_next_pc (pc);
|
|
|
pc_val = (unsigned long) pc;
|
pc_val = (unsigned long) pc;
|
this_instr = read_memory_integer (pc, 4);
|
this_instr = read_memory_integer (pc, 4);
|
status = read_register (PS_REGNUM);
|
status = read_register (PS_REGNUM);
|
nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
|
nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
|
|
|
if (condition_true (bits (this_instr, 28, 31), status))
|
if (condition_true (bits (this_instr, 28, 31), status))
|
{
|
{
|
switch (bits (this_instr, 24, 27))
|
switch (bits (this_instr, 24, 27))
|
{
|
{
|
case 0x0:
|
case 0x0:
|
case 0x1: /* data processing */
|
case 0x1: /* data processing */
|
case 0x2:
|
case 0x2:
|
case 0x3:
|
case 0x3:
|
{
|
{
|
unsigned long operand1, operand2, result = 0;
|
unsigned long operand1, operand2, result = 0;
|
unsigned long rn;
|
unsigned long rn;
|
int c;
|
int c;
|
|
|
if (bits (this_instr, 12, 15) != 15)
|
if (bits (this_instr, 12, 15) != 15)
|
break;
|
break;
|
|
|
if (bits (this_instr, 22, 25) == 0
|
if (bits (this_instr, 22, 25) == 0
|
&& bits (this_instr, 4, 7) == 9) /* multiply */
|
&& bits (this_instr, 4, 7) == 9) /* multiply */
|
error ("Illegal update to pc in instruction");
|
error ("Illegal update to pc in instruction");
|
|
|
/* Multiply into PC */
|
/* Multiply into PC */
|
c = (status & FLAG_C) ? 1 : 0;
|
c = (status & FLAG_C) ? 1 : 0;
|
rn = bits (this_instr, 16, 19);
|
rn = bits (this_instr, 16, 19);
|
operand1 = (rn == 15) ? pc_val + 8 : read_register (rn);
|
operand1 = (rn == 15) ? pc_val + 8 : read_register (rn);
|
|
|
if (bit (this_instr, 25))
|
if (bit (this_instr, 25))
|
{
|
{
|
unsigned long immval = bits (this_instr, 0, 7);
|
unsigned long immval = bits (this_instr, 0, 7);
|
unsigned long rotate = 2 * bits (this_instr, 8, 11);
|
unsigned long rotate = 2 * bits (this_instr, 8, 11);
|
operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
|
operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
|
& 0xffffffff;
|
& 0xffffffff;
|
}
|
}
|
else /* operand 2 is a shifted register */
|
else /* operand 2 is a shifted register */
|
operand2 = shifted_reg_val (this_instr, c, pc_val, status);
|
operand2 = shifted_reg_val (this_instr, c, pc_val, status);
|
|
|
switch (bits (this_instr, 21, 24))
|
switch (bits (this_instr, 21, 24))
|
{
|
{
|
case 0x0: /*and */
|
case 0x0: /*and */
|
result = operand1 & operand2;
|
result = operand1 & operand2;
|
break;
|
break;
|
|
|
case 0x1: /*eor */
|
case 0x1: /*eor */
|
result = operand1 ^ operand2;
|
result = operand1 ^ operand2;
|
break;
|
break;
|
|
|
case 0x2: /*sub */
|
case 0x2: /*sub */
|
result = operand1 - operand2;
|
result = operand1 - operand2;
|
break;
|
break;
|
|
|
case 0x3: /*rsb */
|
case 0x3: /*rsb */
|
result = operand2 - operand1;
|
result = operand2 - operand1;
|
break;
|
break;
|
|
|
case 0x4: /*add */
|
case 0x4: /*add */
|
result = operand1 + operand2;
|
result = operand1 + operand2;
|
break;
|
break;
|
|
|
case 0x5: /*adc */
|
case 0x5: /*adc */
|
result = operand1 + operand2 + c;
|
result = operand1 + operand2 + c;
|
break;
|
break;
|
|
|
case 0x6: /*sbc */
|
case 0x6: /*sbc */
|
result = operand1 - operand2 + c;
|
result = operand1 - operand2 + c;
|
break;
|
break;
|
|
|
case 0x7: /*rsc */
|
case 0x7: /*rsc */
|
result = operand2 - operand1 + c;
|
result = operand2 - operand1 + c;
|
break;
|
break;
|
|
|
case 0x8:
|
case 0x8:
|
case 0x9:
|
case 0x9:
|
case 0xa:
|
case 0xa:
|
case 0xb: /* tst, teq, cmp, cmn */
|
case 0xb: /* tst, teq, cmp, cmn */
|
result = (unsigned long) nextpc;
|
result = (unsigned long) nextpc;
|
break;
|
break;
|
|
|
case 0xc: /*orr */
|
case 0xc: /*orr */
|
result = operand1 | operand2;
|
result = operand1 | operand2;
|
break;
|
break;
|
|
|
case 0xd: /*mov */
|
case 0xd: /*mov */
|
/* Always step into a function. */
|
/* Always step into a function. */
|
result = operand2;
|
result = operand2;
|
break;
|
break;
|
|
|
case 0xe: /*bic */
|
case 0xe: /*bic */
|
result = operand1 & ~operand2;
|
result = operand1 & ~operand2;
|
break;
|
break;
|
|
|
case 0xf: /*mvn */
|
case 0xf: /*mvn */
|
result = ~operand2;
|
result = ~operand2;
|
break;
|
break;
|
}
|
}
|
nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result);
|
nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result);
|
|
|
if (nextpc == pc)
|
if (nextpc == pc)
|
error ("Infinite loop detected");
|
error ("Infinite loop detected");
|
break;
|
break;
|
}
|
}
|
|
|
case 0x4:
|
case 0x4:
|
case 0x5: /* data transfer */
|
case 0x5: /* data transfer */
|
case 0x6:
|
case 0x6:
|
case 0x7:
|
case 0x7:
|
if (bit (this_instr, 20))
|
if (bit (this_instr, 20))
|
{
|
{
|
/* load */
|
/* load */
|
if (bits (this_instr, 12, 15) == 15)
|
if (bits (this_instr, 12, 15) == 15)
|
{
|
{
|
/* rd == pc */
|
/* rd == pc */
|
unsigned long rn;
|
unsigned long rn;
|
unsigned long base;
|
unsigned long base;
|
|
|
if (bit (this_instr, 22))
|
if (bit (this_instr, 22))
|
error ("Illegal update to pc in instruction");
|
error ("Illegal update to pc in instruction");
|
|
|
/* byte write to PC */
|
/* byte write to PC */
|
rn = bits (this_instr, 16, 19);
|
rn = bits (this_instr, 16, 19);
|
base = (rn == 15) ? pc_val + 8 : read_register (rn);
|
base = (rn == 15) ? pc_val + 8 : read_register (rn);
|
if (bit (this_instr, 24))
|
if (bit (this_instr, 24))
|
{
|
{
|
/* pre-indexed */
|
/* pre-indexed */
|
int c = (status & FLAG_C) ? 1 : 0;
|
int c = (status & FLAG_C) ? 1 : 0;
|
unsigned long offset =
|
unsigned long offset =
|
(bit (this_instr, 25)
|
(bit (this_instr, 25)
|
? shifted_reg_val (this_instr, c, pc_val, status)
|
? shifted_reg_val (this_instr, c, pc_val, status)
|
: bits (this_instr, 0, 11));
|
: bits (this_instr, 0, 11));
|
|
|
if (bit (this_instr, 23))
|
if (bit (this_instr, 23))
|
base += offset;
|
base += offset;
|
else
|
else
|
base -= offset;
|
base -= offset;
|
}
|
}
|
nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base,
|
nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base,
|
4);
|
4);
|
|
|
nextpc = ADDR_BITS_REMOVE (nextpc);
|
nextpc = ADDR_BITS_REMOVE (nextpc);
|
|
|
if (nextpc == pc)
|
if (nextpc == pc)
|
error ("Infinite loop detected");
|
error ("Infinite loop detected");
|
}
|
}
|
}
|
}
|
break;
|
break;
|
|
|
case 0x8:
|
case 0x8:
|
case 0x9: /* block transfer */
|
case 0x9: /* block transfer */
|
if (bit (this_instr, 20))
|
if (bit (this_instr, 20))
|
{
|
{
|
/* LDM */
|
/* LDM */
|
if (bit (this_instr, 15))
|
if (bit (this_instr, 15))
|
{
|
{
|
/* loading pc */
|
/* loading pc */
|
int offset = 0;
|
int offset = 0;
|
|
|
if (bit (this_instr, 23))
|
if (bit (this_instr, 23))
|
{
|
{
|
/* up */
|
/* up */
|
unsigned long reglist = bits (this_instr, 0, 14);
|
unsigned long reglist = bits (this_instr, 0, 14);
|
offset = bitcount (reglist) * 4;
|
offset = bitcount (reglist) * 4;
|
if (bit (this_instr, 24)) /* pre */
|
if (bit (this_instr, 24)) /* pre */
|
offset += 4;
|
offset += 4;
|
}
|
}
|
else if (bit (this_instr, 24))
|
else if (bit (this_instr, 24))
|
offset = -4;
|
offset = -4;
|
|
|
{
|
{
|
unsigned long rn_val =
|
unsigned long rn_val =
|
read_register (bits (this_instr, 16, 19));
|
read_register (bits (this_instr, 16, 19));
|
nextpc =
|
nextpc =
|
(CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val
|
(CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val
|
+ offset),
|
+ offset),
|
4);
|
4);
|
}
|
}
|
nextpc = ADDR_BITS_REMOVE (nextpc);
|
nextpc = ADDR_BITS_REMOVE (nextpc);
|
if (nextpc == pc)
|
if (nextpc == pc)
|
error ("Infinite loop detected");
|
error ("Infinite loop detected");
|
}
|
}
|
}
|
}
|
break;
|
break;
|
|
|
case 0xb: /* branch & link */
|
case 0xb: /* branch & link */
|
case 0xa: /* branch */
|
case 0xa: /* branch */
|
{
|
{
|
nextpc = BranchDest (pc, this_instr);
|
nextpc = BranchDest (pc, this_instr);
|
|
|
nextpc = ADDR_BITS_REMOVE (nextpc);
|
nextpc = ADDR_BITS_REMOVE (nextpc);
|
if (nextpc == pc)
|
if (nextpc == pc)
|
error ("Infinite loop detected");
|
error ("Infinite loop detected");
|
break;
|
break;
|
}
|
}
|
|
|
case 0xc:
|
case 0xc:
|
case 0xd:
|
case 0xd:
|
case 0xe: /* coproc ops */
|
case 0xe: /* coproc ops */
|
case 0xf: /* SWI */
|
case 0xf: /* SWI */
|
break;
|
break;
|
|
|
default:
|
default:
|
fprintf (stderr, "Bad bit-field extraction\n");
|
fprintf (stderr, "Bad bit-field extraction\n");
|
return (pc);
|
return (pc);
|
}
|
}
|
}
|
}
|
|
|
return nextpc;
|
return nextpc;
|
}
|
}
|
|
|
#include "bfd-in2.h"
|
#include "bfd-in2.h"
|
#include "libcoff.h"
|
#include "libcoff.h"
|
|
|
static int
|
static int
|
gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
|
gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
|
{
|
{
|
if (arm_pc_is_thumb (memaddr))
|
if (arm_pc_is_thumb (memaddr))
|
{
|
{
|
static asymbol *asym;
|
static asymbol *asym;
|
static combined_entry_type ce;
|
static combined_entry_type ce;
|
static struct coff_symbol_struct csym;
|
static struct coff_symbol_struct csym;
|
static struct _bfd fake_bfd;
|
static struct _bfd fake_bfd;
|
static bfd_target fake_target;
|
static bfd_target fake_target;
|
|
|
if (csym.native == NULL)
|
if (csym.native == NULL)
|
{
|
{
|
/* Create a fake symbol vector containing a Thumb symbol. This is
|
/* Create a fake symbol vector containing a Thumb symbol. This is
|
solely so that the code in print_insn_little_arm() and
|
solely so that the code in print_insn_little_arm() and
|
print_insn_big_arm() in opcodes/arm-dis.c will detect the presence
|
print_insn_big_arm() in opcodes/arm-dis.c will detect the presence
|
of a Thumb symbol and switch to decoding Thumb instructions. */
|
of a Thumb symbol and switch to decoding Thumb instructions. */
|
|
|
fake_target.flavour = bfd_target_coff_flavour;
|
fake_target.flavour = bfd_target_coff_flavour;
|
fake_bfd.xvec = &fake_target;
|
fake_bfd.xvec = &fake_target;
|
ce.u.syment.n_sclass = C_THUMBEXTFUNC;
|
ce.u.syment.n_sclass = C_THUMBEXTFUNC;
|
csym.native = &ce;
|
csym.native = &ce;
|
csym.symbol.the_bfd = &fake_bfd;
|
csym.symbol.the_bfd = &fake_bfd;
|
csym.symbol.name = "fake";
|
csym.symbol.name = "fake";
|
asym = (asymbol *) & csym;
|
asym = (asymbol *) & csym;
|
}
|
}
|
|
|
memaddr = UNMAKE_THUMB_ADDR (memaddr);
|
memaddr = UNMAKE_THUMB_ADDR (memaddr);
|
info->symbols = &asym;
|
info->symbols = &asym;
|
}
|
}
|
else
|
else
|
info->symbols = NULL;
|
info->symbols = NULL;
|
|
|
if (TARGET_BYTE_ORDER == BIG_ENDIAN)
|
if (TARGET_BYTE_ORDER == BIG_ENDIAN)
|
return print_insn_big_arm (memaddr, info);
|
return print_insn_big_arm (memaddr, info);
|
else
|
else
|
return print_insn_little_arm (memaddr, info);
|
return print_insn_little_arm (memaddr, info);
|
}
|
}
|
|
|
/* This function implements the BREAKPOINT_FROM_PC macro. It uses the
|
/* This function implements the BREAKPOINT_FROM_PC macro. It uses the
|
program counter value to determine whether a 16-bit or 32-bit
|
program counter value to determine whether a 16-bit or 32-bit
|
breakpoint should be used. It returns a pointer to a string of
|
breakpoint should be used. It returns a pointer to a string of
|
bytes that encode a breakpoint instruction, stores the length of
|
bytes that encode a breakpoint instruction, stores the length of
|
the string to *lenptr, and adjusts the program counter (if
|
the string to *lenptr, and adjusts the program counter (if
|
necessary) to point to the actual memory location where the
|
necessary) to point to the actual memory location where the
|
breakpoint should be inserted. */
|
breakpoint should be inserted. */
|
|
|
unsigned char *
|
unsigned char *
|
arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
|
arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
|
{
|
{
|
if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr))
|
if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr))
|
{
|
{
|
if (TARGET_BYTE_ORDER == BIG_ENDIAN)
|
if (TARGET_BYTE_ORDER == BIG_ENDIAN)
|
{
|
{
|
static char thumb_breakpoint[] = THUMB_BE_BREAKPOINT;
|
static char thumb_breakpoint[] = THUMB_BE_BREAKPOINT;
|
*pcptr = UNMAKE_THUMB_ADDR (*pcptr);
|
*pcptr = UNMAKE_THUMB_ADDR (*pcptr);
|
*lenptr = sizeof (thumb_breakpoint);
|
*lenptr = sizeof (thumb_breakpoint);
|
return thumb_breakpoint;
|
return thumb_breakpoint;
|
}
|
}
|
else
|
else
|
{
|
{
|
static char thumb_breakpoint[] = THUMB_LE_BREAKPOINT;
|
static char thumb_breakpoint[] = THUMB_LE_BREAKPOINT;
|
*pcptr = UNMAKE_THUMB_ADDR (*pcptr);
|
*pcptr = UNMAKE_THUMB_ADDR (*pcptr);
|
*lenptr = sizeof (thumb_breakpoint);
|
*lenptr = sizeof (thumb_breakpoint);
|
return thumb_breakpoint;
|
return thumb_breakpoint;
|
}
|
}
|
}
|
}
|
else
|
else
|
{
|
{
|
if (TARGET_BYTE_ORDER == BIG_ENDIAN)
|
if (TARGET_BYTE_ORDER == BIG_ENDIAN)
|
{
|
{
|
static char arm_breakpoint[] = ARM_BE_BREAKPOINT;
|
static char arm_breakpoint[] = ARM_BE_BREAKPOINT;
|
*lenptr = sizeof (arm_breakpoint);
|
*lenptr = sizeof (arm_breakpoint);
|
return arm_breakpoint;
|
return arm_breakpoint;
|
}
|
}
|
else
|
else
|
{
|
{
|
static char arm_breakpoint[] = ARM_LE_BREAKPOINT;
|
static char arm_breakpoint[] = ARM_LE_BREAKPOINT;
|
*lenptr = sizeof (arm_breakpoint);
|
*lenptr = sizeof (arm_breakpoint);
|
return arm_breakpoint;
|
return arm_breakpoint;
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
/* Extract from an array REGBUF containing the (raw) register state a
|
/* Extract from an array REGBUF containing the (raw) register state a
|
function return value of type TYPE, and copy that, in virtual
|
function return value of type TYPE, and copy that, in virtual
|
format, into VALBUF. */
|
format, into VALBUF. */
|
|
|
void
|
void
|
arm_extract_return_value (struct type *type,
|
arm_extract_return_value (struct type *type,
|
char regbuf[REGISTER_BYTES],
|
char regbuf[REGISTER_BYTES],
|
char *valbuf)
|
char *valbuf)
|
{
|
{
|
if (TYPE_CODE_FLT == TYPE_CODE (type))
|
if (TYPE_CODE_FLT == TYPE_CODE (type))
|
convert_from_extended (®buf[REGISTER_BYTE (F0_REGNUM)], valbuf);
|
convert_from_extended (®buf[REGISTER_BYTE (F0_REGNUM)], valbuf);
|
else
|
else
|
memcpy (valbuf, ®buf[REGISTER_BYTE (A1_REGNUM)], TYPE_LENGTH (type));
|
memcpy (valbuf, ®buf[REGISTER_BYTE (A1_REGNUM)], TYPE_LENGTH (type));
|
}
|
}
|
|
|
/* Return non-zero if the PC is inside a thumb call thunk. */
|
/* Return non-zero if the PC is inside a thumb call thunk. */
|
|
|
int
|
int
|
arm_in_call_stub (CORE_ADDR pc, char *name)
|
arm_in_call_stub (CORE_ADDR pc, char *name)
|
{
|
{
|
CORE_ADDR start_addr;
|
CORE_ADDR start_addr;
|
|
|
/* Find the starting address of the function containing the PC. If
|
/* Find the starting address of the function containing the PC. If
|
the caller didn't give us a name, look it up at the same time. */
|
the caller didn't give us a name, look it up at the same time. */
|
if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0)
|
if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0)
|
return 0;
|
return 0;
|
|
|
return strncmp (name, "_call_via_r", 11) == 0;
|
return strncmp (name, "_call_via_r", 11) == 0;
|
}
|
}
|
|
|
/* If PC is in a Thumb call or return stub, return the address of the
|
/* If PC is in a Thumb call or return stub, return the address of the
|
target PC, which is in a register. The thunk functions are called
|
target PC, which is in a register. The thunk functions are called
|
_called_via_xx, where x is the register name. The possible names
|
_called_via_xx, where x is the register name. The possible names
|
are r0-r9, sl, fp, ip, sp, and lr. */
|
are r0-r9, sl, fp, ip, sp, and lr. */
|
|
|
CORE_ADDR
|
CORE_ADDR
|
arm_skip_stub (CORE_ADDR pc)
|
arm_skip_stub (CORE_ADDR pc)
|
{
|
{
|
char *name;
|
char *name;
|
CORE_ADDR start_addr;
|
CORE_ADDR start_addr;
|
|
|
/* Find the starting address and name of the function containing the PC. */
|
/* Find the starting address and name of the function containing the PC. */
|
if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
|
if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
|
return 0;
|
return 0;
|
|
|
/* Call thunks always start with "_call_via_". */
|
/* Call thunks always start with "_call_via_". */
|
if (strncmp (name, "_call_via_", 10) == 0)
|
if (strncmp (name, "_call_via_", 10) == 0)
|
{
|
{
|
/* Use the name suffix to determine which register contains the
|
/* Use the name suffix to determine which register contains the
|
target PC. */
|
target PC. */
|
static char *table[15] =
|
static char *table[15] =
|
{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
|
{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
|
"r8", "r9", "sl", "fp", "ip", "sp", "lr"
|
"r8", "r9", "sl", "fp", "ip", "sp", "lr"
|
};
|
};
|
int regno;
|
int regno;
|
|
|
for (regno = 0; regno <= 14; regno++)
|
for (regno = 0; regno <= 14; regno++)
|
if (strcmp (&name[10], table[regno]) == 0)
|
if (strcmp (&name[10], table[regno]) == 0)
|
return read_register (regno);
|
return read_register (regno);
|
}
|
}
|
|
|
return 0; /* not a stub */
|
return 0; /* not a stub */
|
}
|
}
|
|
|
/* If the user changes the register disassembly flavor used for info register
|
/* If the user changes the register disassembly flavor used for info register
|
and other commands, we have to also switch the flavor used in opcodes
|
and other commands, we have to also switch the flavor used in opcodes
|
for disassembly output.
|
for disassembly output.
|
This function is run in the set disassembly_flavor command, and does that. */
|
This function is run in the set disassembly_flavor command, and does that. */
|
|
|
static void
|
static void
|
set_disassembly_flavor_sfunc (char *args, int from_tty,
|
set_disassembly_flavor_sfunc (char *args, int from_tty,
|
struct cmd_list_element *c)
|
struct cmd_list_element *c)
|
{
|
{
|
set_disassembly_flavor ();
|
set_disassembly_flavor ();
|
}
|
}
|
|
|
static void
|
static void
|
set_disassembly_flavor (void)
|
set_disassembly_flavor (void)
|
{
|
{
|
const char *setname, *setdesc, **regnames;
|
const char *setname, *setdesc, **regnames;
|
int numregs, j;
|
int numregs, j;
|
|
|
/* Find the flavor that the user wants in the opcodes table. */
|
/* Find the flavor that the user wants in the opcodes table. */
|
int current = 0;
|
int current = 0;
|
numregs = get_arm_regnames (current, &setname, &setdesc, ®names);
|
numregs = get_arm_regnames (current, &setname, &setdesc, ®names);
|
while ((disassembly_flavor != setname)
|
while ((disassembly_flavor != setname)
|
&& (current < num_flavor_options))
|
&& (current < num_flavor_options))
|
get_arm_regnames (++current, &setname, &setdesc, ®names);
|
get_arm_regnames (++current, &setname, &setdesc, ®names);
|
current_option = current;
|
current_option = current;
|
|
|
/* Fill our copy. */
|
/* Fill our copy. */
|
for (j = 0; j < numregs; j++)
|
for (j = 0; j < numregs; j++)
|
arm_register_names[j] = (char *) regnames[j];
|
arm_register_names[j] = (char *) regnames[j];
|
|
|
/* Adjust case. */
|
/* Adjust case. */
|
if (isupper (*regnames[PC_REGNUM]))
|
if (isupper (*regnames[PC_REGNUM]))
|
{
|
{
|
arm_register_names[FPS_REGNUM] = "FPS";
|
arm_register_names[FPS_REGNUM] = "FPS";
|
arm_register_names[PS_REGNUM] = "CPSR";
|
arm_register_names[PS_REGNUM] = "CPSR";
|
}
|
}
|
else
|
else
|
{
|
{
|
arm_register_names[FPS_REGNUM] = "fps";
|
arm_register_names[FPS_REGNUM] = "fps";
|
arm_register_names[PS_REGNUM] = "cpsr";
|
arm_register_names[PS_REGNUM] = "cpsr";
|
}
|
}
|
|
|
/* Synchronize the disassembler. */
|
/* Synchronize the disassembler. */
|
set_arm_regname_option (current);
|
set_arm_regname_option (current);
|
}
|
}
|
|
|
/* arm_othernames implements the "othernames" command. This is kind
|
/* arm_othernames implements the "othernames" command. This is kind
|
of hacky, and I prefer the set-show disassembly-flavor which is
|
of hacky, and I prefer the set-show disassembly-flavor which is
|
also used for the x86 gdb. I will keep this around, however, in
|
also used for the x86 gdb. I will keep this around, however, in
|
case anyone is actually using it. */
|
case anyone is actually using it. */
|
|
|
static void
|
static void
|
arm_othernames (char *names, int n)
|
arm_othernames (char *names, int n)
|
{
|
{
|
/* Circle through the various flavors. */
|
/* Circle through the various flavors. */
|
current_option = (current_option + 1) % num_flavor_options;
|
current_option = (current_option + 1) % num_flavor_options;
|
|
|
disassembly_flavor = valid_flavors[current_option];
|
disassembly_flavor = valid_flavors[current_option];
|
set_disassembly_flavor ();
|
set_disassembly_flavor ();
|
}
|
}
|
|
|
void
|
void
|
_initialize_arm_tdep (void)
|
_initialize_arm_tdep (void)
|
{
|
{
|
struct ui_file *stb;
|
struct ui_file *stb;
|
long length;
|
long length;
|
struct cmd_list_element *new_cmd;
|
struct cmd_list_element *new_cmd;
|
const char *setname, *setdesc, **regnames;
|
const char *setname, *setdesc, **regnames;
|
int numregs, i, j;
|
int numregs, i, j;
|
static char *helptext;
|
static char *helptext;
|
|
|
tm_print_insn = gdb_print_insn_arm;
|
tm_print_insn = gdb_print_insn_arm;
|
|
|
/* Get the number of possible sets of register names defined in opcodes. */
|
/* Get the number of possible sets of register names defined in opcodes. */
|
num_flavor_options = get_arm_regname_num_options ();
|
num_flavor_options = get_arm_regname_num_options ();
|
|
|
/* Sync the opcode insn printer with our register viewer: */
|
/* Sync the opcode insn printer with our register viewer: */
|
parse_arm_disassembler_option ("reg-names-std");
|
parse_arm_disassembler_option ("reg-names-std");
|
|
|
/* Begin creating the help text. */
|
/* Begin creating the help text. */
|
stb = mem_fileopen ();
|
stb = mem_fileopen ();
|
fprintf_unfiltered (stb, "Set the disassembly flavor.\n\
|
fprintf_unfiltered (stb, "Set the disassembly flavor.\n\
|
The valid values are:\n");
|
The valid values are:\n");
|
|
|
/* Initialize the array that will be passed to add_set_enum_cmd(). */
|
/* Initialize the array that will be passed to add_set_enum_cmd(). */
|
valid_flavors = xmalloc ((num_flavor_options + 1) * sizeof (char *));
|
valid_flavors = xmalloc ((num_flavor_options + 1) * sizeof (char *));
|
for (i = 0; i < num_flavor_options; i++)
|
for (i = 0; i < num_flavor_options; i++)
|
{
|
{
|
numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
|
numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
|
valid_flavors[i] = (char *) setname;
|
valid_flavors[i] = (char *) setname;
|
fprintf_unfiltered (stb, "%s - %s\n", setname,
|
fprintf_unfiltered (stb, "%s - %s\n", setname,
|
setdesc);
|
setdesc);
|
/* Copy the default names (if found) and synchronize disassembler. */
|
/* Copy the default names (if found) and synchronize disassembler. */
|
if (!strcmp (setname, "std"))
|
if (!strcmp (setname, "std"))
|
{
|
{
|
disassembly_flavor = (char *) setname;
|
disassembly_flavor = (char *) setname;
|
current_option = i;
|
current_option = i;
|
for (j = 0; j < numregs; j++)
|
for (j = 0; j < numregs; j++)
|
arm_register_names[j] = (char *) regnames[j];
|
arm_register_names[j] = (char *) regnames[j];
|
set_arm_regname_option (i);
|
set_arm_regname_option (i);
|
}
|
}
|
}
|
}
|
/* Mark the end of valid options. */
|
/* Mark the end of valid options. */
|
valid_flavors[num_flavor_options] = NULL;
|
valid_flavors[num_flavor_options] = NULL;
|
|
|
/* Finish the creation of the help text. */
|
/* Finish the creation of the help text. */
|
fprintf_unfiltered (stb, "The default is \"std\".");
|
fprintf_unfiltered (stb, "The default is \"std\".");
|
helptext = ui_file_xstrdup (stb, &length);
|
helptext = ui_file_xstrdup (stb, &length);
|
ui_file_delete (stb);
|
ui_file_delete (stb);
|
|
|
/* Add the disassembly-flavor command */
|
/* Add the disassembly-flavor command */
|
new_cmd = add_set_enum_cmd ("disassembly-flavor", no_class,
|
new_cmd = add_set_enum_cmd ("disassembly-flavor", no_class,
|
valid_flavors,
|
valid_flavors,
|
(char *) &disassembly_flavor,
|
(char *) &disassembly_flavor,
|
helptext,
|
helptext,
|
&setlist);
|
&setlist);
|
new_cmd->function.sfunc = set_disassembly_flavor_sfunc;
|
new_cmd->function.sfunc = set_disassembly_flavor_sfunc;
|
add_show_from_set (new_cmd, &showlist);
|
add_show_from_set (new_cmd, &showlist);
|
|
|
/* ??? Maybe this should be a boolean. */
|
/* ??? Maybe this should be a boolean. */
|
add_show_from_set (add_set_cmd ("apcs32", no_class,
|
add_show_from_set (add_set_cmd ("apcs32", no_class,
|
var_zinteger, (char *) &arm_apcs_32,
|
var_zinteger, (char *) &arm_apcs_32,
|
"Set usage of ARM 32-bit mode.\n", &setlist),
|
"Set usage of ARM 32-bit mode.\n", &setlist),
|
&showlist);
|
&showlist);
|
|
|
/* Add the deprecated "othernames" command */
|
/* Add the deprecated "othernames" command */
|
|
|
add_com ("othernames", class_obscure, arm_othernames,
|
add_com ("othernames", class_obscure, arm_othernames,
|
"Switch to the next set of register names.");
|
"Switch to the next set of register names.");
|
}
|
}
|
|
|
/* Test whether the coff symbol specific value corresponds to a Thumb
|
/* Test whether the coff symbol specific value corresponds to a Thumb
|
function. */
|
function. */
|
|
|
int
|
int
|
coff_sym_is_thumb (int val)
|
coff_sym_is_thumb (int val)
|
{
|
{
|
return (val == C_THUMBEXT ||
|
return (val == C_THUMBEXT ||
|
val == C_THUMBSTAT ||
|
val == C_THUMBSTAT ||
|
val == C_THUMBEXTFUNC ||
|
val == C_THUMBEXTFUNC ||
|
val == C_THUMBSTATFUNC ||
|
val == C_THUMBSTATFUNC ||
|
val == C_THUMBLABEL);
|
val == C_THUMBLABEL);
|
}
|
}
|
|
|
