/* Parameters for execution on a Matsushita mn10200 processor.
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/* Parameters for execution on a Matsushita mn10200 processor.
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Copyright 1997 Free Software Foundation, Inc.
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Copyright 1997 Free Software Foundation, Inc.
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Contributed by Geoffrey Noer <noer@cygnus.com>
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Contributed by Geoffrey Noer <noer@cygnus.com>
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This file is part of GDB.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330,
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Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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Boston, MA 02111-1307, USA. */
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/* The mn10200 is little endian. */
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/* The mn10200 is little endian. */
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#define TARGET_BYTE_ORDER LITTLE_ENDIAN
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#define TARGET_BYTE_ORDER LITTLE_ENDIAN
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/* ints are only 16bits on the mn10200. */
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/* ints are only 16bits on the mn10200. */
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#undef TARGET_INT_BIT
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#undef TARGET_INT_BIT
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#define TARGET_INT_BIT 16
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#define TARGET_INT_BIT 16
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/* The mn10200 doesn't support long long types. */
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/* The mn10200 doesn't support long long types. */
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#undef TARGET_LONG_LONG_BIT
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#undef TARGET_LONG_LONG_BIT
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#define TARGET_LONG_LONG_BIT 32
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#define TARGET_LONG_LONG_BIT 32
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/* The mn10200 doesn't support double or long double either. */
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/* The mn10200 doesn't support double or long double either. */
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#undef TARGET_DOUBLE_BIT
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#undef TARGET_DOUBLE_BIT
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#undef TARGET_LONG_DOUBLE_BIT
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#undef TARGET_LONG_DOUBLE_BIT
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#define TARGET_DOUBLE_BIT 32
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#define TARGET_DOUBLE_BIT 32
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#define TARGET_LONG_DOUBLE_BIT 32
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#define TARGET_LONG_DOUBLE_BIT 32
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/* Not strictly correct, but the machine independent code is not
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/* Not strictly correct, but the machine independent code is not
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ready to handle any of the basic sizes not being a power of two. */
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ready to handle any of the basic sizes not being a power of two. */
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#undef TARGET_PTR_BIT
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#undef TARGET_PTR_BIT
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#define TARGET_PTR_BIT 32
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#define TARGET_PTR_BIT 32
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/* The mn10200 really has 24 bit registers but the simulator reads/writes
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/* The mn10200 really has 24 bit registers but the simulator reads/writes
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them as 32bit values, so we claim they're 32bits each. This may have
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them as 32bit values, so we claim they're 32bits each. This may have
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to be tweaked if the Matsushita emulator/board really deals with them
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to be tweaked if the Matsushita emulator/board really deals with them
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as 24bits each. */
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as 24bits each. */
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#define REGISTER_SIZE 4
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#define REGISTER_SIZE 4
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#define MAX_REGISTER_RAW_SIZE REGISTER_SIZE
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#define MAX_REGISTER_RAW_SIZE REGISTER_SIZE
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#define NUM_REGS 11
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#define NUM_REGS 11
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#define REGISTER_BYTES (NUM_REGS * REGISTER_SIZE)
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#define REGISTER_BYTES (NUM_REGS * REGISTER_SIZE)
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#define REGISTER_NAMES \
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#define REGISTER_NAMES \
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{ "d0", "d1", "d2", "d3", "a0", "a1", "a2", "sp", \
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{ "d0", "d1", "d2", "d3", "a0", "a1", "a2", "sp", \
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"pc", "mdr", "psw"}
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"pc", "mdr", "psw"}
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#define FP_REGNUM 6
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#define FP_REGNUM 6
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#define SP_REGNUM 7
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#define SP_REGNUM 7
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#define PC_REGNUM 8
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#define PC_REGNUM 8
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#define MDR_REGNUM 9
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#define MDR_REGNUM 9
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#define PSW_REGNUM 10
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#define PSW_REGNUM 10
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/* Treat the registers as 32bit values. */
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/* Treat the registers as 32bit values. */
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#define REGISTER_VIRTUAL_TYPE(REG) builtin_type_long
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#define REGISTER_VIRTUAL_TYPE(REG) builtin_type_long
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#define REGISTER_BYTE(REG) ((REG) * REGISTER_SIZE)
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#define REGISTER_BYTE(REG) ((REG) * REGISTER_SIZE)
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#define REGISTER_VIRTUAL_SIZE(REG) REGISTER_SIZE
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#define REGISTER_VIRTUAL_SIZE(REG) REGISTER_SIZE
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#define REGISTER_RAW_SIZE(REG) REGISTER_SIZE
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#define REGISTER_RAW_SIZE(REG) REGISTER_SIZE
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#define MAX_REGISTER_VIRTUAL_SIZE REGISTER_SIZE
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#define MAX_REGISTER_VIRTUAL_SIZE REGISTER_SIZE
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/* The breakpoint instruction must be the same size as te smallest
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/* The breakpoint instruction must be the same size as te smallest
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instruction in the instruction set.
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instruction in the instruction set.
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The Matsushita mn10x00 processors have single byte instructions
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The Matsushita mn10x00 processors have single byte instructions
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so we need a single byte breakpoint. Matsushita hasn't defined
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so we need a single byte breakpoint. Matsushita hasn't defined
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one, so we defined it ourselves.
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one, so we defined it ourselves.
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0xff is the only available single byte insn left on the mn10200. */
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0xff is the only available single byte insn left on the mn10200. */
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#define BREAKPOINT {0xff}
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#define BREAKPOINT {0xff}
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#define FUNCTION_START_OFFSET 0
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#define FUNCTION_START_OFFSET 0
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#define DECR_PC_AFTER_BREAK 0
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#define DECR_PC_AFTER_BREAK 0
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/* Stacks grow the normal way. */
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/* Stacks grow the normal way. */
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#define INNER_THAN(lhs,rhs) ((lhs) < (rhs))
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#define INNER_THAN(lhs,rhs) ((lhs) < (rhs))
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#define SAVED_PC_AFTER_CALL(frame) \
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#define SAVED_PC_AFTER_CALL(frame) \
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(read_memory_integer (read_register (SP_REGNUM), REGISTER_SIZE) & 0xffffff)
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(read_memory_integer (read_register (SP_REGNUM), REGISTER_SIZE) & 0xffffff)
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struct frame_info;
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struct frame_info;
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struct frame_saved_regs;
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struct frame_saved_regs;
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struct type;
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struct type;
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struct value;
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struct value;
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#define EXTRA_FRAME_INFO struct frame_saved_regs fsr; int status; int stack_size;
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#define EXTRA_FRAME_INFO struct frame_saved_regs fsr; int status; int stack_size;
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extern void mn10200_init_extra_frame_info PARAMS ((struct frame_info *));
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extern void mn10200_init_extra_frame_info PARAMS ((struct frame_info *));
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#define INIT_EXTRA_FRAME_INFO(fromleaf, fi) mn10200_init_extra_frame_info (fi)
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#define INIT_EXTRA_FRAME_INFO(fromleaf, fi) mn10200_init_extra_frame_info (fi)
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#define INIT_FRAME_PC(x,y)
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#define INIT_FRAME_PC(x,y)
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extern void mn10200_frame_find_saved_regs PARAMS ((struct frame_info *,
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extern void mn10200_frame_find_saved_regs PARAMS ((struct frame_info *,
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struct frame_saved_regs *));
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struct frame_saved_regs *));
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#define FRAME_FIND_SAVED_REGS(fi, regaddr) regaddr = fi->fsr
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#define FRAME_FIND_SAVED_REGS(fi, regaddr) regaddr = fi->fsr
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extern CORE_ADDR mn10200_frame_chain PARAMS ((struct frame_info *));
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extern CORE_ADDR mn10200_frame_chain PARAMS ((struct frame_info *));
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#define FRAME_CHAIN(fi) mn10200_frame_chain (fi)
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#define FRAME_CHAIN(fi) mn10200_frame_chain (fi)
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#define FRAME_CHAIN_VALID(FP, FI) generic_file_frame_chain_valid (FP, FI)
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#define FRAME_CHAIN_VALID(FP, FI) generic_file_frame_chain_valid (FP, FI)
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extern CORE_ADDR mn10200_find_callers_reg PARAMS ((struct frame_info *, int));
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extern CORE_ADDR mn10200_find_callers_reg PARAMS ((struct frame_info *, int));
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extern CORE_ADDR mn10200_frame_saved_pc PARAMS ((struct frame_info *));
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extern CORE_ADDR mn10200_frame_saved_pc PARAMS ((struct frame_info *));
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#define FRAME_SAVED_PC(FI) (mn10200_frame_saved_pc (FI))
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#define FRAME_SAVED_PC(FI) (mn10200_frame_saved_pc (FI))
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/* Extract from an array REGBUF containing the (raw) register state
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/* Extract from an array REGBUF containing the (raw) register state
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a function return value of type TYPE, and copy that, in virtual format,
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a function return value of type TYPE, and copy that, in virtual format,
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into VALBUF. */
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into VALBUF. */
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#define EXTRACT_RETURN_VALUE(TYPE, REGBUF, VALBUF) \
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#define EXTRACT_RETURN_VALUE(TYPE, REGBUF, VALBUF) \
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{ \
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{ \
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if (TYPE_LENGTH (TYPE) > 8) \
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if (TYPE_LENGTH (TYPE) > 8) \
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abort (); \
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abort (); \
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else if (TYPE_LENGTH (TYPE) > 2 && TYPE_CODE (TYPE) != TYPE_CODE_PTR) \
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else if (TYPE_LENGTH (TYPE) > 2 && TYPE_CODE (TYPE) != TYPE_CODE_PTR) \
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{ \
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{ \
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memcpy (VALBUF, REGBUF + REGISTER_BYTE (0), 2); \
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memcpy (VALBUF, REGBUF + REGISTER_BYTE (0), 2); \
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memcpy (VALBUF + 2, REGBUF + REGISTER_BYTE (1), 2); \
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memcpy (VALBUF + 2, REGBUF + REGISTER_BYTE (1), 2); \
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} \
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} \
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else if (TYPE_CODE (TYPE) == TYPE_CODE_PTR)\
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else if (TYPE_CODE (TYPE) == TYPE_CODE_PTR)\
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{ \
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{ \
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memcpy (VALBUF, REGBUF + REGISTER_BYTE (4), TYPE_LENGTH (TYPE)); \
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memcpy (VALBUF, REGBUF + REGISTER_BYTE (4), TYPE_LENGTH (TYPE)); \
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} \
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} \
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else \
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else \
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{ \
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{ \
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memcpy (VALBUF, REGBUF + REGISTER_BYTE (0), TYPE_LENGTH (TYPE)); \
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memcpy (VALBUF, REGBUF + REGISTER_BYTE (0), TYPE_LENGTH (TYPE)); \
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} \
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} \
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}
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}
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#define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \
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#define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \
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extract_address (REGBUF + REGISTER_BYTE (4), \
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extract_address (REGBUF + REGISTER_BYTE (4), \
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REGISTER_RAW_SIZE (4))
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REGISTER_RAW_SIZE (4))
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#define STORE_RETURN_VALUE(TYPE, VALBUF) \
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#define STORE_RETURN_VALUE(TYPE, VALBUF) \
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{ \
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{ \
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if (TYPE_LENGTH (TYPE) > 8) \
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if (TYPE_LENGTH (TYPE) > 8) \
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abort (); \
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abort (); \
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else if (TYPE_LENGTH (TYPE) > 2 && TYPE_CODE (TYPE) != TYPE_CODE_PTR) \
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else if (TYPE_LENGTH (TYPE) > 2 && TYPE_CODE (TYPE) != TYPE_CODE_PTR) \
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{ \
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{ \
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write_register_bytes (REGISTER_BYTE (0), VALBUF, 2); \
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write_register_bytes (REGISTER_BYTE (0), VALBUF, 2); \
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write_register_bytes (REGISTER_BYTE (1), VALBUF + 2, 2); \
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write_register_bytes (REGISTER_BYTE (1), VALBUF + 2, 2); \
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} \
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} \
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else if (TYPE_CODE (TYPE) == TYPE_CODE_PTR)\
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else if (TYPE_CODE (TYPE) == TYPE_CODE_PTR)\
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{ \
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{ \
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write_register_bytes (REGISTER_BYTE (4), VALBUF, TYPE_LENGTH (TYPE)); \
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write_register_bytes (REGISTER_BYTE (4), VALBUF, TYPE_LENGTH (TYPE)); \
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} \
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} \
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else \
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else \
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{ \
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{ \
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write_register_bytes (REGISTER_BYTE (0), VALBUF, TYPE_LENGTH (TYPE)); \
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write_register_bytes (REGISTER_BYTE (0), VALBUF, TYPE_LENGTH (TYPE)); \
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} \
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} \
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}
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}
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extern CORE_ADDR mn10200_store_struct_return (CORE_ADDR addr, CORE_ADDR sp);
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extern CORE_ADDR mn10200_store_struct_return (CORE_ADDR addr, CORE_ADDR sp);
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#define STORE_STRUCT_RETURN(STRUCT_ADDR, SP) \
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#define STORE_STRUCT_RETURN(STRUCT_ADDR, SP) \
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(SP) = mn10200_store_struct_return (STRUCT_ADDR, SP)
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(SP) = mn10200_store_struct_return (STRUCT_ADDR, SP)
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extern CORE_ADDR mn10200_skip_prologue PARAMS ((CORE_ADDR));
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extern CORE_ADDR mn10200_skip_prologue PARAMS ((CORE_ADDR));
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#define SKIP_PROLOGUE(pc) (mn10200_skip_prologue (pc))
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#define SKIP_PROLOGUE(pc) (mn10200_skip_prologue (pc))
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#define FRAME_ARGS_SKIP 0
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#define FRAME_ARGS_SKIP 0
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#define FRAME_ARGS_ADDRESS(fi) ((fi)->frame)
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#define FRAME_ARGS_ADDRESS(fi) ((fi)->frame)
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#define FRAME_LOCALS_ADDRESS(fi) ((fi)->frame)
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#define FRAME_LOCALS_ADDRESS(fi) ((fi)->frame)
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#define FRAME_NUM_ARGS(fi) (-1)
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#define FRAME_NUM_ARGS(fi) (-1)
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extern void mn10200_pop_frame PARAMS ((struct frame_info *));
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extern void mn10200_pop_frame PARAMS ((struct frame_info *));
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#define POP_FRAME mn10200_pop_frame (get_current_frame ())
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#define POP_FRAME mn10200_pop_frame (get_current_frame ())
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#define USE_GENERIC_DUMMY_FRAMES 1
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#define USE_GENERIC_DUMMY_FRAMES 1
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#define CALL_DUMMY {0}
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#define CALL_DUMMY {0}
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#define CALL_DUMMY_START_OFFSET (0)
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#define CALL_DUMMY_START_OFFSET (0)
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#define CALL_DUMMY_BREAKPOINT_OFFSET (0)
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#define CALL_DUMMY_BREAKPOINT_OFFSET (0)
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#define CALL_DUMMY_LOCATION AT_ENTRY_POINT
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#define CALL_DUMMY_LOCATION AT_ENTRY_POINT
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#define FIX_CALL_DUMMY(DUMMY, START, FUNADDR, NARGS, ARGS, TYPE, GCCP)
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#define FIX_CALL_DUMMY(DUMMY, START, FUNADDR, NARGS, ARGS, TYPE, GCCP)
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#define CALL_DUMMY_ADDRESS() entry_point_address ()
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#define CALL_DUMMY_ADDRESS() entry_point_address ()
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extern CORE_ADDR mn10200_push_return_address PARAMS ((CORE_ADDR, CORE_ADDR));
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extern CORE_ADDR mn10200_push_return_address PARAMS ((CORE_ADDR, CORE_ADDR));
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#define PUSH_RETURN_ADDRESS(PC, SP) mn10200_push_return_address (PC, SP)
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#define PUSH_RETURN_ADDRESS(PC, SP) mn10200_push_return_address (PC, SP)
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#define PUSH_DUMMY_FRAME generic_push_dummy_frame ()
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#define PUSH_DUMMY_FRAME generic_push_dummy_frame ()
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extern CORE_ADDR
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extern CORE_ADDR
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mn10200_push_arguments PARAMS ((int, struct value **, CORE_ADDR,
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mn10200_push_arguments PARAMS ((int, struct value **, CORE_ADDR,
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unsigned char, CORE_ADDR));
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unsigned char, CORE_ADDR));
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#define PUSH_ARGUMENTS(NARGS, ARGS, SP, STRUCT_RETURN, STRUCT_ADDR) \
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#define PUSH_ARGUMENTS(NARGS, ARGS, SP, STRUCT_RETURN, STRUCT_ADDR) \
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(mn10200_push_arguments (NARGS, ARGS, SP, STRUCT_RETURN, STRUCT_ADDR))
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(mn10200_push_arguments (NARGS, ARGS, SP, STRUCT_RETURN, STRUCT_ADDR))
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#define PC_IN_CALL_DUMMY(PC, SP, FP) generic_pc_in_call_dummy (PC, SP, FP)
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#define PC_IN_CALL_DUMMY(PC, SP, FP) generic_pc_in_call_dummy (PC, SP, FP)
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#define REG_STRUCT_HAS_ADDR(gcc_p,TYPE) \
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#define REG_STRUCT_HAS_ADDR(gcc_p,TYPE) \
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(TYPE_LENGTH (TYPE) > 8)
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(TYPE_LENGTH (TYPE) > 8)
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extern use_struct_convention_fn mn10200_use_struct_convention;
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extern use_struct_convention_fn mn10200_use_struct_convention;
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#define USE_STRUCT_CONVENTION(GCC_P, TYPE) mn10200_use_struct_convention (GCC_P, TYPE)
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#define USE_STRUCT_CONVENTION(GCC_P, TYPE) mn10200_use_struct_convention (GCC_P, TYPE)
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/* Override the default get_saved_register function with
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/* Override the default get_saved_register function with
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one that takes account of generic CALL_DUMMY frames. */
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one that takes account of generic CALL_DUMMY frames. */
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#define GET_SAVED_REGISTER(raw_buffer, optimized, addrp, frame, regnum, lval) \
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#define GET_SAVED_REGISTER(raw_buffer, optimized, addrp, frame, regnum, lval) \
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generic_get_saved_register (raw_buffer, optimized, addrp, frame, regnum, lval)
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generic_get_saved_register (raw_buffer, optimized, addrp, frame, regnum, lval)
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/* Define this for Wingdb */
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/* Define this for Wingdb */
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#define TARGET_MN10200
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#define TARGET_MN10200
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