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/* i370-opc.c -- Instruction 370 (ESA/390) architecture opcode list

/* i370-opc.c -- Instruction 370 (ESA/390) architecture opcode list

   Copyright 1994, 1999, 2000 Free Software Foundation, Inc.

   Copyright 1994, 1999, 2000 Free Software Foundation, Inc.

   PowerPC version written by Ian Lance Taylor, Cygnus Support

   PowerPC version written by Ian Lance Taylor, Cygnus Support

   Rewritten for i370 ESA/390 support by Linas Vepstas <linas@linas.org> 1998, 1999

   Rewritten for i370 ESA/390 support by Linas Vepstas <linas@linas.org> 1998, 1999

This file is part of GDB, GAS, and the GNU binutils.

This file is part of GDB, GAS, and the GNU binutils.

GDB, GAS, and the GNU binutils are free software; you can redistribute

GDB, GAS, and the GNU binutils are free software; you can redistribute

them and/or modify them under the terms of the GNU General Public

them and/or modify them under the terms of the GNU General Public

License as published by the Free Software Foundation; either version

License as published by the Free Software Foundation; either version

2, or (at your option) any later version.

2, or (at your option) any later version.

GDB, GAS, and the GNU binutils are distributed in the hope that they

GDB, GAS, and the GNU binutils are distributed in the hope that they

will be useful, but WITHOUT ANY WARRANTY; without even the implied

will be useful, but WITHOUT ANY WARRANTY; without even the implied

warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See

warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See

the GNU General Public License for more details.

the GNU General Public License for more details.

You should have received a copy of the GNU General Public License

You should have received a copy of the GNU General Public License

along with this file; see the file COPYING.  If not, write to the Free

along with this file; see the file COPYING.  If not, write to the Free

Software Foundation, 59 Temple Place - Suite 330, Boston, MA

Software Foundation, 59 Temple Place - Suite 330, Boston, MA

02111-1307, USA.  */

02111-1307, USA.  */

#include <stdio.h>

#include <stdio.h>

#include "sysdep.h"

#include "sysdep.h"

#include "opcode/i370.h"

#include "opcode/i370.h"

/* This file holds the i370 opcode table.  The opcode table

/* This file holds the i370 opcode table.  The opcode table

   includes almost all of the extended instruction mnemonics.  This

   includes almost all of the extended instruction mnemonics.  This

   permits the disassembler to use them, and simplifies the assembler

   permits the disassembler to use them, and simplifies the assembler

   logic, at the cost of increasing the table size.  The table is

   logic, at the cost of increasing the table size.  The table is

   strictly constant data, so the compiler should be able to put it in

   strictly constant data, so the compiler should be able to put it in

   the .text section.

   the .text section.

   This file also holds the operand table.  All knowledge about

   This file also holds the operand table.  All knowledge about

   inserting operands into instructions and vice-versa is kept in this

   inserting operands into instructions and vice-versa is kept in this

   file.  */

   file.  */

/* Local insertion and extraction functions.  */

/* Local insertion and extraction functions.  */

static i370_insn_t insert_ss_b2  PARAMS (( i370_insn_t, long, const char **));

static i370_insn_t insert_ss_b2  PARAMS (( i370_insn_t, long, const char **));

static i370_insn_t insert_ss_d2  PARAMS (( i370_insn_t, long, const char **));

static i370_insn_t insert_ss_d2  PARAMS (( i370_insn_t, long, const char **));

static i370_insn_t insert_rxf_r3  PARAMS (( i370_insn_t, long, const char **));

static i370_insn_t insert_rxf_r3  PARAMS (( i370_insn_t, long, const char **));

static long extract_ss_b2 PARAMS (( i370_insn_t, int *));

static long extract_ss_b2 PARAMS (( i370_insn_t, int *));

static long extract_ss_d2 PARAMS (( i370_insn_t, int *));

static long extract_ss_d2 PARAMS (( i370_insn_t, int *));

static long extract_rxf_r3 PARAMS (( i370_insn_t, int *));

static long extract_rxf_r3 PARAMS (( i370_insn_t, int *));

/* The operands table.

/* The operands table.

   The fields are bits, shift, insert, extract, flags, name.

   The fields are bits, shift, insert, extract, flags, name.

   The types:

   The types:

   I370_OPERAND_GPR register, must name a register, must be present

   I370_OPERAND_GPR register, must name a register, must be present

   I370_OPERAND_RELATIVE displacement or legnth field, must be present

   I370_OPERAND_RELATIVE displacement or legnth field, must be present

   I370_OPERAND_BASE base register; if present, must name a register

   I370_OPERAND_BASE base register; if present, must name a register

                      if absent, should take value of zero

                      if absent, should take value of zero

   I370_OPERAND_INDEX index register; if present, must name a register

   I370_OPERAND_INDEX index register; if present, must name a register

                      if absent, should take value of zero

                      if absent, should take value of zero

   I370_OPERAND_OPTIONAL other optional operand (usuall reg?)

   I370_OPERAND_OPTIONAL other optional operand (usuall reg?)

*/

*/

const struct i370_operand i370_operands[] =

const struct i370_operand i370_operands[] =

{

{

  /* The zero index is used to indicate the end of the list of

  /* The zero index is used to indicate the end of the list of

     operands.  */

     operands.  */

#define UNUSED 0

#define UNUSED 0

  { 0, 0, 0, 0, 0, "unused" },

  { 0, 0, 0, 0, 0, "unused" },

  /* The R1 register field in an RR form instruction.  */

  /* The R1 register field in an RR form instruction.  */

#define RR_R1 (UNUSED + 1)

#define RR_R1 (UNUSED + 1)

#define RR_R1_MASK (0xf << 4)

#define RR_R1_MASK (0xf << 4)

  { 4, 4, 0, 0, I370_OPERAND_GPR, "RR R1" },

  { 4, 4, 0, 0, I370_OPERAND_GPR, "RR R1" },

  /* The R2 register field in an RR form instruction.  */

  /* The R2 register field in an RR form instruction.  */

#define RR_R2 (RR_R1 + 1)

#define RR_R2 (RR_R1 + 1)

#define RR_R2_MASK (0xf)

#define RR_R2_MASK (0xf)

  { 4, 0, 0, 0, I370_OPERAND_GPR, "RR R2" },

  { 4, 0, 0, 0, I370_OPERAND_GPR, "RR R2" },

  /* The I field in an RR form SVC-style instruction.  */

  /* The I field in an RR form SVC-style instruction.  */

#define RR_I (RR_R2 + 1)

#define RR_I (RR_R2 + 1)

#define RR_I_MASK (0xff)

#define RR_I_MASK (0xff)

  { 8, 0, 0, 0, I370_OPERAND_RELATIVE, "RR I (svc)" },

  { 8, 0, 0, 0, I370_OPERAND_RELATIVE, "RR I (svc)" },

  /* The R1 register field in an RRE form instruction.  */

  /* The R1 register field in an RRE form instruction.  */

#define RRE_R1 (RR_I + 1)

#define RRE_R1 (RR_I + 1)

#define RRE_R1_MASK (0xf << 4)

#define RRE_R1_MASK (0xf << 4)

  { 4, 4, 0, 0, I370_OPERAND_GPR, "RRE R1" },

  { 4, 4, 0, 0, I370_OPERAND_GPR, "RRE R1" },

  /* The R2 register field in an RRE form instruction.  */

  /* The R2 register field in an RRE form instruction.  */

#define RRE_R2 (RRE_R1 + 1)

#define RRE_R2 (RRE_R1 + 1)

#define RRE_R2_MASK (0xf)

#define RRE_R2_MASK (0xf)

  { 4, 0, 0, 0, I370_OPERAND_GPR, "RRE R2" },

  { 4, 0, 0, 0, I370_OPERAND_GPR, "RRE R2" },

  /* The R1 register field in an RRF form instruction.  */

  /* The R1 register field in an RRF form instruction.  */

#define RRF_R1 (RRE_R2 + 1)

#define RRF_R1 (RRE_R2 + 1)

#define RRF_R1_MASK (0xf << 4)

#define RRF_R1_MASK (0xf << 4)

  { 4, 4, 0, 0, I370_OPERAND_GPR, "RRF R1" },

  { 4, 4, 0, 0, I370_OPERAND_GPR, "RRF R1" },

  /* The R2 register field in an RRF form instruction.  */

  /* The R2 register field in an RRF form instruction.  */

#define RRF_R2 (RRF_R1 + 1)

#define RRF_R2 (RRF_R1 + 1)

#define RRF_R2_MASK (0xf)

#define RRF_R2_MASK (0xf)

  { 4, 0, 0, 0, I370_OPERAND_GPR, "RRF R2" },

  { 4, 0, 0, 0, I370_OPERAND_GPR, "RRF R2" },

  /* The R3 register field in an RRF form instruction.  */

  /* The R3 register field in an RRF form instruction.  */

#define RRF_R3 (RRF_R2 + 1)

#define RRF_R3 (RRF_R2 + 1)

#define RRF_R3_MASK (0xf << 12)

#define RRF_R3_MASK (0xf << 12)

  { 4, 12, 0, 0, I370_OPERAND_GPR, "RRF R3" },

  { 4, 12, 0, 0, I370_OPERAND_GPR, "RRF R3" },

  /* The R1 register field in an RX or RS form instruction.  */

  /* The R1 register field in an RX or RS form instruction.  */

#define RX_R1 (RRF_R3 + 1)

#define RX_R1 (RRF_R3 + 1)

#define RX_R1_MASK (0xf << 20)

#define RX_R1_MASK (0xf << 20)

  { 4, 20, 0, 0, I370_OPERAND_GPR, "RX R1" },

  { 4, 20, 0, 0, I370_OPERAND_GPR, "RX R1" },

  /* The X2 index field in an RX form instruction.  */

  /* The X2 index field in an RX form instruction.  */

#define RX_X2 (RX_R1 + 1)

#define RX_X2 (RX_R1 + 1)

#define RX_X2_MASK (0xf << 16)

#define RX_X2_MASK (0xf << 16)

  { 4, 16, 0, 0, I370_OPERAND_GPR | I370_OPERAND_INDEX, "RX X2"},

  { 4, 16, 0, 0, I370_OPERAND_GPR | I370_OPERAND_INDEX, "RX X2"},

  /* The B2 base field in an RX form instruction.  */

  /* The B2 base field in an RX form instruction.  */

#define RX_B2 (RX_X2 + 1)

#define RX_B2 (RX_X2 + 1)

#define RX_B2_MASK (0xf << 12)

#define RX_B2_MASK (0xf << 12)

  { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE, "RX B2"},

  { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE, "RX B2"},

  /* The D2 displacement field in an RX form instruction.  */

  /* The D2 displacement field in an RX form instruction.  */

#define RX_D2 (RX_B2 + 1)

#define RX_D2 (RX_B2 + 1)

#define RX_D2_MASK (0xfff)

#define RX_D2_MASK (0xfff)

  { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "RX D2"},

  { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "RX D2"},

 /* The R3 register field in an RXF form instruction.  */

 /* The R3 register field in an RXF form instruction.  */

#define RXF_R3 (RX_D2 + 1)

#define RXF_R3 (RX_D2 + 1)

#define RXF_R3_MASK (0xf << 12)

#define RXF_R3_MASK (0xf << 12)

  { 4, 12, insert_rxf_r3, extract_rxf_r3, I370_OPERAND_GPR, "RXF R3" },

  { 4, 12, insert_rxf_r3, extract_rxf_r3, I370_OPERAND_GPR, "RXF R3" },

  /* The D2 displacement field in an RS form instruction.  */

  /* The D2 displacement field in an RS form instruction.  */

#define RS_D2 (RXF_R3 + 1)

#define RS_D2 (RXF_R3 + 1)

#define RS_D2_MASK (0xfff)

#define RS_D2_MASK (0xfff)

  { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "RS D2"},

  { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "RS D2"},

  /* The R3 register field in an RS form instruction.  */

  /* The R3 register field in an RS form instruction.  */

#define RS_R3 (RS_D2 + 1)

#define RS_R3 (RS_D2 + 1)

#define RS_R3_MASK (0xf << 16)

#define RS_R3_MASK (0xf << 16)

  { 4, 16, 0, 0, I370_OPERAND_GPR, "RS R3" },

  { 4, 16, 0, 0, I370_OPERAND_GPR, "RS R3" },

  /* The B2 base field in an RS form instruction.  */

  /* The B2 base field in an RS form instruction.  */

#define RS_B2 (RS_R3 + 1)

#define RS_B2 (RS_R3 + 1)

#define RS_B2_MASK (0xf << 12)

#define RS_B2_MASK (0xf << 12)

  { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "RS B2"},

  { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "RS B2"},

  /* The optional B2 base field in an RS form instruction.  */

  /* The optional B2 base field in an RS form instruction.  */

  /* Note that this field will almost always be absent */

  /* Note that this field will almost always be absent */

#define RS_B2_OPT (RS_B2 + 1)

#define RS_B2_OPT (RS_B2 + 1)

#define RS_B2_OPT_MASK (0xf << 12)

#define RS_B2_OPT_MASK (0xf << 12)

  { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_OPTIONAL, "RS B2 OPT"},

  { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_OPTIONAL, "RS B2 OPT"},

  /* The R1 register field in an RSI form instruction.  */

  /* The R1 register field in an RSI form instruction.  */

#define RSI_R1 (RS_B2_OPT + 1)

#define RSI_R1 (RS_B2_OPT + 1)

#define RSI_R1_MASK (0xf << 20)

#define RSI_R1_MASK (0xf << 20)

  { 4, 20, 0, 0, I370_OPERAND_GPR, "RSI R1" },

  { 4, 20, 0, 0, I370_OPERAND_GPR, "RSI R1" },

  /* The R3 register field in an RSI form instruction.  */

  /* The R3 register field in an RSI form instruction.  */

#define RSI_R3 (RSI_R1 + 1)

#define RSI_R3 (RSI_R1 + 1)

#define RSI_R3_MASK (0xf << 16)

#define RSI_R3_MASK (0xf << 16)

  { 4, 16, 0, 0, I370_OPERAND_GPR, "RSI R3" },

  { 4, 16, 0, 0, I370_OPERAND_GPR, "RSI R3" },

  /* The I2 immediate field in an RSI form instruction.  */

  /* The I2 immediate field in an RSI form instruction.  */

#define RSI_I2 (RSI_R3 + 1)

#define RSI_I2 (RSI_R3 + 1)

#define RSI_I2_MASK (0xffff)

#define RSI_I2_MASK (0xffff)

  { 16, 0, 0, 0, I370_OPERAND_RELATIVE, "RSI I2" },

  { 16, 0, 0, 0, I370_OPERAND_RELATIVE, "RSI I2" },

  /* The R1 register field in an RI form instruction.  */

  /* The R1 register field in an RI form instruction.  */

#define RI_R1 (RSI_I2 + 1)

#define RI_R1 (RSI_I2 + 1)

#define RI_R1_MASK (0xf << 20)

#define RI_R1_MASK (0xf << 20)

  { 4, 20, 0, 0, I370_OPERAND_GPR, "RI R1" },

  { 4, 20, 0, 0, I370_OPERAND_GPR, "RI R1" },

  /* The I2 immediate field in an RI form instruction.  */

  /* The I2 immediate field in an RI form instruction.  */

#define RI_I2 (RI_R1 + 1)

#define RI_I2 (RI_R1 + 1)

#define RI_I2_MASK (0xffff)

#define RI_I2_MASK (0xffff)

  { 16, 0, 0, 0, I370_OPERAND_RELATIVE, "RI I2" },

  { 16, 0, 0, 0, I370_OPERAND_RELATIVE, "RI I2" },

 /* The I2 index field in an SI form instruction.  */

 /* The I2 index field in an SI form instruction.  */

#define SI_I2 (RI_I2 + 1)

#define SI_I2 (RI_I2 + 1)

#define SI_I2_MASK (0xff << 16)

#define SI_I2_MASK (0xff << 16)

  { 8, 16, 0, 0, I370_OPERAND_RELATIVE, "SI I2"},

  { 8, 16, 0, 0, I370_OPERAND_RELATIVE, "SI I2"},

 /* The B1 base register field in an SI form instruction.  */

 /* The B1 base register field in an SI form instruction.  */

#define SI_B1 (SI_I2 + 1)

#define SI_B1 (SI_I2 + 1)

#define SI_B1_MASK (0xf << 12)

#define SI_B1_MASK (0xf << 12)

  { 4, 12, 0, 0, I370_OPERAND_GPR, "SI B1" },

  { 4, 12, 0, 0, I370_OPERAND_GPR, "SI B1" },

  /* The D1 displacement field in an SI form instruction.  */

  /* The D1 displacement field in an SI form instruction.  */

#define SI_D1 (SI_B1 + 1)

#define SI_D1 (SI_B1 + 1)

#define SI_D1_MASK (0xfff)

#define SI_D1_MASK (0xfff)

  { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "SI D1" },

  { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "SI D1" },

 /* The B2 base register field in an S form instruction.  */

 /* The B2 base register field in an S form instruction.  */

#define S_B2 (SI_D1 + 1)

#define S_B2 (SI_D1 + 1)

#define S_B2_MASK (0xf << 12)

#define S_B2_MASK (0xf << 12)

  { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "S B2" },

  { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "S B2" },

  /* The D2 displacement field in an S form instruction.  */

  /* The D2 displacement field in an S form instruction.  */

#define S_D2 (S_B2 + 1)

#define S_D2 (S_B2 + 1)

#define S_D2_MASK (0xfff)

#define S_D2_MASK (0xfff)

  { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "S D2" },

  { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "S D2" },

  /* The L length field in an SS form instruction. */

  /* The L length field in an SS form instruction. */

#define SS_L (S_D2 + 1)

#define SS_L (S_D2 + 1)

#define SS_L_MASK (0xffff<<16)

#define SS_L_MASK (0xffff<<16)

  { 8, 16, 0, 0, I370_OPERAND_RELATIVE | I370_OPERAND_LENGTH, "SS L" },

  { 8, 16, 0, 0, I370_OPERAND_RELATIVE | I370_OPERAND_LENGTH, "SS L" },

 /* The B1 base register field in an SS form instruction.  */

 /* The B1 base register field in an SS form instruction.  */

#define SS_B1 (SS_L + 1)

#define SS_B1 (SS_L + 1)

#define SS_B1_MASK (0xf << 12)

#define SS_B1_MASK (0xf << 12)

  { 4, 12, 0, 0, I370_OPERAND_GPR, "SS B1" },

  { 4, 12, 0, 0, I370_OPERAND_GPR, "SS B1" },

  /* The D1 displacement field in an SS form instruction.  */

  /* The D1 displacement field in an SS form instruction.  */

#define SS_D1 (SS_B1 + 1)

#define SS_D1 (SS_B1 + 1)

#define SS_D1_MASK (0xfff)

#define SS_D1_MASK (0xfff)

  { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "SS D1" },

  { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "SS D1" },

 /* The B2 base register field in an SS form instruction.  */

 /* The B2 base register field in an SS form instruction.  */

#define SS_B2 (SS_D1 + 1)

#define SS_B2 (SS_D1 + 1)

#define SS_B2_MASK (0xf << 12)

#define SS_B2_MASK (0xf << 12)

  { 4, 12, insert_ss_b2, extract_ss_b2, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "SS B2" },

  { 4, 12, insert_ss_b2, extract_ss_b2, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "SS B2" },

  /* The D2 displacement field in an SS form instruction.  */

  /* The D2 displacement field in an SS form instruction.  */

#define SS_D2 (SS_B2 + 1)

#define SS_D2 (SS_B2 + 1)

#define SS_D2_MASK (0xfff)

#define SS_D2_MASK (0xfff)

  { 12, 0, insert_ss_d2, extract_ss_d2, I370_OPERAND_RELATIVE, "SS D2" },

  { 12, 0, insert_ss_d2, extract_ss_d2, I370_OPERAND_RELATIVE, "SS D2" },

};

};

/* The functions used to insert and extract complicated operands.  */

/* The functions used to insert and extract complicated operands.  */

/*ARGSUSED*/

/*ARGSUSED*/

static i370_insn_t

static i370_insn_t

insert_ss_b2 (insn, value, errmsg)

insert_ss_b2 (insn, value, errmsg)

     i370_insn_t insn;

     i370_insn_t insn;

     long value;

     long value;

     const char **errmsg;

     const char **errmsg;

{

{

  insn.i[1] |= (value & 0xf) << 28;

  insn.i[1] |= (value & 0xf) << 28;

  return insn;

  return insn;

}

}

static i370_insn_t

static i370_insn_t

insert_ss_d2 (insn, value, errmsg)

insert_ss_d2 (insn, value, errmsg)

     i370_insn_t insn;

     i370_insn_t insn;

     long value;

     long value;

     const char **errmsg;

     const char **errmsg;

{

{

  insn.i[1] |= (value & 0xfff) << 16;

  insn.i[1] |= (value & 0xfff) << 16;

  return insn;

  return insn;

}

}

static i370_insn_t

static i370_insn_t

insert_rxf_r3 (insn, value, errmsg)

insert_rxf_r3 (insn, value, errmsg)

     i370_insn_t insn;

     i370_insn_t insn;

     long value;

     long value;

     const char **errmsg;

     const char **errmsg;

{

{

  insn.i[1] |= (value & 0xf) << 28;

  insn.i[1] |= (value & 0xf) << 28;

  return insn;

  return insn;

}

}

static long

static long

extract_ss_b2 (insn, invalid)

extract_ss_b2 (insn, invalid)

     i370_insn_t insn;

     i370_insn_t insn;

     int *invalid;

     int *invalid;

{

{

  return (insn.i[1] >>28) & 0xf;

  return (insn.i[1] >>28) & 0xf;

}

}

static long

static long

extract_ss_d2 (insn, invalid)

extract_ss_d2 (insn, invalid)

     i370_insn_t insn;

     i370_insn_t insn;

     int *invalid;

     int *invalid;

{

{

  return (insn.i[1] >>16) & 0xfff;

  return (insn.i[1] >>16) & 0xfff;

}

}

static long

static long

extract_rxf_r3 (insn, invalid)

extract_rxf_r3 (insn, invalid)

     i370_insn_t insn;

     i370_insn_t insn;

     int *invalid;

     int *invalid;

{

{

  return (insn.i[1] >>28) & 0xf;

  return (insn.i[1] >>28) & 0xf;

}

}

/* Macros used to form opcodes.  */

/* Macros used to form opcodes.  */

/* The short-instruction opcode.  */

/* The short-instruction opcode.  */

#define OPS(x) ((((unsigned short)(x)) & 0xff) << 8)

#define OPS(x) ((((unsigned short)(x)) & 0xff) << 8)

#define OPS_MASK OPS (0xff)

#define OPS_MASK OPS (0xff)

/* the extended instruction opcode */

/* the extended instruction opcode */

#define XOPS(x) ((((unsigned short)(x)) & 0xff) << 24)

#define XOPS(x) ((((unsigned short)(x)) & 0xff) << 24)

#define XOPS_MASK XOPS (0xff)

#define XOPS_MASK XOPS (0xff)

/* the S instruction opcode */

/* the S instruction opcode */

#define SOPS(x) ((((unsigned short)(x)) & 0xffff) << 16)

#define SOPS(x) ((((unsigned short)(x)) & 0xffff) << 16)

#define SOPS_MASK SOPS (0xffff)

#define SOPS_MASK SOPS (0xffff)

/* the E instruction opcode */

/* the E instruction opcode */

#define EOPS(x) (((unsigned short)(x)) & 0xffff)

#define EOPS(x) (((unsigned short)(x)) & 0xffff)

#define EOPS_MASK EOPS (0xffff)

#define EOPS_MASK EOPS (0xffff)

/* the RI instruction opcode */

/* the RI instruction opcode */

#define ROPS(x) (((((unsigned short)(x)) & 0xff0) << 20) | \

#define ROPS(x) (((((unsigned short)(x)) & 0xff0) << 20) | \

                 ((((unsigned short)(x)) & 0x00f) << 16))

                 ((((unsigned short)(x)) & 0x00f) << 16))

#define ROPS_MASK ROPS (0xfff)

#define ROPS_MASK ROPS (0xfff)

/* --------------------------------------------------------- */

/* --------------------------------------------------------- */

/* An E form instruction.  */

/* An E form instruction.  */

#define E(op)  (EOPS (op))

#define E(op)  (EOPS (op))

#define E_MASK E (0xffff)

#define E_MASK E (0xffff)

/* An RR form instruction.  */

/* An RR form instruction.  */

#define RR(op, r1, r2) \

#define RR(op, r1, r2) \

  (OPS (op) | ((((unsigned short)(r1)) & 0xf) << 4) |   \

  (OPS (op) | ((((unsigned short)(r1)) & 0xf) << 4) |   \

              ((((unsigned short)(r2)) & 0xf) ))

              ((((unsigned short)(r2)) & 0xf) ))

#define RR_MASK RR (0xff, 0x0, 0x0)

#define RR_MASK RR (0xff, 0x0, 0x0)

/* An SVC-style instruction.  */

/* An SVC-style instruction.  */

#define SVC(op, i) \

#define SVC(op, i) \

  (OPS (op) | (((unsigned short)(i)) & 0xff))

  (OPS (op) | (((unsigned short)(i)) & 0xff))

#define SVC_MASK SVC (0xff, 0x0)

#define SVC_MASK SVC (0xff, 0x0)

/* An RRE form instruction.  */

/* An RRE form instruction.  */

#define RRE(op, r1, r2) \

#define RRE(op, r1, r2) \

  (SOPS (op) | ((((unsigned short)(r1)) & 0xf) << 4) |   \

  (SOPS (op) | ((((unsigned short)(r1)) & 0xf) << 4) |   \

               ((((unsigned short)(r2)) & 0xf) ))

               ((((unsigned short)(r2)) & 0xf) ))

#define RRE_MASK RRE (0xffff, 0x0, 0x0)

#define RRE_MASK RRE (0xffff, 0x0, 0x0)

/* An RRF form instruction.  */

/* An RRF form instruction.  */

#define RRF(op, r3, r1, r2) \

#define RRF(op, r3, r1, r2) \

  (SOPS (op) | ((((unsigned short)(r3)) & 0xf) << 12) |   \

  (SOPS (op) | ((((unsigned short)(r3)) & 0xf) << 12) |   \

               ((((unsigned short)(r1)) & 0xf) << 4)  |   \

               ((((unsigned short)(r1)) & 0xf) << 4)  |   \

               ((((unsigned short)(r2)) & 0xf) ))

               ((((unsigned short)(r2)) & 0xf) ))

#define RRF_MASK RRF (0xffff, 0x0, 0x0, 0x0)

#define RRF_MASK RRF (0xffff, 0x0, 0x0, 0x0)

/* An RX form instruction. */

/* An RX form instruction. */

#define RX(op, r1, x2, b2, d2) \

#define RX(op, r1, x2, b2, d2) \

  (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) |  \

  (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) |  \

              ((((unsigned short)(x2)) & 0xf) << 16) |  \

              ((((unsigned short)(x2)) & 0xf) << 16) |  \

              ((((unsigned short)(b2)) & 0xf) << 12) |  \

              ((((unsigned short)(b2)) & 0xf) << 12) |  \

              ((((unsigned short)(d2)) & 0xfff)))

              ((((unsigned short)(d2)) & 0xfff)))

#define RX_MASK RX (0xff, 0x0, 0x0, 0x0, 0x0)

#define RX_MASK RX (0xff, 0x0, 0x0, 0x0, 0x0)

/* An RXE form instruction high word. */

/* An RXE form instruction high word. */

#define RXEH(op, r1, x2, b2, d2) \

#define RXEH(op, r1, x2, b2, d2) \

  (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) |  \

  (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) |  \

              ((((unsigned short)(x2)) & 0xf) << 16) |  \

              ((((unsigned short)(x2)) & 0xf) << 16) |  \

              ((((unsigned short)(b2)) & 0xf) << 12) |  \

              ((((unsigned short)(b2)) & 0xf) << 12) |  \

              ((((unsigned short)(d2)) & 0xfff)))

              ((((unsigned short)(d2)) & 0xfff)))

#define RXEH_MASK RXEH (0xff, 0, 0, 0, 0)

#define RXEH_MASK RXEH (0xff, 0, 0, 0, 0)

/* An RXE form instruction low word. */

/* An RXE form instruction low word. */

#define RXEL(op) \

#define RXEL(op) \

              ((((unsigned short)(op)) & 0xff) << 16 )

              ((((unsigned short)(op)) & 0xff) << 16 )

#define RXEL_MASK RXEL (0xff)

#define RXEL_MASK RXEL (0xff)

/* An RXF form instruction high word. */

/* An RXF form instruction high word. */

#define RXFH(op, r1, x2, b2, d2) \

#define RXFH(op, r1, x2, b2, d2) \

  (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) |  \

  (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) |  \

              ((((unsigned short)(x2)) & 0xf) << 16) |  \

              ((((unsigned short)(x2)) & 0xf) << 16) |  \

              ((((unsigned short)(b2)) & 0xf) << 12) |  \

              ((((unsigned short)(b2)) & 0xf) << 12) |  \

              ((((unsigned short)(d2)) & 0xfff)))

              ((((unsigned short)(d2)) & 0xfff)))

#define RXFH_MASK RXFH (0xff, 0, 0, 0, 0)

#define RXFH_MASK RXFH (0xff, 0, 0, 0, 0)

/* An RXF form instruction low word. */

/* An RXF form instruction low word. */

#define RXFL(op, r3) \

#define RXFL(op, r3) \

              (((((unsigned short)(r3)) & 0xf)  << 28 ) | \

              (((((unsigned short)(r3)) & 0xf)  << 28 ) | \

               ((((unsigned short)(op)) & 0xff) << 16 ))

               ((((unsigned short)(op)) & 0xff) << 16 ))

#define RXFL_MASK RXFL (0xff, 0)

#define RXFL_MASK RXFL (0xff, 0)

/* An RS form instruction. */

/* An RS form instruction. */

#define RS(op, r1, b3, b2, d2) \

#define RS(op, r1, b3, b2, d2) \

  (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) |  \

  (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) |  \

              ((((unsigned short)(b3)) & 0xf) << 16) |  \

              ((((unsigned short)(b3)) & 0xf) << 16) |  \

              ((((unsigned short)(b2)) & 0xf) << 12) |  \

              ((((unsigned short)(b2)) & 0xf) << 12) |  \

              ((((unsigned short)(d2)) & 0xfff)))

              ((((unsigned short)(d2)) & 0xfff)))

#define RS_MASK RS (0xff, 0x0, 0x0, 0x0, 0x0)

#define RS_MASK RS (0xff, 0x0, 0x0, 0x0, 0x0)

/* An RSI form instruction. */

/* An RSI form instruction. */

#define RSI(op, r1, r3, i2) \

#define RSI(op, r1, r3, i2) \

  (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) |  \

  (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) |  \

              ((((unsigned short)(r3)) & 0xf) << 16) |  \

              ((((unsigned short)(r3)) & 0xf) << 16) |  \

              ((((unsigned short)(i2)) & 0xffff)))

              ((((unsigned short)(i2)) & 0xffff)))

#define RSI_MASK RSI (0xff, 0x0, 0x0, 0x0)

#define RSI_MASK RSI (0xff, 0x0, 0x0, 0x0)

/* An RI form instruction. */

/* An RI form instruction. */

#define RI(op, r1, i2) \

#define RI(op, r1, i2) \

  (ROPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) |  \

  (ROPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) |  \

              ((((unsigned short)(i2)) & 0xffff)))

              ((((unsigned short)(i2)) & 0xffff)))

#define RI_MASK RI (0xfff, 0x0, 0x0)

#define RI_MASK RI (0xfff, 0x0, 0x0)

/* An SI form instruction. */

/* An SI form instruction. */

#define SI(op, i2, b1, d1) \

#define SI(op, i2, b1, d1) \

  (XOPS(op) | ((((unsigned short)(i2)) & 0xff) << 16) |  \

  (XOPS(op) | ((((unsigned short)(i2)) & 0xff) << 16) |  \

              ((((unsigned short)(b1)) & 0xf)  << 12) |  \

              ((((unsigned short)(b1)) & 0xf)  << 12) |  \

              ((((unsigned short)(d1)) & 0xfff)))

              ((((unsigned short)(d1)) & 0xfff)))

#define SI_MASK SI (0xff, 0x0, 0x0, 0x0)

#define SI_MASK SI (0xff, 0x0, 0x0, 0x0)

/* An S form instruction. */

/* An S form instruction. */

#define S(op, b2, d2) \

#define S(op, b2, d2) \

  (SOPS(op) | ((((unsigned short)(b2)) & 0xf) << 12) |  \

  (SOPS(op) | ((((unsigned short)(b2)) & 0xf) << 12) |  \

              ((((unsigned short)(d2)) & 0xfff)))

              ((((unsigned short)(d2)) & 0xfff)))

#define S_MASK S (0xffff, 0x0, 0x0)

#define S_MASK S (0xffff, 0x0, 0x0)

/* An SS form instruction high word. */

/* An SS form instruction high word. */

#define SSH(op, l, b1, d1) \

#define SSH(op, l, b1, d1) \

  (XOPS(op) | ((((unsigned short)(l)) & 0xff) << 16) |  \

  (XOPS(op) | ((((unsigned short)(l)) & 0xff) << 16) |  \

              ((((unsigned short)(b1)) & 0xf)  << 12) |  \

              ((((unsigned short)(b1)) & 0xf)  << 12) |  \

              ((((unsigned short)(d1)) & 0xfff)))

              ((((unsigned short)(d1)) & 0xfff)))

/* An SS form instruction low word. */

/* An SS form instruction low word. */

#define SSL(b2, d2) \

#define SSL(b2, d2) \

            ( ((((unsigned short)(b1)) & 0xf)   << 28) |  \

            ( ((((unsigned short)(b1)) & 0xf)   << 28) |  \

              ((((unsigned short)(d1)) & 0xfff) << 16 ))

              ((((unsigned short)(d1)) & 0xfff) << 16 ))

#define SS_MASK SSH (0xff, 0x0, 0x0, 0x0)

#define SS_MASK SSH (0xff, 0x0, 0x0, 0x0)

/* An SSE form instruction high word. */

/* An SSE form instruction high word. */

#define SSEH(op, b1, d1) \

#define SSEH(op, b1, d1) \

  (SOPS(op) | ((((unsigned short)(b1)) & 0xf)  << 12) |  \

  (SOPS(op) | ((((unsigned short)(b1)) & 0xf)  << 12) |  \

              ((((unsigned short)(d1)) & 0xfff)))

              ((((unsigned short)(d1)) & 0xfff)))

/* An SSE form instruction low word. */

/* An SSE form instruction low word. */

#define SSEL(b2, d2) \

#define SSEL(b2, d2) \

            ( ((((unsigned short)(b1)) & 0xf)   << 28) |  \

            ( ((((unsigned short)(b1)) & 0xf)   << 28) |  \

              ((((unsigned short)(d1)) & 0xfff) << 16 ))

              ((((unsigned short)(d1)) & 0xfff) << 16 ))

#define SSE_MASK SSEH (0xffff, 0x0, 0x0)

#define SSE_MASK SSEH (0xffff, 0x0, 0x0)

/* Smaller names for the flags so each entry in the opcodes table will

/* Smaller names for the flags so each entry in the opcodes table will

   fit on a single line.  These flags are set up so that e.g. IXA means

   fit on a single line.  These flags are set up so that e.g. IXA means

   the insn is supported on the 370/XA or newer architecture.

   the insn is supported on the 370/XA or newer architecture.

   Note that 370 or older obsolete insn's are not supported ...

   Note that 370 or older obsolete insn's are not supported ...

 */

 */

#define IBF     I370_OPCODE_ESA390_BF

#define IBF     I370_OPCODE_ESA390_BF

#define IBS     I370_OPCODE_ESA390_BS

#define IBS     I370_OPCODE_ESA390_BS

#define ICK     I370_OPCODE_ESA390_CK

#define ICK     I370_OPCODE_ESA390_CK

#define ICM     I370_OPCODE_ESA390_CM

#define ICM     I370_OPCODE_ESA390_CM

#define IFX     I370_OPCODE_ESA390_FX

#define IFX     I370_OPCODE_ESA390_FX

#define IHX     I370_OPCODE_ESA390_HX

#define IHX     I370_OPCODE_ESA390_HX

#define IIR     I370_OPCODE_ESA390_IR

#define IIR     I370_OPCODE_ESA390_IR

#define IMI     I370_OPCODE_ESA390_MI

#define IMI     I370_OPCODE_ESA390_MI