/* Disassemble V850 instructions.
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/* Disassemble V850 instructions.
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Copyright 1996, 1997, 1998, 2000 Free Software Foundation, Inc.
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Copyright 1996, 1997, 1998, 2000 Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include <stdio.h>
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#include <stdio.h>
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#include "sysdep.h"
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#include "sysdep.h"
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#include "opcode/v850.h"
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#include "opcode/v850.h"
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#include "dis-asm.h"
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#include "dis-asm.h"
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#include "opintl.h"
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#include "opintl.h"
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static const char *const v850_reg_names[] =
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static const char *const v850_reg_names[] =
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{ "r0", "r1", "r2", "sp", "gp", "r5", "r6", "r7",
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{ "r0", "r1", "r2", "sp", "gp", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
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"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
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"r24", "r25", "r26", "r27", "r28", "r29", "ep", "lp" };
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"r24", "r25", "r26", "r27", "r28", "r29", "ep", "lp" };
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static const char *const v850_sreg_names[] =
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static const char *const v850_sreg_names[] =
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{ "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "sr6", "sr7",
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{ "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "sr6", "sr7",
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"sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
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"sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
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"ctpc", "ctpsw", "dbpc", "dbpsw", "ctbp", "sr21", "sr22", "sr23",
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"ctpc", "ctpsw", "dbpc", "dbpsw", "ctbp", "sr21", "sr22", "sr23",
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"sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31",
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"sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31",
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"sr16", "sr17", "sr18", "sr19", "sr20", "sr21", "sr22", "sr23",
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"sr16", "sr17", "sr18", "sr19", "sr20", "sr21", "sr22", "sr23",
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"sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31" };
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"sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31" };
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static const char *const v850_cc_names[] =
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static const char *const v850_cc_names[] =
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{ "v", "c/l", "z", "nh", "s/n", "t", "lt", "le",
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{ "v", "c/l", "z", "nh", "s/n", "t", "lt", "le",
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"nv", "nc/nl", "nz", "h", "ns/p", "sa", "ge", "gt" };
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"nv", "nc/nl", "nz", "h", "ns/p", "sa", "ge", "gt" };
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static int
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static int
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disassemble (memaddr, info, insn)
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disassemble (memaddr, info, insn)
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bfd_vma memaddr;
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bfd_vma memaddr;
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struct disassemble_info *info;
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struct disassemble_info *info;
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unsigned long insn;
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unsigned long insn;
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{
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{
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struct v850_opcode * op = (struct v850_opcode *)v850_opcodes;
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struct v850_opcode * op = (struct v850_opcode *)v850_opcodes;
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const struct v850_operand * operand;
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const struct v850_operand * operand;
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int match = 0;
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int match = 0;
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int short_op = ((insn & 0x0600) != 0x0600);
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int short_op = ((insn & 0x0600) != 0x0600);
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int bytes_read;
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int bytes_read;
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int target_processor;
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int target_processor;
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/* Special case: 32 bit MOV */
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/* Special case: 32 bit MOV */
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if ((insn & 0xffe0) == 0x0620)
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if ((insn & 0xffe0) == 0x0620)
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short_op = true;
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short_op = true;
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bytes_read = short_op ? 2 : 4;
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bytes_read = short_op ? 2 : 4;
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/* If this is a two byte insn, then mask off the high bits. */
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/* If this is a two byte insn, then mask off the high bits. */
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if (short_op)
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if (short_op)
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insn &= 0xffff;
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insn &= 0xffff;
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switch (info->mach)
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switch (info->mach)
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{
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{
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case 0:
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case 0:
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default:
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default:
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target_processor = PROCESSOR_V850;
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target_processor = PROCESSOR_V850;
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break;
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break;
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case bfd_mach_v850e:
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case bfd_mach_v850e:
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target_processor = PROCESSOR_V850E;
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target_processor = PROCESSOR_V850E;
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break;
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break;
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case bfd_mach_v850ea:
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case bfd_mach_v850ea:
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target_processor = PROCESSOR_V850EA;
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target_processor = PROCESSOR_V850EA;
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break;
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break;
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}
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}
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/* Find the opcode. */
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/* Find the opcode. */
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while (op->name)
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while (op->name)
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{
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{
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if ((op->mask & insn) == op->opcode
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if ((op->mask & insn) == op->opcode
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&& (op->processors & target_processor))
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&& (op->processors & target_processor))
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{
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{
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const unsigned char * opindex_ptr;
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const unsigned char * opindex_ptr;
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unsigned int opnum;
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unsigned int opnum;
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unsigned int memop;
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unsigned int memop;
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match = 1;
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match = 1;
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(*info->fprintf_func) (info->stream, "%s\t", op->name);
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(*info->fprintf_func) (info->stream, "%s\t", op->name);
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/*fprintf (stderr, "match: mask: %x insn: %x, opcode: %x, name: %s\n", op->mask, insn, op->opcode, op->name );*/
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/*fprintf (stderr, "match: mask: %x insn: %x, opcode: %x, name: %s\n", op->mask, insn, op->opcode, op->name );*/
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memop = op->memop;
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memop = op->memop;
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/* Now print the operands.
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/* Now print the operands.
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MEMOP is the operand number at which a memory
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MEMOP is the operand number at which a memory
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address specification starts, or zero if this
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address specification starts, or zero if this
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instruction has no memory addresses.
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instruction has no memory addresses.
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A memory address is always two arguments.
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A memory address is always two arguments.
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This information allows us to determine when to
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This information allows us to determine when to
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insert commas into the output stream as well as
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insert commas into the output stream as well as
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when to insert disp[reg] expressions onto the
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when to insert disp[reg] expressions onto the
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output stream. */
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output stream. */
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for (opindex_ptr = op->operands, opnum = 1;
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for (opindex_ptr = op->operands, opnum = 1;
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*opindex_ptr != 0;
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*opindex_ptr != 0;
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opindex_ptr++, opnum++)
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opindex_ptr++, opnum++)
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{
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{
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long value;
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long value;
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int flag;
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int flag;
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int status;
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int status;
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bfd_byte buffer[ 4 ];
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bfd_byte buffer[ 4 ];
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operand = &v850_operands[*opindex_ptr];
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operand = &v850_operands[*opindex_ptr];
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if (operand->extract)
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if (operand->extract)
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value = (operand->extract) (insn, 0);
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value = (operand->extract) (insn, 0);
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else
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else
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{
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{
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if (operand->bits == -1)
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if (operand->bits == -1)
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value = (insn & operand->shift);
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value = (insn & operand->shift);
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else
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else
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value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
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value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
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if (operand->flags & V850_OPERAND_SIGNED)
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if (operand->flags & V850_OPERAND_SIGNED)
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value = ((long)(value << (32 - operand->bits))
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value = ((long)(value << (32 - operand->bits))
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>> (32 - operand->bits));
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>> (32 - operand->bits));
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}
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}
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/* The first operand is always output without any
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/* The first operand is always output without any
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special handling.
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special handling.
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For the following arguments:
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For the following arguments:
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If memop && opnum == memop + 1, then we need '[' since
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If memop && opnum == memop + 1, then we need '[' since
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we're about to output the register used in a memory
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we're about to output the register used in a memory
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reference.
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reference.
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If memop && opnum == memop + 2, then we need ']' since
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If memop && opnum == memop + 2, then we need ']' since
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we just finished the register in a memory reference. We
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we just finished the register in a memory reference. We
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also need a ',' before this operand.
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also need a ',' before this operand.
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Else we just need a comma.
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Else we just need a comma.
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We may need to output a trailing ']' if the last operand
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We may need to output a trailing ']' if the last operand
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in an instruction is the register for a memory address.
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in an instruction is the register for a memory address.
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The exception (and there's always an exception) is the
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The exception (and there's always an exception) is the
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"jmp" insn which needs square brackets around it's only
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"jmp" insn which needs square brackets around it's only
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register argument. */
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register argument. */
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if (memop && opnum == memop + 1) info->fprintf_func (info->stream, "[");
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if (memop && opnum == memop + 1) info->fprintf_func (info->stream, "[");
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else if (memop && opnum == memop + 2) info->fprintf_func (info->stream, "],");
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else if (memop && opnum == memop + 2) info->fprintf_func (info->stream, "],");
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else if (memop == 1 && opnum == 1
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else if (memop == 1 && opnum == 1
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&& (operand->flags & V850_OPERAND_REG))
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&& (operand->flags & V850_OPERAND_REG))
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info->fprintf_func (info->stream, "[");
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info->fprintf_func (info->stream, "[");
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else if (opnum > 1) info->fprintf_func (info->stream, ", ");
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else if (opnum > 1) info->fprintf_func (info->stream, ", ");
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/* extract the flags, ignorng ones which do not effect disassembly output. */
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/* extract the flags, ignorng ones which do not effect disassembly output. */
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flag = operand->flags;
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flag = operand->flags;
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flag &= ~ V850_OPERAND_SIGNED;
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flag &= ~ V850_OPERAND_SIGNED;
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flag &= ~ V850_OPERAND_RELAX;
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flag &= ~ V850_OPERAND_RELAX;
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flag &= - flag;
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flag &= - flag;
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switch (flag)
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switch (flag)
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{
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{
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case V850_OPERAND_REG: info->fprintf_func (info->stream, "%s", v850_reg_names[value]); break;
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case V850_OPERAND_REG: info->fprintf_func (info->stream, "%s", v850_reg_names[value]); break;
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case V850_OPERAND_SRG: info->fprintf_func (info->stream, "%s", v850_sreg_names[value]); break;
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case V850_OPERAND_SRG: info->fprintf_func (info->stream, "%s", v850_sreg_names[value]); break;
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case V850_OPERAND_CC: info->fprintf_func (info->stream, "%s", v850_cc_names[value]); break;
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case V850_OPERAND_CC: info->fprintf_func (info->stream, "%s", v850_cc_names[value]); break;
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case V850_OPERAND_EP: info->fprintf_func (info->stream, "ep"); break;
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case V850_OPERAND_EP: info->fprintf_func (info->stream, "ep"); break;
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default: info->fprintf_func (info->stream, "%d", value); break;
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default: info->fprintf_func (info->stream, "%d", value); break;
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case V850_OPERAND_DISP:
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case V850_OPERAND_DISP:
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{
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{
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bfd_vma addr = value + memaddr;
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bfd_vma addr = value + memaddr;
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/* On the v850 the top 8 bits of an address are used by an overlay manager.
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/* On the v850 the top 8 bits of an address are used by an overlay manager.
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Thus it may happen that when we are looking for a symbol to match
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Thus it may happen that when we are looking for a symbol to match
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against an address with some of its top bits set, the search fails to
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against an address with some of its top bits set, the search fails to
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turn up an exact match. In this case we try to find an exact match
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turn up an exact match. In this case we try to find an exact match
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against a symbol in the lower address space, and if we find one, we
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against a symbol in the lower address space, and if we find one, we
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use that address. We only do this for JARL instructions however, as
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use that address. We only do this for JARL instructions however, as
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we do not want to misinterpret branch instructions. */
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we do not want to misinterpret branch instructions. */
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if (operand->bits == 22)
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if (operand->bits == 22)
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{
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{
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if ( ! info->symbol_at_address_func (addr, info)
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if ( ! info->symbol_at_address_func (addr, info)
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&& ((addr & 0xFF000000) != 0)
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&& ((addr & 0xFF000000) != 0)
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&& info->symbol_at_address_func (addr & 0x00FFFFFF, info))
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&& info->symbol_at_address_func (addr & 0x00FFFFFF, info))
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{
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{
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addr &= 0x00FFFFFF;
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addr &= 0x00FFFFFF;
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}
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}
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}
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}
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info->print_address_func (addr, info);
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info->print_address_func (addr, info);
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break;
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break;
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}
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}
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case V850E_PUSH_POP:
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case V850E_PUSH_POP:
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{
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{
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static int list12_regs[32] = { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 };
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static int list12_regs[32] = { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 };
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static int list18_h_regs[32] = { 19, 18, 17, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1, 30, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 };
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static int list18_h_regs[32] = { 19, 18, 17, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1, 30, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 };
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static int list18_l_regs[32] = { 3, 2, 1, -2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1, 14, 15, 13, 12, 7, 6, 5, 4, 11, 10, 9, 8 };
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static int list18_l_regs[32] = { 3, 2, 1, -2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1, 14, 15, 13, 12, 7, 6, 5, 4, 11, 10, 9, 8 };
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int * regs;
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int * regs;
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int i;
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int i;
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unsigned long int mask = 0;
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unsigned long int mask = 0;
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int pc = false;
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int pc = false;
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int sr = false;
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int sr = false;
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switch (operand->shift)
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switch (operand->shift)
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{
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{
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case 0xffe00001: regs = list12_regs; break;
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case 0xffe00001: regs = list12_regs; break;
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case 0xfff8000f: regs = list18_h_regs; break;
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case 0xfff8000f: regs = list18_h_regs; break;
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case 0xfff8001f: regs = list18_l_regs; value &= ~0x10; break; /* Do not include magic bit */
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case 0xfff8001f: regs = list18_l_regs; value &= ~0x10; break; /* Do not include magic bit */
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default:
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default:
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/* xgettext:c-format */
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/* xgettext:c-format */
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fprintf (stderr, _("unknown operand shift: %x\n"), operand->shift );
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fprintf (stderr, _("unknown operand shift: %x\n"), operand->shift );
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abort();
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abort();
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}
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}
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for (i = 0; i < 32; i++)
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for (i = 0; i < 32; i++)
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{
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{
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if (value & (1 << i))
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if (value & (1 << i))
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{
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{
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switch (regs[ i ])
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switch (regs[ i ])
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{
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{
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default: mask |= (1 << regs[ i ]); break;
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default: mask |= (1 << regs[ i ]); break;
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/* xgettext:c-format */
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/* xgettext:c-format */
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case 0: fprintf (stderr, _("unknown pop reg: %d\n"), i ); abort();
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case 0: fprintf (stderr, _("unknown pop reg: %d\n"), i ); abort();
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case -1: pc = true; break;
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case -1: pc = true; break;
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case -2: sr = true; break;
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case -2: sr = true; break;
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}
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}
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}
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}
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}
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}
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info->fprintf_func (info->stream, "{");
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info->fprintf_func (info->stream, "{");
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if (mask || pc || sr)
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if (mask || pc || sr)
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{
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{
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if (mask)
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if (mask)
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{
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{
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unsigned int bit;
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unsigned int bit;
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int shown_one = false;
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int shown_one = false;
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for (bit = 0; bit < 32; bit++)
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for (bit = 0; bit < 32; bit++)
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if (mask & (1 << bit))
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if (mask & (1 << bit))
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{
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{
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unsigned long int first = bit;
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unsigned long int first = bit;
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unsigned long int last;
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unsigned long int last;
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if (shown_one)
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if (shown_one)
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info->fprintf_func (info->stream, ", ");
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info->fprintf_func (info->stream, ", ");
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else
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else
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shown_one = true;
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shown_one = true;
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info->fprintf_func (info->stream, v850_reg_names[first]);
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info->fprintf_func (info->stream, v850_reg_names[first]);
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for (bit++; bit < 32; bit++)
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for (bit++; bit < 32; bit++)
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if ((mask & (1 << bit)) == 0)
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if ((mask & (1 << bit)) == 0)
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break;
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break;
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last = bit;
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last = bit;
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if (last > first + 1)
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if (last > first + 1)
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{
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{
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info->fprintf_func (info->stream, " - %s", v850_reg_names[ last - 1 ]);
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info->fprintf_func (info->stream, " - %s", v850_reg_names[ last - 1 ]);
|
}
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}
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}
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}
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}
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}
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if (pc)
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if (pc)
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info->fprintf_func (info->stream, "%sPC", mask ? ", " : "");
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info->fprintf_func (info->stream, "%sPC", mask ? ", " : "");
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if (sr)
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if (sr)
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info->fprintf_func (info->stream, "%sSR", (mask || pc) ? ", " : "");
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info->fprintf_func (info->stream, "%sSR", (mask || pc) ? ", " : "");
|
}
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}
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|
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info->fprintf_func (info->stream, "}");
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info->fprintf_func (info->stream, "}");
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}
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}
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break;
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break;
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|
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case V850E_IMMEDIATE16:
|
case V850E_IMMEDIATE16:
|
status = info->read_memory_func (memaddr + bytes_read, buffer, 2, info);
|
status = info->read_memory_func (memaddr + bytes_read, buffer, 2, info);
|
if (status == 0)
|
if (status == 0)
|
{
|
{
|
bytes_read += 2;
|
bytes_read += 2;
|
value = bfd_getl16 (buffer);
|
value = bfd_getl16 (buffer);
|
|
|
/* If this is a DISPOSE instruction with ff set to 0x10, then shift value up by 16. */
|
/* If this is a DISPOSE instruction with ff set to 0x10, then shift value up by 16. */
|
if ((insn & 0x001fffc0) == 0x00130780)
|
if ((insn & 0x001fffc0) == 0x00130780)
|
value <<= 16;
|
value <<= 16;
|
|
|
info->fprintf_func (info->stream, "0x%x", value);
|
info->fprintf_func (info->stream, "0x%x", value);
|
}
|
}
|
else
|
else
|
{
|
{
|
info->memory_error_func (status, memaddr + bytes_read, info);
|
info->memory_error_func (status, memaddr + bytes_read, info);
|
}
|
}
|
break;
|
break;
|
|
|
case V850E_IMMEDIATE32:
|
case V850E_IMMEDIATE32:
|
status = info->read_memory_func (memaddr + bytes_read, buffer, 4, info);
|
status = info->read_memory_func (memaddr + bytes_read, buffer, 4, info);
|
if (status == 0)
|
if (status == 0)
|
{
|
{
|
bytes_read += 4;
|
bytes_read += 4;
|
value = bfd_getl32 (buffer);
|
value = bfd_getl32 (buffer);
|
info->fprintf_func (info->stream, "0x%lx", value);
|
info->fprintf_func (info->stream, "0x%lx", value);
|
}
|
}
|
else
|
else
|
{
|
{
|
info->memory_error_func (status, memaddr + bytes_read, info);
|
info->memory_error_func (status, memaddr + bytes_read, info);
|
}
|
}
|
break;
|
break;
|
}
|
}
|
|
|
/* Handle jmp correctly. */
|
/* Handle jmp correctly. */
|
if (memop == 1 && opnum == 1
|
if (memop == 1 && opnum == 1
|
&& ((operand->flags & V850_OPERAND_REG) != 0))
|
&& ((operand->flags & V850_OPERAND_REG) != 0))
|
(*info->fprintf_func) (info->stream, "]");
|
(*info->fprintf_func) (info->stream, "]");
|
}
|
}
|
|
|
/* Close any square bracket we left open. */
|
/* Close any square bracket we left open. */
|
if (memop && opnum == memop + 2)
|
if (memop && opnum == memop + 2)
|
(*info->fprintf_func) (info->stream, "]");
|
(*info->fprintf_func) (info->stream, "]");
|
|
|
/* All done. */
|
/* All done. */
|
break;
|
break;
|
}
|
}
|
op++;
|
op++;
|
}
|
}
|
|
|
if (!match)
|
if (!match)
|
{
|
{
|
if (short_op)
|
if (short_op)
|
info->fprintf_func (info->stream, ".short\t0x%04x", insn);
|
info->fprintf_func (info->stream, ".short\t0x%04x", insn);
|
else
|
else
|
info->fprintf_func (info->stream, ".long\t0x%08x", insn);
|
info->fprintf_func (info->stream, ".long\t0x%08x", insn);
|
}
|
}
|
|
|
return bytes_read;
|
return bytes_read;
|
}
|
}
|
|
|
int
|
int
|
print_insn_v850 (memaddr, info)
|
print_insn_v850 (memaddr, info)
|
bfd_vma memaddr;
|
bfd_vma memaddr;
|
struct disassemble_info * info;
|
struct disassemble_info * info;
|
{
|
{
|
int status;
|
int status;
|
bfd_byte buffer[ 4 ];
|
bfd_byte buffer[ 4 ];
|
unsigned long insn = 0;
|
unsigned long insn = 0;
|
|
|
/* First figure out how big the opcode is. */
|
/* First figure out how big the opcode is. */
|
|
|
status = info->read_memory_func (memaddr, buffer, 2, info);
|
status = info->read_memory_func (memaddr, buffer, 2, info);
|
if (status == 0)
|
if (status == 0)
|
{
|
{
|
insn = bfd_getl16 (buffer);
|
insn = bfd_getl16 (buffer);
|
|
|
if ( (insn & 0x0600) == 0x0600
|
if ( (insn & 0x0600) == 0x0600
|
&& (insn & 0xffe0) != 0x0620)
|
&& (insn & 0xffe0) != 0x0620)
|
{
|
{
|
/* If this is a 4 byte insn, read 4 bytes of stuff. */
|
/* If this is a 4 byte insn, read 4 bytes of stuff. */
|
status = info->read_memory_func (memaddr, buffer, 4, info);
|
status = info->read_memory_func (memaddr, buffer, 4, info);
|
|
|
if (status == 0)
|
if (status == 0)
|
insn = bfd_getl32 (buffer);
|
insn = bfd_getl32 (buffer);
|
}
|
}
|
}
|
}
|
|
|
if (status != 0)
|
if (status != 0)
|
{
|
{
|
info->memory_error_func (status, memaddr, info);
|
info->memory_error_func (status, memaddr, info);
|
return -1;
|
return -1;
|
}
|
}
|
|
|
/* Make sure we tell our caller how many bytes we consumed. */
|
/* Make sure we tell our caller how many bytes we consumed. */
|
return disassemble (memaddr, info, insn);
|
return disassemble (memaddr, info, insn);
|
}
|
}
|
|
|
