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1. MEC and ERC32 emulation
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1. MEC and ERC32 emulation
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The file 'erc32.c' contains a model of the MEC, 512 K rom and 4 M ram.
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The file 'erc32.c' contains a model of the MEC, 512 K rom and 4 M ram.
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The following paragraphs outline the implemented MEC functions.
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The following paragraphs outline the implemented MEC functions.
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1.1 UARTs
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1.1 UARTs
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The UARTs are connected to two pseudo-devices, /dev/ttypc and /dev/ttypd.
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The UARTs are connected to two pseudo-devices, /dev/ttypc and /dev/ttypd.
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The following registers are implemeted:
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The following registers are implemeted:
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- UART A RX and TX register (0x01f800e0)
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- UART A RX and TX register (0x01f800e0)
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- UART B RX and TX register (0x01f800e4)
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- UART B RX and TX register (0x01f800e4)
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- UART status register (0x01f800e8)
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- UART status register (0x01f800e8)
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To speed up simulation, the UARTs operate at approximately 115200 baud.
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To speed up simulation, the UARTs operate at approximately 115200 baud.
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The UARTs generate interrupt 4 and 5 after each received or transmitted
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The UARTs generate interrupt 4 and 5 after each received or transmitted
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character. The error interrupt is generated if overflow occurs - other
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character. The error interrupt is generated if overflow occurs - other
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errors cannot occure.
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errors cannot occure.
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1.2 Real-time clock and general pupose timer A
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1.2 Real-time clock and general pupose timer A
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The following registers are implemeted:
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The following registers are implemeted:
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- Real-time clock timer (0x01f80080, read-only)
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- Real-time clock timer (0x01f80080, read-only)
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- Real-time clock scaler program register (0x01f80084, write-only)
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- Real-time clock scaler program register (0x01f80084, write-only)
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- Real-time clock counter program register (0x01f80080, write-only)
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- Real-time clock counter program register (0x01f80080, write-only)
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- Genearl pupose timer (0x01f80088, read-only)
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- Genearl pupose timer (0x01f80088, read-only)
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- Real-time clock scaler program register (0x01f8008c, write-only)
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- Real-time clock scaler program register (0x01f8008c, write-only)
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- General purpose timer counter prog. register (0x01f80088, write-only)
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- General purpose timer counter prog. register (0x01f80088, write-only)
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- Timer control register (0x01f80098, write-only)
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- Timer control register (0x01f80098, write-only)
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1.3 Interrupt controller
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1.3 Interrupt controller
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The interrupt controller is implemented as in the MEC specification with
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The interrupt controller is implemented as in the MEC specification with
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the exception of the interrupt shape register. Since external interrupts
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the exception of the interrupt shape register. Since external interrupts
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are not possible, the interrupt shape register is not implemented. The
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are not possible, the interrupt shape register is not implemented. The
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only internal interrupts that are generated are the real-time clock,
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only internal interrupts that are generated are the real-time clock,
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the general purpose timer and UARTs. However, all 15 interrupts
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the general purpose timer and UARTs. However, all 15 interrupts
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can be tested via the interrupt force register.
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can be tested via the interrupt force register.
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The following registers are implemeted:
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The following registers are implemeted:
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- Interrupt pending register (0x01f80048, read-only)
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- Interrupt pending register (0x01f80048, read-only)
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- Interrupt mask register (0x01f8004c, read-write)
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- Interrupt mask register (0x01f8004c, read-write)
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- Interrupt clear register (0x01f80050, write-only)
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- Interrupt clear register (0x01f80050, write-only)
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- Interrupt force register (0x01f80054, read-write)
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- Interrupt force register (0x01f80054, read-write)
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1.4 Breakpoint and watchpoint register
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1.4 Breakpoint and watchpoint register
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The breakpoint and watchpoint functions are implemented as in the MEC
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The breakpoint and watchpoint functions are implemented as in the MEC
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specification. Traps are correctly generated, and the system fault status
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specification. Traps are correctly generated, and the system fault status
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register is updated accordingly. Implemeted registers are:
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register is updated accordingly. Implemeted registers are:
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- Debug control register (0x01f800c0, read-write)
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- Debug control register (0x01f800c0, read-write)
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- Breakpoint register (0x01f800c4, write-only)
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- Breakpoint register (0x01f800c4, write-only)
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- Watchpoint register (0x01f800c8, write-only)
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- Watchpoint register (0x01f800c8, write-only)
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- System fault status register (0x01f800a0, read-write)
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- System fault status register (0x01f800a0, read-write)
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- Firts failing address register (0x01f800a4, read-write)
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- Firts failing address register (0x01f800a4, read-write)
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1.5 Memory interface
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1.5 Memory interface
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The following memory areas are valid for the ERC32 simulator:
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The following memory areas are valid for the ERC32 simulator:
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0x00000000 - 0x00080000 ROM (512 Kbyte, loaded at start-up)
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0x00000000 - 0x00080000 ROM (512 Kbyte, loaded at start-up)
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0x02000000 - 0x02400000 RAM (4 Mbyte, initialised to 0x0)
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0x02000000 - 0x02400000 RAM (4 Mbyte, initialised to 0x0)
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0x01f80000 - 0x01f800ff MEC registers
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0x01f80000 - 0x01f800ff MEC registers
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Access to unimplemented MEC registers or non-existing memory will result
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Access to unimplemented MEC registers or non-existing memory will result
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in a memory exception trap. However, access to unimplemented MEC registers
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in a memory exception trap. However, access to unimplemented MEC registers
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in the area 0x01f80000 - 0x01f80100 will not cause a memory exception trap.
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in the area 0x01f80000 - 0x01f80100 will not cause a memory exception trap.
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The written value will be stored in a register and can be read back. It
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The written value will be stored in a register and can be read back. It
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does however not affect the function in any way.
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does however not affect the function in any way.
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The memory configuartion register is used to define available memory
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The memory configuartion register is used to define available memory
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in the system. The fields RSIZ and PSIZ are used to set RAM and ROM
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in the system. The fields RSIZ and PSIZ are used to set RAM and ROM
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size, the remaining fields are not used. NOTE: after reset, the MEC
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size, the remaining fields are not used. NOTE: after reset, the MEC
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is set to decode 4 Kbyte of ROM and 256 Kbyte of RAM. The memory
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is set to decode 4 Kbyte of ROM and 256 Kbyte of RAM. The memory
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configuration register has to be updated to reflect the available memory.
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configuration register has to be updated to reflect the available memory.
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The waitstate configuration register is used to generate waitstates.
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The waitstate configuration register is used to generate waitstates.
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This register must also be updated with the correct configuration after
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This register must also be updated with the correct configuration after
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reset.
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reset.
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The memory protection scheme is implemented - it is enabled through bit 3
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The memory protection scheme is implemented - it is enabled through bit 3
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in the MEC control register.
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in the MEC control register.
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The following registers are implemeted:
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The following registers are implemeted:
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- MEC control register (bit 3 only) (0x01f80000, read-write)
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- MEC control register (bit 3 only) (0x01f80000, read-write)
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- Memory control register (0x01f80010, read-write)
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- Memory control register (0x01f80010, read-write)
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- Waitstate configuration register (0x01f80018, read-write)
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- Waitstate configuration register (0x01f80018, read-write)
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- Memory access register 0 (0x01f80020, read-write)
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- Memory access register 0 (0x01f80020, read-write)
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- Memory access register 1 (0x01f80024, read-write)
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- Memory access register 1 (0x01f80024, read-write)
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1.6 Watchdog
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1.6 Watchdog
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The watchdog is implemented as in the specification. The input clock is
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The watchdog is implemented as in the specification. The input clock is
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always the system clock regardsless of WDCS bit in mec configuration
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always the system clock regardsless of WDCS bit in mec configuration
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register.
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register.
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The following registers are implemeted:
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The following registers are implemeted:
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- Watchdog program and acknowledge register (0x01f80060, write-only)
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- Watchdog program and acknowledge register (0x01f80060, write-only)
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- Watchdog trap door set register (0x01f80064, write-only)
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- Watchdog trap door set register (0x01f80064, write-only)
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1.7 Software reset register
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1.7 Software reset register
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Implemented as in the specification (0x01f800004, write-only).
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Implemented as in the specification (0x01f800004, write-only).
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1.8 Power-down mode
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1.8 Power-down mode
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The power-down register (0x01f800008) is implemented as in the specification.
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The power-down register (0x01f800008) is implemented as in the specification.
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However, if the simulator event queue is empty, power-down mode is not
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However, if the simulator event queue is empty, power-down mode is not
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entered since no interrupt would be generated to exit from the mode. A
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entered since no interrupt would be generated to exit from the mode. A
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Ctrl-C in the simulator window will exit the power-down mode.
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Ctrl-C in the simulator window will exit the power-down mode.
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1.9 MEC control register
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1.9 MEC control register
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The following bits are implemented in the MEC control register:
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The following bits are implemented in the MEC control register:
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Bit Name Function
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Bit Name Function
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0 PRD Power-down mode enable
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0 PRD Power-down mode enable
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1 SWR Soft reset enable
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1 SWR Soft reset enable
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3 APR Access protection enable
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3 APR Access protection enable
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