// -*- C -*-
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// -*- C -*-
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//
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//
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//
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//
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// MIPS Architecture:
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// MIPS Architecture:
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//
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//
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// CPU Instruction Set (mips16)
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// CPU Instruction Set (mips16)
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//
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//
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// The instructions in this section are ordered according
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// The instructions in this section are ordered according
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// to http://www.sgi.com/MIPS/arch/MIPS16/mips16.pdf.
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// to http://www.sgi.com/MIPS/arch/MIPS16/mips16.pdf.
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// The MIPS16 codes registers in a special way, map from one to the other.
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// The MIPS16 codes registers in a special way, map from one to the other.
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// :::::::
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// :::::::
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:compute:::int:TRX:RX:((RX < 2) ? (16 + RX) \: RX)
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:compute:::int:TRX:RX:((RX < 2) ? (16 + RX) \: RX)
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:compute:::int:TRY:RY:((RY < 2) ? (16 + RY) \: RY)
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:compute:::int:TRY:RY:((RY < 2) ? (16 + RY) \: RY)
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:compute:::int:TRZ:RZ:((RZ < 2) ? (16 + RZ) \: RZ)
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:compute:::int:TRZ:RZ:((RZ < 2) ? (16 + RZ) \: RZ)
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:compute:::int:SHIFT:SHAMT:((SHAMT == 0) ? 8 \: SHAMT)
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:compute:::int:SHIFT:SHAMT:((SHAMT == 0) ? 8 \: SHAMT)
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:compute:::int:SHAMT:SHAMT_4_0,S5:(LSINSERTED (S5, 5, 5) | SHAMT_4_0)
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:compute:::int:SHAMT:SHAMT_4_0,S5:(LSINSERTED (S5, 5, 5) | SHAMT_4_0)
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:compute:::address_word:IMMEDIATE:IMM_25_21,IMM_20_16,IMMED_15_0:(LSINSERTED (IMM_25_21, 25, 21) | LSINSERTED (IMM_20_16, 20, 16) | LSINSERTED (IMMED_15_0, 15, 0))
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:compute:::address_word:IMMEDIATE:IMM_25_21,IMM_20_16,IMMED_15_0:(LSINSERTED (IMM_25_21, 25, 21) | LSINSERTED (IMM_20_16, 20, 16) | LSINSERTED (IMMED_15_0, 15, 0))
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:compute:::int:R32:R32L,R32H:((R32H << 3) | R32L)
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:compute:::int:R32:R32L,R32H:((R32H << 3) | R32L)
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:compute:::address_word:IMMEDIATE:IMM_10_5,IMM_15_11,IMM_4_0:(LSINSERTED (IMM_10_5, 10, 5) | LSINSERTED (IMM_15_11, 15, 11) | LSINSERTED (IMM_4_0, 4, 0))
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:compute:::address_word:IMMEDIATE:IMM_10_5,IMM_15_11,IMM_4_0:(LSINSERTED (IMM_10_5, 10, 5) | LSINSERTED (IMM_15_11, 15, 11) | LSINSERTED (IMM_4_0, 4, 0))
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:compute:::address_word:IMMEDIATE:IMM_10_4,IMM_14_11,IMM_3_0:(LSINSERTED (IMM_10_4, 10, 4) | LSINSERTED (IMM_14_11, 14, 11) | LSINSERTED (IMM_3_0, 3, 0))
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:compute:::address_word:IMMEDIATE:IMM_10_4,IMM_14_11,IMM_3_0:(LSINSERTED (IMM_10_4, 10, 4) | LSINSERTED (IMM_14_11, 14, 11) | LSINSERTED (IMM_3_0, 3, 0))
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// Load and Store Instructions
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// Load and Store Instructions
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10000,3.RX,3.RY,5.IMMED:RRI:16::LB
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10000,3.RX,3.RY,5.IMMED:RRI:16::LB
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"lb r, (r)"
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"lb r, (r)"
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*mips16:
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*mips16:
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*vr4100:
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*vr4100:
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{
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{
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GPR[TRY] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED));
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GPR[TRY] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED));
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}
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}
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11110,6.IMM_10_5,5.IMM_15_11 + 10000,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LB
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11110,6.IMM_10_5,5.IMM_15_11 + 10000,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LB
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"lb r, (r)"
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"lb r, (r)"
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*mips16:
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*mips16:
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*vr4100:
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*vr4100:
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{
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{
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GPR[TRY] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[TRX], EXTEND16 (IMMEDIATE)));
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GPR[TRY] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[TRX], EXTEND16 (IMMEDIATE)));
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}
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}
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10100,3.RX,3.RY,5.IMMED:RRI:16::LBU
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10100,3.RX,3.RY,5.IMMED:RRI:16::LBU
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"lbu r, (r)"
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"lbu r, (r)"
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*mips16:
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*mips16:
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*vr4100:
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*vr4100:
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{
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{
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GPR[TRY] = do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED);
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GPR[TRY] = do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED);
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}
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}
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11110,6.IMM_10_5,5.IMM_15_11 + 10100,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LBU
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11110,6.IMM_10_5,5.IMM_15_11 + 10100,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LBU
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"lbu r, (r)"
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"lbu r, (r)"
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*mips16:
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*mips16:
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*vr4100:
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*vr4100:
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{
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{
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GPR[TRY] = do_load (SD_, AccessLength_BYTE, GPR[TRX], EXTEND16 (IMMEDIATE));
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GPR[TRY] = do_load (SD_, AccessLength_BYTE, GPR[TRX], EXTEND16 (IMMEDIATE));
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}
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}
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10001,3.RX,3.RY,5.IMMED:RRI:16::LH
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10001,3.RX,3.RY,5.IMMED:RRI:16::LH
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"lh r, (r)"
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"lh r, (r)"
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*mips16:
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*mips16:
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*vr4100:
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*vr4100:
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{
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{
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GPR[TRY] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1));
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GPR[TRY] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1));
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}
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}
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11110,6.IMM_10_5,5.IMM_15_11 + 10001,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LH
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11110,6.IMM_10_5,5.IMM_15_11 + 10001,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LH
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"lh r, (r)"
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"lh r, (r)"
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*mips16:
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*mips16:
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*vr4100:
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*vr4100:
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{
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{
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GPR[TRY] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[TRX], EXTEND16 (IMMEDIATE)));
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GPR[TRY] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[TRX], EXTEND16 (IMMEDIATE)));
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}
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}
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10101,3.RX,3.RY,5.IMMED:RRI:16::LHU
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10101,3.RX,3.RY,5.IMMED:RRI:16::LHU
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"lhu r, (r)"
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"lhu r, (r)"
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*mips16:
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*mips16:
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*vr4100:
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*vr4100:
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{
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{
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GPR[TRY] = do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1);
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GPR[TRY] = do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1);
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}
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}
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11110,6.IMM_10_5,5.IMM_15_11 + 10101,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LHU
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11110,6.IMM_10_5,5.IMM_15_11 + 10101,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LHU
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"lhu r, (r)"
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"lhu r, (r)"
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*mips16:
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*mips16:
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*vr4100:
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*vr4100:
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{
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{
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GPR[TRY] = do_load (SD_, AccessLength_HALFWORD, GPR[TRX], EXTEND16 (IMMEDIATE));
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GPR[TRY] = do_load (SD_, AccessLength_HALFWORD, GPR[TRX], EXTEND16 (IMMEDIATE));
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}
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}
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10011,3.RX,3.RY,5.IMMED:RRI:16::LW
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10011,3.RX,3.RY,5.IMMED:RRI:16::LW
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"lw r, (r)"
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"lw r, (r)"
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*mips16:
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*mips16:
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*vr4100:
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*vr4100:
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{
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{
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GPR[TRY] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2));
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GPR[TRY] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2));
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}
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}
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11110,6.IMM_10_5,5.IMM_15_11 + 10011,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LW
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11110,6.IMM_10_5,5.IMM_15_11 + 10011,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LW
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"lw r, (r)"
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"lw r, (r)"
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*mips16:
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*mips16:
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*vr4100:
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*vr4100:
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{
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{
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GPR[TRY] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[TRX], EXTEND16 (IMMEDIATE)));
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GPR[TRY] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[TRX], EXTEND16 (IMMEDIATE)));
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}
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}
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10110,3.RX,8.IMMED:RI:16::LWPC
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10110,3.RX,8.IMMED:RI:16::LWPC
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"lw r, (PC)"
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"lw r, (PC)"
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*mips16:
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*mips16:
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*vr4100:
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*vr4100:
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{
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{
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GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD,
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GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD,
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basepc (SD_) & ~3, IMMED << 2));
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basepc (SD_) & ~3, IMMED << 2));
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}
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}
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11110,6.IMM_10_5,5.IMM_15_11 + 10110,3.RX,000,5.IMM_4_0:EXT-RI:16::LWPC
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11110,6.IMM_10_5,5.IMM_15_11 + 10110,3.RX,000,5.IMM_4_0:EXT-RI:16::LWPC
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"lw r, (PC)"
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"lw r, (PC)"
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*mips16:
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*mips16:
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*vr4100:
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*vr4100:
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{
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{
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GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, basepc (SD_) & ~3, EXTEND16 (IMMEDIATE)));
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GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, basepc (SD_) & ~3, EXTEND16 (IMMEDIATE)));
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}
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}
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10010,3.RX,8.IMMED:RI:16::LWSP
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10010,3.RX,8.IMMED:RI:16::LWSP
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"lw r, (SP)"
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"lw r, (SP)"
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*mips16:
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*mips16:
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*vr4100:
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*vr4100:
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{
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{
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GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, SP, IMMED << 2));
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GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, SP, IMMED << 2));
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}
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}
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11110,6.IMM_10_5,5.IMM_15_11 + 10010,3.RX,000,5.IMM_4_0:EXT-RI:16::LWSP
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11110,6.IMM_10_5,5.IMM_15_11 + 10010,3.RX,000,5.IMM_4_0:EXT-RI:16::LWSP
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"lw r, (SP)"
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"lw r, (SP)"
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*mips16:
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*mips16:
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*vr4100:
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*vr4100:
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{
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{
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GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, SP, EXTEND16 (IMMEDIATE)));
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GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, SP, EXTEND16 (IMMEDIATE)));
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}
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}
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10111,3.RX,3.RY,5.IMMED:RRI:16::LWU
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10111,3.RX,3.RY,5.IMMED:RRI:16::LWU
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"lwu r, (r)"
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"lwu r, (r)"
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*mips16:
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*mips16:
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*vr4100:
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*vr4100:
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{
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{
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GPR[TRY] = do_load (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2);
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GPR[TRY] = do_load (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2);
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}
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}
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11110,6.IMM_10_5,5.IMM_15_11 + 10111,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LWU
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11110,6.IMM_10_5,5.IMM_15_11 + 10111,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LWU
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"lwu r, (r)"
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"lwu r, (r)"
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*mips16:
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*mips16:
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*vr4100:
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*vr4100:
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{
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{
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GPR[TRY] = do_load (SD_, AccessLength_WORD, GPR[TRX], EXTEND16 (IMMEDIATE));
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GPR[TRY] = do_load (SD_, AccessLength_WORD, GPR[TRX], EXTEND16 (IMMEDIATE));
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}
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}
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00111,3.RX,3.RY,5.IMMED:RRI:16::LD
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00111,3.RX,3.RY,5.IMMED:RRI:16::LD
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"ld r, (r)"
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"ld r, (r)"
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*mips16:
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*mips16:
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*vr4100:
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*vr4100:
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{
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{
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GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, GPR[TRX], IMMED << 3);
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GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, GPR[TRX], IMMED << 3);
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}
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}
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11110,6.IMM_10_5,5.IMM_15_11 + 00111,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LD
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11110,6.IMM_10_5,5.IMM_15_11 + 00111,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LD
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"ld r, (r)"
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"ld r, (r)"
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*mips16:
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*mips16:
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*vr4100:
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*vr4100:
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{
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{
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GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, GPR[TRX], EXTEND16 (IMMEDIATE));
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GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, GPR[TRX], EXTEND16 (IMMEDIATE));
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}
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}
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11111,100,3.RY,5.IMMED:RI64:16::LDPC
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11111,100,3.RY,5.IMMED:RI64:16::LDPC
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"ld r, (PC)"
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"ld r, (PC)"
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*mips16:
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*mips16:
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*vr4100:
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*vr4100:
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{
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{
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GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD,
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GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD,
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basepc (SD_) & ~7, IMMED << 3);
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basepc (SD_) & ~7, IMMED << 3);
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}
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}
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11110,6.IMM_10_5,5.IMM_15_11 + 11111,100,3.RY,5.IMM_4_0:EXT-RI64:16::LDPC
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11110,6.IMM_10_5,5.IMM_15_11 + 11111,100,3.RY,5.IMM_4_0:EXT-RI64:16::LDPC
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"ld r, (PC)"
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"ld r, (PC)"
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*mips16:
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*mips16:
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*vr4100:
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*vr4100:
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{
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{
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GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, basepc (SD_) & ~7, EXTEND16 (IMMEDIATE));
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GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, basepc (SD_) & ~7, EXTEND16 (IMMEDIATE));
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}
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}
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11111,000,3.RY,5.IMMED:RI64:16::LDSP
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11111,000,3.RY,5.IMMED:RI64:16::LDSP
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"ld r, (SP)"
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"ld r, (SP)"
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*mips16:
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*mips16:
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*vr4100:
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*vr4100:
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{
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{
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GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3);
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GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3);
|
}
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}
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11110,6.IMM_10_5,5.IMM_15_11 + 11111,000,3.RY,5.IMM_4_0:EXT-RI64:16::LDSP
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11110,6.IMM_10_5,5.IMM_15_11 + 11111,000,3.RY,5.IMM_4_0:EXT-RI64:16::LDSP
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"ld r, (SP)"
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"ld r, (SP)"
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*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
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{
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{
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GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, SP, EXTEND16 (IMMEDIATE));
|
GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, SP, EXTEND16 (IMMEDIATE));
|
}
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}
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11000,3.RX,3.RY,5.IMMED:RRI:16::SB
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11000,3.RX,3.RY,5.IMMED:RRI:16::SB
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"sb r, (r)"
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"sb r, (r)"
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*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
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{
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do_store (SD_, AccessLength_BYTE, GPR[TRX], IMMED, GPR[TRY]);
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do_store (SD_, AccessLength_BYTE, GPR[TRX], IMMED, GPR[TRY]);
|
}
|
}
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11110,6.IMM_10_5,5.IMM_15_11 + 11000,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SB
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11110,6.IMM_10_5,5.IMM_15_11 + 11000,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SB
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"sb r, (r)"
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"sb r, (r)"
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*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
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do_store (SD_, AccessLength_BYTE, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]);
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do_store (SD_, AccessLength_BYTE, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]);
|
}
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}
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11001,3.RX,3.RY,5.IMMED:RRI:16::SH
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11001,3.RX,3.RY,5.IMMED:RRI:16::SH
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"sh r, (r)"
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"sh r, (r)"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_store (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1, GPR[TRY]);
|
do_store (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1, GPR[TRY]);
|
}
|
}
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11110,6.IMM_10_5,5.IMM_15_11 + 11001,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SH
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11110,6.IMM_10_5,5.IMM_15_11 + 11001,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SH
|
"sh r, (r)"
|
"sh r, (r)"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_store (SD_, AccessLength_HALFWORD, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]);
|
do_store (SD_, AccessLength_HALFWORD, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]);
|
}
|
}
|
|
|
|
|
|
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11011,3.RX,3.RY,5.IMMED:RRI:16::SW
|
11011,3.RX,3.RY,5.IMMED:RRI:16::SW
|
"sw r, (r)"
|
"sw r, (r)"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_store (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2, GPR[TRY]);
|
do_store (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2, GPR[TRY]);
|
}
|
}
|
|
|
11110,6.IMM_10_5,5.IMM_15_11 + 11011,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SW
|
11110,6.IMM_10_5,5.IMM_15_11 + 11011,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SW
|
"sw r, (r)"
|
"sw r, (r)"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_store (SD_, AccessLength_WORD, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]);
|
do_store (SD_, AccessLength_WORD, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]);
|
}
|
}
|
|
|
|
|
|
|
11010,3.RX,8.IMMED:RI:16::SWSP
|
11010,3.RX,8.IMMED:RI:16::SWSP
|
"sw r, (SP)"
|
"sw r, (SP)"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_store (SD_, AccessLength_WORD, SP, IMMED << 2, GPR[TRX]);
|
do_store (SD_, AccessLength_WORD, SP, IMMED << 2, GPR[TRX]);
|
}
|
}
|
|
|
11110,6.IMM_10_5,5.IMM_15_11 + 11010,3.RX,000,5.IMM_4_0:EXT-RI:16::SWSP
|
11110,6.IMM_10_5,5.IMM_15_11 + 11010,3.RX,000,5.IMM_4_0:EXT-RI:16::SWSP
|
"sw r, (SP)"
|
"sw r, (SP)"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_store (SD_, AccessLength_WORD, SP, EXTEND16 (IMMEDIATE), GPR[TRX]);
|
do_store (SD_, AccessLength_WORD, SP, EXTEND16 (IMMEDIATE), GPR[TRX]);
|
}
|
}
|
|
|
|
|
|
|
01100,010,8.IMMED:I8:16::SWRASP
|
01100,010,8.IMMED:I8:16::SWRASP
|
"sw r, (SP)"
|
"sw r, (SP)"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_store (SD_, AccessLength_WORD, SP, IMMED << 2, RA);
|
do_store (SD_, AccessLength_WORD, SP, IMMED << 2, RA);
|
}
|
}
|
|
|
11110,6.IMM_10_5,5.IMM_15_11 + 01100,010,000,5.IMM_4_0:EXT-I8:16::SWRASP
|
11110,6.IMM_10_5,5.IMM_15_11 + 01100,010,000,5.IMM_4_0:EXT-I8:16::SWRASP
|
"sw r, (SP)"
|
"sw r, (SP)"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_store (SD_, AccessLength_WORD, SP, EXTEND16 (IMMEDIATE), RA);
|
do_store (SD_, AccessLength_WORD, SP, EXTEND16 (IMMEDIATE), RA);
|
}
|
}
|
|
|
|
|
|
|
01111,3.RX,3.RY,5.IMMED:RRI:16::SD
|
01111,3.RX,3.RY,5.IMMED:RRI:16::SD
|
"sd r, (r)"
|
"sd r, (r)"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_store (SD_, AccessLength_DOUBLEWORD, GPR[TRX], IMMED << 3, GPR[TRY]);
|
do_store (SD_, AccessLength_DOUBLEWORD, GPR[TRX], IMMED << 3, GPR[TRY]);
|
}
|
}
|
|
|
11110,6.IMM_10_5,5.IMM_15_11 + 01111,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SD
|
11110,6.IMM_10_5,5.IMM_15_11 + 01111,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SD
|
"sd r, (r)"
|
"sd r, (r)"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_store (SD_, AccessLength_DOUBLEWORD, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]);
|
do_store (SD_, AccessLength_DOUBLEWORD, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]);
|
}
|
}
|
|
|
|
|
|
|
11111,001,3.RY,5.IMMED:RI64:16::SDSP
|
11111,001,3.RY,5.IMMED:RI64:16::SDSP
|
"sd r, (SP)"
|
"sd r, (SP)"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_store (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3, GPR[TRY]);
|
do_store (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3, GPR[TRY]);
|
}
|
}
|
|
|
11110,6.IMM_10_5,5.IMM_15_11 + 11111,001,3.RY,5.IMM_4_0:EXT-RI64:16::SDSP
|
11110,6.IMM_10_5,5.IMM_15_11 + 11111,001,3.RY,5.IMM_4_0:EXT-RI64:16::SDSP
|
"sd r, (SP)"
|
"sd r, (SP)"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_store (SD_, AccessLength_DOUBLEWORD, SP, EXTEND16 (IMMEDIATE), GPR[TRY]);
|
do_store (SD_, AccessLength_DOUBLEWORD, SP, EXTEND16 (IMMEDIATE), GPR[TRY]);
|
}
|
}
|
|
|
|
|
|
|
11111,010,8.IMMED:I64:16::SDRASP
|
11111,010,8.IMMED:I64:16::SDRASP
|
"sd r, (SP)"
|
"sd r, (SP)"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_store (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3, RA);
|
do_store (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3, RA);
|
}
|
}
|
|
|
11110,6.IMM_10_5,5.IMM_15_11 + 11111,010,000,5.IMM_4_0:EXT-I64:16::SDRASP
|
11110,6.IMM_10_5,5.IMM_15_11 + 11111,010,000,5.IMM_4_0:EXT-I64:16::SDRASP
|
"sd r, (SP)"
|
"sd r, (SP)"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_store (SD_, AccessLength_DOUBLEWORD, SP, EXTEND16 (IMMEDIATE), RA);
|
do_store (SD_, AccessLength_DOUBLEWORD, SP, EXTEND16 (IMMEDIATE), RA);
|
}
|
}
|
|
|
|
|
|
|
// ALU Immediate Instructions
|
// ALU Immediate Instructions
|
|
|
|
|
01101,3.RX,8.IMMED:RI:16::LI
|
01101,3.RX,8.IMMED:RI:16::LI
|
"li r, "
|
"li r, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_ori (SD_, 0, TRX, IMMED);
|
do_ori (SD_, 0, TRX, IMMED);
|
}
|
}
|
|
|
11110,6.IMM_10_5,5.IMM_15_11 + 01101,3.RX,000,5.IMM_4_0:EXT-RI:16::LI
|
11110,6.IMM_10_5,5.IMM_15_11 + 01101,3.RX,000,5.IMM_4_0:EXT-RI:16::LI
|
"li r, "
|
"li r, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_ori (SD_, 0, TRX, IMMEDIATE);
|
do_ori (SD_, 0, TRX, IMMEDIATE);
|
}
|
}
|
|
|
|
|
|
|
01000,3.RX,3.RY,0,4.IMMED:RRI-A:16::ADDIU
|
01000,3.RX,3.RY,0,4.IMMED:RRI-A:16::ADDIU
|
"addiu r, r, "
|
"addiu r, r, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_addiu (SD_, TRX, TRY, EXTEND4 (IMMED));
|
do_addiu (SD_, TRX, TRY, EXTEND4 (IMMED));
|
}
|
}
|
|
|
11110,7.IMM_10_4,4.IMM_14_11 + 01000,3.RX,3.RY,0,4.IMM_3_0:EXT-RRI-A:16::ADDIU
|
11110,7.IMM_10_4,4.IMM_14_11 + 01000,3.RX,3.RY,0,4.IMM_3_0:EXT-RRI-A:16::ADDIU
|
"addiu r, r, "
|
"addiu r, r, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_addiu (SD_, TRX, TRY, EXTEND15 (IMMEDIATE));
|
do_addiu (SD_, TRX, TRY, EXTEND15 (IMMEDIATE));
|
}
|
}
|
|
|
|
|
|
|
01001,3.RX,8.IMMED:RI:16::ADDIU8
|
01001,3.RX,8.IMMED:RI:16::ADDIU8
|
"addiu r, "
|
"addiu r, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_addiu (SD_, TRX, TRX, EXTEND8 (IMMED));
|
do_addiu (SD_, TRX, TRX, EXTEND8 (IMMED));
|
}
|
}
|
|
|
11110,6.IMM_10_5,5.IMM_15_11 + 01001,3.RX,000,5.IMM_4_0:EXT-RI:16::ADDIU8
|
11110,6.IMM_10_5,5.IMM_15_11 + 01001,3.RX,000,5.IMM_4_0:EXT-RI:16::ADDIU8
|
"addiu r, "
|
"addiu r, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_addiu (SD_, TRX, TRX, EXTEND16 (IMMEDIATE));
|
do_addiu (SD_, TRX, TRX, EXTEND16 (IMMEDIATE));
|
}
|
}
|
|
|
|
|
|
|
01100,011,8.IMMED:I8:16::ADJSP
|
01100,011,8.IMMED:I8:16::ADJSP
|
"addiu SP, "
|
"addiu SP, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_addiu (SD_, SPIDX, SPIDX, EXTEND8 (IMMED) << 3);
|
do_addiu (SD_, SPIDX, SPIDX, EXTEND8 (IMMED) << 3);
|
}
|
}
|
|
|
11110,6.IMM_10_5,5.IMM_15_11 + 01100,011,000,5.IMM_4_0:EXT-I8:16::ADJSP
|
11110,6.IMM_10_5,5.IMM_15_11 + 01100,011,000,5.IMM_4_0:EXT-I8:16::ADJSP
|
"addiu SP, "
|
"addiu SP, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_addiu (SD_, SPIDX, SPIDX, EXTEND16 (IMMEDIATE));
|
do_addiu (SD_, SPIDX, SPIDX, EXTEND16 (IMMEDIATE));
|
}
|
}
|
|
|
|
|
|
|
00001,3.RX,8.IMMED:RI:16::ADDIUPC
|
00001,3.RX,8.IMMED:RI:16::ADDIUPC
|
"addiu r, PC, "
|
"addiu r, PC, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
unsigned32 temp = (basepc (SD_) & ~3) + (IMMED << 2);
|
unsigned32 temp = (basepc (SD_) & ~3) + (IMMED << 2);
|
GPR[TRX] = EXTEND32 (temp);
|
GPR[TRX] = EXTEND32 (temp);
|
}
|
}
|
|
|
11110,6.IMM_10_5,5.IMM_15_11 + 00001,3.RX,000,5.IMM_4_0:EXT-RI:16::ADDIUPC
|
11110,6.IMM_10_5,5.IMM_15_11 + 00001,3.RX,000,5.IMM_4_0:EXT-RI:16::ADDIUPC
|
"addiu r, PC, "
|
"addiu r, PC, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
unsigned32 temp = (basepc (SD_) & ~3) + EXTEND16 (IMMEDIATE);
|
unsigned32 temp = (basepc (SD_) & ~3) + EXTEND16 (IMMEDIATE);
|
GPR[TRX] = EXTEND32 (temp);
|
GPR[TRX] = EXTEND32 (temp);
|
}
|
}
|
|
|
|
|
|
|
00000,3.RX,8.IMMED:RI:16::ADDIUSP
|
00000,3.RX,8.IMMED:RI:16::ADDIUSP
|
"addiu r, SP, "
|
"addiu r, SP, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_addiu (SD_, SPIDX, TRX, IMMED << 2);
|
do_addiu (SD_, SPIDX, TRX, IMMED << 2);
|
}
|
}
|
|
|
11110,6.IMM_10_5,5.IMM_15_11 + 00000,3.RX,000,5.IMM_4_0:EXT-RI:16::ADDIUSP
|
11110,6.IMM_10_5,5.IMM_15_11 + 00000,3.RX,000,5.IMM_4_0:EXT-RI:16::ADDIUSP
|
"addiu r, SP, "
|
"addiu r, SP, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_addiu (SD_, SPIDX, TRX, EXTEND16 (IMMEDIATE));
|
do_addiu (SD_, SPIDX, TRX, EXTEND16 (IMMEDIATE));
|
}
|
}
|
|
|
|
|
|
|
01000,3.RX,3.RY,1,4.IMMED:RRI-A:16::DADDIU
|
01000,3.RX,3.RY,1,4.IMMED:RRI-A:16::DADDIU
|
"daddiu r, r, "
|
"daddiu r, r, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_daddiu (SD_, TRX, TRY, EXTEND4 (IMMED));
|
do_daddiu (SD_, TRX, TRY, EXTEND4 (IMMED));
|
}
|
}
|
|
|
11110,7.IMM_10_4,4.IMM_14_11 + 01000,3.RX,3.RY,1,4.IMM_3_0:EXT-RRI-A:16::DADDIU
|
11110,7.IMM_10_4,4.IMM_14_11 + 01000,3.RX,3.RY,1,4.IMM_3_0:EXT-RRI-A:16::DADDIU
|
"daddiu r, r, "
|
"daddiu r, r, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_daddiu (SD_, TRX, TRY, EXTEND15 (IMMEDIATE));
|
do_daddiu (SD_, TRX, TRY, EXTEND15 (IMMEDIATE));
|
}
|
}
|
|
|
|
|
|
|
11111,101,3.RY,5.IMMED:RI64:16::DADDIU5
|
11111,101,3.RY,5.IMMED:RI64:16::DADDIU5
|
"daddiu r, "
|
"daddiu r, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_daddiu (SD_, TRY, TRY, EXTEND5 (IMMED));
|
do_daddiu (SD_, TRY, TRY, EXTEND5 (IMMED));
|
}
|
}
|
|
|
11110,6.IMM_10_5,5.IMM_15_11 + 11111,101,3.RY,5.IMM_4_0:EXT-RI64:16::DADDIU5
|
11110,6.IMM_10_5,5.IMM_15_11 + 11111,101,3.RY,5.IMM_4_0:EXT-RI64:16::DADDIU5
|
"daddiu r, "
|
"daddiu r, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_daddiu (SD_, TRY, TRY, EXTEND16 (IMMEDIATE));
|
do_daddiu (SD_, TRY, TRY, EXTEND16 (IMMEDIATE));
|
}
|
}
|
|
|
|
|
|
|
11111,011,8.IMMED:I64:16::DADJSP
|
11111,011,8.IMMED:I64:16::DADJSP
|
"daddiu SP, "
|
"daddiu SP, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_daddiu (SD_, SPIDX, SPIDX, EXTEND8 (IMMED) << 3);
|
do_daddiu (SD_, SPIDX, SPIDX, EXTEND8 (IMMED) << 3);
|
}
|
}
|
|
|
11110,6.IMM_10_5,5.IMM_15_11 + 11111,011,000,5.IMM_4_0:EXT-I64:16::DADJSP
|
11110,6.IMM_10_5,5.IMM_15_11 + 11111,011,000,5.IMM_4_0:EXT-I64:16::DADJSP
|
"daddiu SP, "
|
"daddiu SP, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_daddiu (SD_, SPIDX, SPIDX, EXTEND16 (IMMEDIATE));
|
do_daddiu (SD_, SPIDX, SPIDX, EXTEND16 (IMMEDIATE));
|
}
|
}
|
|
|
|
|
|
|
11111,110,3.RY,5.IMMED:RI64:16::DADDIUPC
|
11111,110,3.RY,5.IMMED:RI64:16::DADDIUPC
|
"daddiu r, PC, "
|
"daddiu r, PC, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
GPR[TRY] = (basepc (SD_) & ~3) + (IMMED << 2);
|
GPR[TRY] = (basepc (SD_) & ~3) + (IMMED << 2);
|
}
|
}
|
|
|
11110,6.IMM_10_5,5.IMM_15_11 + 11111,110,3.RY,5.IMM_4_0:EXT-RI64:16::DADDIUPC
|
11110,6.IMM_10_5,5.IMM_15_11 + 11111,110,3.RY,5.IMM_4_0:EXT-RI64:16::DADDIUPC
|
"daddiu r, PC, "
|
"daddiu r, PC, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
GPR[TRY] = (basepc (SD_) & ~3) + EXTEND16 (IMMEDIATE);
|
GPR[TRY] = (basepc (SD_) & ~3) + EXTEND16 (IMMEDIATE);
|
}
|
}
|
|
|
|
|
|
|
11111,111,3.RY,5.IMMED:RI64:16::DADDIUSP
|
11111,111,3.RY,5.IMMED:RI64:16::DADDIUSP
|
"daddiu r, SP, "
|
"daddiu r, SP, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_daddiu (SD_, SPIDX, TRY, IMMED << 2);
|
do_daddiu (SD_, SPIDX, TRY, IMMED << 2);
|
}
|
}
|
|
|
11110,6.IMM_10_5,5.IMM_15_11 + 11111,111,3.RY,5.IMM_4_0:EXT-RI64:16::DADDIUSP
|
11110,6.IMM_10_5,5.IMM_15_11 + 11111,111,3.RY,5.IMM_4_0:EXT-RI64:16::DADDIUSP
|
"daddiu r, SP, "
|
"daddiu r, SP, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_daddiu (SD_, SPIDX, TRY, EXTEND16 (IMMEDIATE));
|
do_daddiu (SD_, SPIDX, TRY, EXTEND16 (IMMEDIATE));
|
}
|
}
|
|
|
|
|
|
|
01010,3.RX,8.IMMED:RI:16::SLTI
|
01010,3.RX,8.IMMED:RI:16::SLTI
|
"slti r, "
|
"slti r, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_slti (SD_, TRX, T8IDX, IMMED);
|
do_slti (SD_, TRX, T8IDX, IMMED);
|
}
|
}
|
|
|
11110,6.IMM_10_5,5.IMM_15_11 + 01010,3.RX,000,5.IMM_4_0:EXT-RI:16::SLTI
|
11110,6.IMM_10_5,5.IMM_15_11 + 01010,3.RX,000,5.IMM_4_0:EXT-RI:16::SLTI
|
"slti r, "
|
"slti r, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_slti (SD_, TRX, T8IDX, IMMEDIATE);
|
do_slti (SD_, TRX, T8IDX, IMMEDIATE);
|
}
|
}
|
|
|
|
|
|
|
01011,3.RX,8.IMMED:RI:16::SLTIU
|
01011,3.RX,8.IMMED:RI:16::SLTIU
|
"sltiu r, "
|
"sltiu r, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_sltiu (SD_, TRX, T8IDX, IMMED);
|
do_sltiu (SD_, TRX, T8IDX, IMMED);
|
}
|
}
|
|
|
11110,6.IMM_10_5,5.IMM_15_11 + 01011,3.RX,000,5.IMM_4_0:EXT-RI:16::SLTIU
|
11110,6.IMM_10_5,5.IMM_15_11 + 01011,3.RX,000,5.IMM_4_0:EXT-RI:16::SLTIU
|
"sltiu r, "
|
"sltiu r, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_sltiu (SD_, TRX, T8IDX, IMMEDIATE);
|
do_sltiu (SD_, TRX, T8IDX, IMMEDIATE);
|
}
|
}
|
|
|
|
|
|
|
11101,3.RX,3.RY,01010:RR:16::CMP
|
11101,3.RX,3.RY,01010:RR:16::CMP
|
"sltiu r, r"
|
"sltiu r, r"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_xor (SD_, TRX, TRY, T8IDX);
|
do_xor (SD_, TRX, TRY, T8IDX);
|
}
|
}
|
|
|
|
|
01110,3.RX,8.IMMED:RI:16::CMPI
|
01110,3.RX,8.IMMED:RI:16::CMPI
|
"sltiu r, "
|
"sltiu r, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_xori (SD_, TRX, T8IDX, IMMED);
|
do_xori (SD_, TRX, T8IDX, IMMED);
|
}
|
}
|
|
|
11110,6.IMM_10_5,5.IMM_15_11 + 01110,3.RX,000,5.IMM_4_0:EXT-RI:16::CMPI
|
11110,6.IMM_10_5,5.IMM_15_11 + 01110,3.RX,000,5.IMM_4_0:EXT-RI:16::CMPI
|
"sltiu r, "
|
"sltiu r, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_xori (SD_, TRX, T8IDX, IMMEDIATE);
|
do_xori (SD_, TRX, T8IDX, IMMEDIATE);
|
}
|
}
|
|
|
|
|
|
|
// Two/Three Operand, Register-Type
|
// Two/Three Operand, Register-Type
|
|
|
|
|
|
|
11100,3.RX,3.RY,3.RZ,01:RRR:16::ADDU
|
11100,3.RX,3.RY,3.RZ,01:RRR:16::ADDU
|
"addu r, r, r"
|
"addu r, r, r"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_addu (SD_, TRX, TRY, TRZ);
|
do_addu (SD_, TRX, TRY, TRZ);
|
}
|
}
|
|
|
|
|
|
|
11100,3.RX,3.RY,3.RZ,11:RRR:16::SUBU
|
11100,3.RX,3.RY,3.RZ,11:RRR:16::SUBU
|
"subu r, r, r"
|
"subu r, r, r"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_subu (SD_, TRX, TRY, TRZ);
|
do_subu (SD_, TRX, TRY, TRZ);
|
}
|
}
|
|
|
11100,3.RX,3.RY,3.RZ,00:RRR:16::DADDU
|
11100,3.RX,3.RY,3.RZ,00:RRR:16::DADDU
|
"daddu r, r, r"
|
"daddu r, r, r"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_daddu (SD_, TRX, TRY, TRZ);
|
do_daddu (SD_, TRX, TRY, TRZ);
|
}
|
}
|
|
|
|
|
|
|
11100,3.RX,3.RY,3.RZ,10:RRR:16::DSUBU
|
11100,3.RX,3.RY,3.RZ,10:RRR:16::DSUBU
|
"dsubu r, r, r"
|
"dsubu r, r, r"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_dsubu (SD_, TRX, TRY, TRZ);
|
do_dsubu (SD_, TRX, TRY, TRZ);
|
}
|
}
|
|
|
|
|
|
|
11101,3.RX,3.RY,00010:RR:16::SLT
|
11101,3.RX,3.RY,00010:RR:16::SLT
|
"slt r, r"
|
"slt r, r"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_slt (SD_, TRX, TRY, T8IDX);
|
do_slt (SD_, TRX, TRY, T8IDX);
|
}
|
}
|
|
|
|
|
|
|
11101,3.RX,3.RY,00011:RR:16::SLTU
|
11101,3.RX,3.RY,00011:RR:16::SLTU
|
"sltu r, r"
|
"sltu r, r"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_sltu (SD_, TRX, TRY, T8IDX);
|
do_sltu (SD_, TRX, TRY, T8IDX);
|
}
|
}
|
|
|
|
|
|
|
11101,3.RX,3.RY,01011:RR:16::NEG
|
11101,3.RX,3.RY,01011:RR:16::NEG
|
"neg r, r"
|
"neg r, r"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_subu (SD_, 0, TRY, TRX);
|
do_subu (SD_, 0, TRY, TRX);
|
}
|
}
|
|
|
|
|
|
|
11101,3.RX,3.RY,01100:RR:16::AND
|
11101,3.RX,3.RY,01100:RR:16::AND
|
"and r, r"
|
"and r, r"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_and (SD_, TRX, TRY, TRX);
|
do_and (SD_, TRX, TRY, TRX);
|
}
|
}
|
|
|
|
|
|
|
11101,3.RX,3.RY,01101:RR:16::OR
|
11101,3.RX,3.RY,01101:RR:16::OR
|
"or r, r"
|
"or r, r"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_or (SD_, TRX, TRY, TRX);
|
do_or (SD_, TRX, TRY, TRX);
|
}
|
}
|
|
|
|
|
|
|
11101,3.RX,3.RY,01110:RR:16::XOR
|
11101,3.RX,3.RY,01110:RR:16::XOR
|
"xor r, r"
|
"xor r, r"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_xor (SD_, TRX, TRY, TRX);
|
do_xor (SD_, TRX, TRY, TRX);
|
}
|
}
|
|
|
|
|
|
|
11101,3.RX,3.RY,01111:RR:16::NOT
|
11101,3.RX,3.RY,01111:RR:16::NOT
|
"not r, r"
|
"not r, r"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_nor (SD_, 0, TRY, TRX);
|
do_nor (SD_, 0, TRY, TRX);
|
}
|
}
|
|
|
|
|
|
|
01100,111,3.RY,5.R32:I8_MOVR32:16::MOVR32
|
01100,111,3.RY,5.R32:I8_MOVR32:16::MOVR32
|
"move r, r"
|
"move r, r"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_or (SD_, R32, 0, TRY);
|
do_or (SD_, R32, 0, TRY);
|
}
|
}
|
|
|
|
|
|
|
01100,101,3.R32L,2.R32H,3.RZ:I8_MOV32R:16::MOV32R
|
01100,101,3.R32L,2.R32H,3.RZ:I8_MOV32R:16::MOV32R
|
"move r, r"
|
"move r, r"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_or (SD_, TRZ, 0, R32);
|
do_or (SD_, TRZ, 0, R32);
|
}
|
}
|
|
|
|
|
|
|
00110,3.RX,3.RY,3.SHAMT,00:SHIFT:16::SLL
|
00110,3.RX,3.RY,3.SHAMT,00:SHIFT:16::SLL
|
"sll r, r, "
|
"sll r, r, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_sll (SD_, TRY, TRX, SHIFT);
|
do_sll (SD_, TRY, TRX, SHIFT);
|
}
|
}
|
|
|
11110,5.SHAMT,0,00000 + 00110,3.RX,3.RY,000,00:EXT-SHIFT:16::SLL
|
11110,5.SHAMT,0,00000 + 00110,3.RX,3.RY,000,00:EXT-SHIFT:16::SLL
|
"sll r, r, "
|
"sll r, r, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_sll (SD_, TRY, TRX, SHAMT);
|
do_sll (SD_, TRY, TRX, SHAMT);
|
}
|
}
|
|
|
|
|
|
|
00110,3.RX,3.RY,3.SHAMT,10:SHIFT:16::SRL
|
00110,3.RX,3.RY,3.SHAMT,10:SHIFT:16::SRL
|
"srl r, r, "
|
"srl r, r, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_srl (SD_, TRY, TRX, SHIFT);
|
do_srl (SD_, TRY, TRX, SHIFT);
|
}
|
}
|
|
|
11110,5.SHAMT,0,00000 + 00110,3.RX,3.RY,000,10:EXT-SHIFT:16::SRL
|
11110,5.SHAMT,0,00000 + 00110,3.RX,3.RY,000,10:EXT-SHIFT:16::SRL
|
"srl r, r, "
|
"srl r, r, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_srl (SD_, TRY, TRX, SHAMT);
|
do_srl (SD_, TRY, TRX, SHAMT);
|
}
|
}
|
|
|
|
|
|
|
00110,3.RX,3.RY,3.SHAMT,11:SHIFT:16::SRA
|
00110,3.RX,3.RY,3.SHAMT,11:SHIFT:16::SRA
|
"sra r, r, "
|
"sra r, r, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_sra (SD_, TRY, TRX, SHIFT);
|
do_sra (SD_, TRY, TRX, SHIFT);
|
}
|
}
|
|
|
11110,5.SHAMT,0,00000 + 00110,3.RX,3.RY,000,11:EXT-SHIFT:16::SRA
|
11110,5.SHAMT,0,00000 + 00110,3.RX,3.RY,000,11:EXT-SHIFT:16::SRA
|
"sra r, r, "
|
"sra r, r, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_sra (SD_, TRY, TRX, SHAMT);
|
do_sra (SD_, TRY, TRX, SHAMT);
|
}
|
}
|
|
|
|
|
|
|
11101,3.RX,3.RY,00100:RR:16::SLLV
|
11101,3.RX,3.RY,00100:RR:16::SLLV
|
"sllv r, r"
|
"sllv r, r"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_sllv (SD_, TRX, TRY, TRY);
|
do_sllv (SD_, TRX, TRY, TRY);
|
}
|
}
|
|
|
|
|
11101,3.RX,3.RY,00110:RR:16::SRLV
|
11101,3.RX,3.RY,00110:RR:16::SRLV
|
"srlv r, r"
|
"srlv r, r"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_srlv (SD_, TRX, TRY, TRY);
|
do_srlv (SD_, TRX, TRY, TRY);
|
}
|
}
|
|
|
|
|
11101,3.RX,3.RY,00111:RR:16::SRAV
|
11101,3.RX,3.RY,00111:RR:16::SRAV
|
"srav r, r"
|
"srav r, r"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_srav (SD_, TRX, TRY, TRY);
|
do_srav (SD_, TRX, TRY, TRY);
|
}
|
}
|
|
|
|
|
00110,3.RX,3.RY,3.SHAMT,01:SHIFT:16::DSLL
|
00110,3.RX,3.RY,3.SHAMT,01:SHIFT:16::DSLL
|
"dsll r, r, "
|
"dsll r, r, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_dsll (SD_, TRY, TRX, SHIFT);
|
do_dsll (SD_, TRY, TRX, SHIFT);
|
}
|
}
|
|
|
11110,5.SHAMT_4_0,1.S5,00000 + 00110,3.RX,3.RY,000,01:EXT-SHIFT:16::DSLL
|
11110,5.SHAMT_4_0,1.S5,00000 + 00110,3.RX,3.RY,000,01:EXT-SHIFT:16::DSLL
|
"dsll r, r, "
|
"dsll r, r, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_dsll (SD_, TRY, TRX, SHAMT);
|
do_dsll (SD_, TRY, TRX, SHAMT);
|
}
|
}
|
|
|
|
|
|
|
11101,3.SHAMT,3.RY,01000:SHIFT64:16::DSRL
|
11101,3.SHAMT,3.RY,01000:SHIFT64:16::DSRL
|
"dsrl r, "
|
"dsrl r, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_dsrl (SD_, TRY, TRY, SHIFT);
|
do_dsrl (SD_, TRY, TRY, SHIFT);
|
}
|
}
|
|
|
11110,5.SHAMT_4_0,1.S5,00000 + 11101,000,3.RY,01000:EXT-SHIFT64:16::DSRL
|
11110,5.SHAMT_4_0,1.S5,00000 + 11101,000,3.RY,01000:EXT-SHIFT64:16::DSRL
|
"dsrl r, "
|
"dsrl r, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_dsrl (SD_, TRY, TRY, SHAMT);
|
do_dsrl (SD_, TRY, TRY, SHAMT);
|
}
|
}
|
|
|
|
|
|
|
11101,3.SHAMT,3.RY,10011:SHIFT64:16::DSRA
|
11101,3.SHAMT,3.RY,10011:SHIFT64:16::DSRA
|
"dsra r, "
|
"dsra r, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_dsra (SD_, TRY, TRY, SHIFT);
|
do_dsra (SD_, TRY, TRY, SHIFT);
|
}
|
}
|
|
|
11110,5.SHAMT_4_0,1.S5,00000 + 11101,000,3.RY,10011:EXT-SHIFT64:16::DSRA
|
11110,5.SHAMT_4_0,1.S5,00000 + 11101,000,3.RY,10011:EXT-SHIFT64:16::DSRA
|
"dsra r, "
|
"dsra r, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_dsra (SD_, TRY, TRY, SHAMT);
|
do_dsra (SD_, TRY, TRY, SHAMT);
|
}
|
}
|
|
|
|
|
|
|
11101,3.RX,3.RY,10100:RR:16::DSLLV
|
11101,3.RX,3.RY,10100:RR:16::DSLLV
|
"dsllv r, r"
|
"dsllv r, r"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_dsllv (SD_, TRX, TRY, TRY);
|
do_dsllv (SD_, TRX, TRY, TRY);
|
}
|
}
|
|
|
|
|
11101,3.RX,3.RY,10110:RR:16::DSRLV
|
11101,3.RX,3.RY,10110:RR:16::DSRLV
|
"dsrlv r, r"
|
"dsrlv r, r"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_dsrlv (SD_, TRX, TRY, TRY);
|
do_dsrlv (SD_, TRX, TRY, TRY);
|
}
|
}
|
|
|
|
|
11101,3.RX,3.RY,10111:RR:16::DSRAV
|
11101,3.RX,3.RY,10111:RR:16::DSRAV
|
"dsrav r, r"
|
"dsrav r, r"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_dsrav (SD_, TRX, TRY, TRY);
|
do_dsrav (SD_, TRX, TRY, TRY);
|
}
|
}
|
|
|
|
|
// Multiply /Divide Instructions
|
// Multiply /Divide Instructions
|
|
|
|
|
11101,3.RX,3.RY,11000:RR:16::MULT
|
11101,3.RX,3.RY,11000:RR:16::MULT
|
"mult r, r"
|
"mult r, r"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_mult (SD_, TRX, TRY, 0);
|
do_mult (SD_, TRX, TRY, 0);
|
}
|
}
|
|
|
|
|
11101,3.RX,3.RY,11001:RR:16::MULTU
|
11101,3.RX,3.RY,11001:RR:16::MULTU
|
"multu r, r"
|
"multu r, r"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_multu (SD_, TRX, TRY, 0);
|
do_multu (SD_, TRX, TRY, 0);
|
}
|
}
|
|
|
|
|
11101,3.RX,3.RY,11010:RR:16::DIV
|
11101,3.RX,3.RY,11010:RR:16::DIV
|
"div r, r"
|
"div r, r"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_div (SD_, TRX, TRY);
|
do_div (SD_, TRX, TRY);
|
}
|
}
|
|
|
|
|
11101,3.RX,3.RY,11011:RR:16::DIVU
|
11101,3.RX,3.RY,11011:RR:16::DIVU
|
"divu r, r"
|
"divu r, r"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_divu (SD_, TRX, TRY);
|
do_divu (SD_, TRX, TRY);
|
}
|
}
|
|
|
|
|
11101,3.RX,000,10000:RR:16::MFHI
|
11101,3.RX,000,10000:RR:16::MFHI
|
"mfhi r"
|
"mfhi r"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_mfhi (SD_, TRX);
|
do_mfhi (SD_, TRX);
|
}
|
}
|
|
|
|
|
11101,3.RX,000,10010:RR:16::MFLO
|
11101,3.RX,000,10010:RR:16::MFLO
|
"mflo r"
|
"mflo r"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_mflo (SD_, TRX);
|
do_mflo (SD_, TRX);
|
}
|
}
|
|
|
|
|
11101,3.RX,3.RY,11100:RR:16::DMULT
|
11101,3.RX,3.RY,11100:RR:16::DMULT
|
"dmult r, r"
|
"dmult r, r"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_dmult (SD_, TRX, TRY, 0);
|
do_dmult (SD_, TRX, TRY, 0);
|
}
|
}
|
|
|
|
|
11101,3.RX,3.RY,11101:RR:16::DMULTU
|
11101,3.RX,3.RY,11101:RR:16::DMULTU
|
"dmultu r, r"
|
"dmultu r, r"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_dmultu (SD_, TRX, TRY, 0);
|
do_dmultu (SD_, TRX, TRY, 0);
|
}
|
}
|
|
|
|
|
11101,3.RX,3.RY,11110:RR:16::DDIV
|
11101,3.RX,3.RY,11110:RR:16::DDIV
|
"ddiv r, r"
|
"ddiv r, r"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_ddiv (SD_, TRX, TRY);
|
do_ddiv (SD_, TRX, TRY);
|
}
|
}
|
|
|
|
|
11101,3.RX,3.RY,11111:RR:16::DDIVU
|
11101,3.RX,3.RY,11111:RR:16::DDIVU
|
"ddivu r, r"
|
"ddivu r, r"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_ddivu (SD_, TRX, TRY);
|
do_ddivu (SD_, TRX, TRY);
|
}
|
}
|
|
|
|
|
// Jump and Branch Instructions
|
// Jump and Branch Instructions
|
|
|
|
|
|
|
// Issue instruction in delay slot of branch
|
// Issue instruction in delay slot of branch
|
:function:::address_word:delayslot16:address_word nia, address_word target
|
:function:::address_word:delayslot16:address_word nia, address_word target
|
{
|
{
|
instruction_word delay_insn;
|
instruction_word delay_insn;
|
sim_events_slip (SD, 1);
|
sim_events_slip (SD, 1);
|
DSPC = CIA; /* save current PC somewhere */
|
DSPC = CIA; /* save current PC somewhere */
|
STATE |= simDELAYSLOT;
|
STATE |= simDELAYSLOT;
|
delay_insn = IMEM16 (nia); /* NOTE: mips16 */
|
delay_insn = IMEM16 (nia); /* NOTE: mips16 */
|
idecode_issue (CPU_, delay_insn, (nia));
|
idecode_issue (CPU_, delay_insn, (nia));
|
STATE &= ~simDELAYSLOT;
|
STATE &= ~simDELAYSLOT;
|
return target;
|
return target;
|
}
|
}
|
|
|
// compute basepc dependant on us being in a delay slot
|
// compute basepc dependant on us being in a delay slot
|
:function:::address_word:basepc:
|
:function:::address_word:basepc:
|
{
|
{
|
if (STATE & simDELAYSLOT)
|
if (STATE & simDELAYSLOT)
|
{
|
{
|
return DSPC; /* return saved address of preceeding jmp */
|
return DSPC; /* return saved address of preceeding jmp */
|
}
|
}
|
else
|
else
|
{
|
{
|
return CIA;
|
return CIA;
|
}
|
}
|
}
|
}
|
|
|
|
|
// JAL
|
// JAL
|
00011,0,5.IMM_20_16,5.IMM_25_21 + 16.IMMED_15_0:JAL:16::JAL
|
00011,0,5.IMM_20_16,5.IMM_25_21 + 16.IMMED_15_0:JAL:16::JAL
|
"jal "
|
"jal "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
address_word region = (NIA & MASK (63, 28));
|
address_word region = (NIA & MASK (63, 28));
|
RA = NIA + 2; /* skip 16 bit delayslot insn */
|
RA = NIA + 2; /* skip 16 bit delayslot insn */
|
NIA = delayslot16 (SD_, NIA, (region | (IMMEDIATE << 2))) | 1;
|
NIA = delayslot16 (SD_, NIA, (region | (IMMEDIATE << 2))) | 1;
|
}
|
}
|
|
|
|
|
|
|
// JALX - 32 and 16 bit versions.
|
// JALX - 32 and 16 bit versions.
|
|
|
011101,26.IMMED:JALX:32::JALX32
|
011101,26.IMMED:JALX:32::JALX32
|
"jalx "
|
"jalx "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
address_word region = (NIA & MASK (63, 28));
|
address_word region = (NIA & MASK (63, 28));
|
RA = NIA + 4; /* skip 32 bit delayslot insn */
|
RA = NIA + 4; /* skip 32 bit delayslot insn */
|
NIA = delayslot32 (SD_, (region | (IMMED << 2)) | 1);
|
NIA = delayslot32 (SD_, (region | (IMMED << 2)) | 1);
|
}
|
}
|
|
|
00011,1,5.IMM_20_16,5.IMM_25_21 + 16.IMMED_15_0:JALX:16::JALX16
|
00011,1,5.IMM_20_16,5.IMM_25_21 + 16.IMMED_15_0:JALX:16::JALX16
|
"jalx "
|
"jalx "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
address_word region = (NIA & MASK (63, 28));
|
address_word region = (NIA & MASK (63, 28));
|
RA = NIA + 2; /* 16 bit INSN */
|
RA = NIA + 2; /* 16 bit INSN */
|
NIA = delayslot16 (SD_, NIA, (region | (IMMEDIATE << 2)) & ~1);
|
NIA = delayslot16 (SD_, NIA, (region | (IMMEDIATE << 2)) & ~1);
|
}
|
}
|
|
|
|
|
|
|
11101,3.RX,000,00000:RR:16::JR
|
11101,3.RX,000,00000:RR:16::JR
|
"jr r"
|
"jr r"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
NIA = delayslot16 (SD_, NIA, GPR[TRX]);
|
NIA = delayslot16 (SD_, NIA, GPR[TRX]);
|
}
|
}
|
|
|
|
|
11101,000,001,00000:RR:16::JRRA
|
11101,000,001,00000:RR:16::JRRA
|
"jrra"
|
"jrra"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
NIA = delayslot16 (SD_, NIA, RA);
|
NIA = delayslot16 (SD_, NIA, RA);
|
}
|
}
|
|
|
|
|
|
|
11101,3.RX,010,00000:RR:16::JALR
|
11101,3.RX,010,00000:RR:16::JALR
|
"jalr r"
|
"jalr r"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
RA = NIA + 2;
|
RA = NIA + 2;
|
NIA = delayslot16 (SD_, NIA, GPR[TRX]);
|
NIA = delayslot16 (SD_, NIA, GPR[TRX]);
|
}
|
}
|
|
|
|
|
|
|
00100,3.RX,8.IMMED:RI:16::BEQZ
|
00100,3.RX,8.IMMED:RI:16::BEQZ
|
"beqz r, "
|
"beqz r, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
if (GPR[TRX] == 0)
|
if (GPR[TRX] == 0)
|
NIA = (NIA + (EXTEND8 (IMMED) << 1));
|
NIA = (NIA + (EXTEND8 (IMMED) << 1));
|
}
|
}
|
|
|
11110,6.IMM_10_5,5.IMM_15_11 + 00100,3.RX,000,5.IMM_4_0:EXT-RI:16::BEQZ
|
11110,6.IMM_10_5,5.IMM_15_11 + 00100,3.RX,000,5.IMM_4_0:EXT-RI:16::BEQZ
|
"beqz r, "
|
"beqz r, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
if (GPR[TRX] == 0)
|
if (GPR[TRX] == 0)
|
NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1));
|
NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1));
|
}
|
}
|
|
|
|
|
|
|
00101,3.RX,8.IMMED:RI:16::BNEZ
|
00101,3.RX,8.IMMED:RI:16::BNEZ
|
"bnez r, "
|
"bnez r, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
if (GPR[TRX] != 0)
|
if (GPR[TRX] != 0)
|
NIA = (NIA + (EXTEND8 (IMMED) << 1));
|
NIA = (NIA + (EXTEND8 (IMMED) << 1));
|
}
|
}
|
|
|
11110,6.IMM_10_5,5.IMM_15_11 + 00101,3.RX,000,5.IMM_4_0:EXT-RI:16::BNEZ
|
11110,6.IMM_10_5,5.IMM_15_11 + 00101,3.RX,000,5.IMM_4_0:EXT-RI:16::BNEZ
|
"bnez r, "
|
"bnez r, "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
if (GPR[TRX] != 0)
|
if (GPR[TRX] != 0)
|
NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1));
|
NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1));
|
}
|
}
|
|
|
|
|
|
|
01100,000,8.IMMED:I8:16::BTEQZ
|
01100,000,8.IMMED:I8:16::BTEQZ
|
"bteqz "
|
"bteqz "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
if (T8 == 0)
|
if (T8 == 0)
|
NIA = (NIA + (EXTEND8 (IMMED) << 1));
|
NIA = (NIA + (EXTEND8 (IMMED) << 1));
|
}
|
}
|
|
|
11110,6.IMM_10_5,5.IMM_15_11 + 01100,000,000,5.IMM_4_0:EXT-I8:16::BTEQZ
|
11110,6.IMM_10_5,5.IMM_15_11 + 01100,000,000,5.IMM_4_0:EXT-I8:16::BTEQZ
|
"bteqz "
|
"bteqz "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
if (T8 == 0)
|
if (T8 == 0)
|
NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1));
|
NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1));
|
}
|
}
|
|
|
|
|
|
|
01100,001,8.IMMED:I8:16::BTNEZ
|
01100,001,8.IMMED:I8:16::BTNEZ
|
"btnez "
|
"btnez "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
if (T8 != 0)
|
if (T8 != 0)
|
NIA = (NIA + (EXTEND8 (IMMED) << 1));
|
NIA = (NIA + (EXTEND8 (IMMED) << 1));
|
}
|
}
|
|
|
11110,6.IMM_10_5,5.IMM_15_11 + 01100,001,000,5.IMM_4_0:EXT-I8:16::BTNEZ
|
11110,6.IMM_10_5,5.IMM_15_11 + 01100,001,000,5.IMM_4_0:EXT-I8:16::BTNEZ
|
"btnez "
|
"btnez "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
if (T8 != 0)
|
if (T8 != 0)
|
NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1));
|
NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1));
|
}
|
}
|
|
|
|
|
|
|
00010,11.IMMED:I:16::B
|
00010,11.IMMED:I:16::B
|
"b "
|
"b "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
NIA = (NIA + (EXTEND11 (IMMED) << 1));
|
NIA = (NIA + (EXTEND11 (IMMED) << 1));
|
}
|
}
|
|
|
11110,6.IMM_10_5,5.IMM_15_11 + 00010,6.0,5.IMM_4_0:EXT-I:16::B
|
11110,6.IMM_10_5,5.IMM_15_11 + 00010,6.0,5.IMM_4_0:EXT-I:16::B
|
"b "
|
"b "
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1));
|
NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1));
|
}
|
}
|
|
|
|
|
|
|
11101,3.RX,3.RY,00101:RR:16::BREAK
|
11101,3.RX,3.RY,00101:RR:16::BREAK
|
"break"
|
"break"
|
*mips16:
|
*mips16:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
if (STATE & simDELAYSLOT)
|
if (STATE & simDELAYSLOT)
|
PC = cia - 2; /* reference the branch instruction */
|
PC = cia - 2; /* reference the branch instruction */
|
else
|
else
|
PC = cia;
|
PC = cia;
|
SignalException (BreakPoint, instruction_0);
|
SignalException (BreakPoint, instruction_0);
|
}
|
}
|
|
|
