#ifndef _JP2_H_
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#ifndef _JP2_H_
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#define _JP2_H_
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#define _JP2_H_
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#define Boolean int
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#define Boolean int
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#define false 0
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#define false 0
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#define true 1
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#define true 1
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/* Selects crc trailer size in bits. Currently supported: 8 */
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/* Selects crc trailer size in bits. Currently supported: 8 */
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#define CRC_SIZE (8)
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#define CRC_SIZE (8)
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/* Scan chain size in bits. */
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/* Scan chain size in bits. */
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#define SC_SIZE (4)
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#define SC_SIZE (4)
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#ifndef ULONGEST
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#ifndef ULONGEST
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#define ULONGEST unsigned long
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#define ULONGEST unsigned long
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#endif
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#endif
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extern unsigned int serverPort;
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extern unsigned int serverPort;
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extern unsigned int server_fd;
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extern unsigned int server_fd;
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extern void HandleServerSocket(Boolean block);
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extern void HandleServerSocket(Boolean block);
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extern int err;
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extern int err;
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extern void JTAGRequest(void);
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extern void JTAGRequest(void);
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extern void GDBRequest(void);
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extern void GDBRequest(void);
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/* read a word from wishbone */
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/* read a word from wishbone */
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int dbg_wb_read32(unsigned long adr, unsigned long *data);
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int dbg_wb_read32(unsigned long adr, unsigned long *data);
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/* write a word to wishbone */
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/* write a word to wishbone */
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int dbg_wb_write32(unsigned long adr, unsigned long data);
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int dbg_wb_write32(unsigned long adr, unsigned long data);
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/* read a block from wishbone */
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/* read a block from wishbone */
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int dbg_wb_read_block32(unsigned long adr, unsigned long *data, int len);
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int dbg_wb_read_block32(unsigned long adr, unsigned long *data, int len);
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/* write a block to wishbone */
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/* write a block to wishbone */
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int dbg_wb_write_block32(unsigned long adr, unsigned long *data, int len);
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int dbg_wb_write_block32(unsigned long adr, unsigned long *data, int len);
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/* read a register from cpu */
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/* read a register from cpu */
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int dbg_cpu0_read(unsigned long adr, unsigned long *data);
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int dbg_cpu0_read(unsigned long adr, unsigned long *data);
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/* read a register from cpu module */
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/* read a register from cpu module */
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int dbg_cpu0_read_ctrl(unsigned long adr, unsigned char *data);
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int dbg_cpu0_read_ctrl(unsigned long adr, unsigned char *data);
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/* write a cpu register */
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/* write a cpu register */
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int dbg_cpu0_write(unsigned long adr, unsigned long data);
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int dbg_cpu0_write(unsigned long adr, unsigned long data);
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/* write a cpu module register */
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/* write a cpu module register */
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int dbg_cpu0_write_ctrl(unsigned long adr, unsigned char data);
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int dbg_cpu0_write_ctrl(unsigned long adr, unsigned char data);
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#define DC_SIZE 4
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#define DC_SIZE 4
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#define DC_STATUS_SIZE 4
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#define DC_STATUS_SIZE 4
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#define DC_WISHBONE 0
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#define DC_WISHBONE 0
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#define DC_CPU0 1
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#define DC_CPU0 1
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#define DC_CPU1 2
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#define DC_CPU1 2
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#define DI_GO 0
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#define DI_GO 0
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#define DI_READ_CMD 1
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#define DI_READ_CMD 1
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#define DI_WRITE_CMD 2
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#define DI_WRITE_CMD 2
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#define DI_READ_CTRL 3
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#define DI_READ_CTRL 3
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#define DI_WRITE_CTRL 4
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#define DI_WRITE_CTRL 4
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#define DBG_CRC_SIZE 32
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#define DBG_CRC_SIZE 32
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#define DBG_CRC_POLY 0x04c11db7
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#define DBG_CRC_POLY 0x04c11db7
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#define DBG_ERR_OK 0
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#define DBG_ERR_OK 0
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#define DBG_ERR_CRC 8
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#define DBG_ERR_CRC 8
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#define NUM_SOFT_RETRIES 3
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#define NUM_SOFT_RETRIES 3
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#define NUM_HARD_RETRIES 3
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#define NUM_HARD_RETRIES 3
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#define NUM_ACCESS_RETRIES 10
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#define NUM_ACCESS_RETRIES 10
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#define CHECK(x) check(__FILE__, __LINE__, (x))
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#define CHECK(x) check(__FILE__, __LINE__, (x))
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#endif /* _JP2_H_ */
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#endif /* _JP2_H_ */
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