#ifndef __ASM_SH_IRQ_SH7300_H
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#ifndef __ASM_SH_IRQ_SH7300_H
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#define __ASM_SH_IRQ_SH7300_H
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#define __ASM_SH_IRQ_SH7300_H
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/*
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/*
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* linux/include/asm-sh/irq-sh7300.h
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* linux/include/asm-sh/irq-sh7300.h
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*
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*
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* Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
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* Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
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*/
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*/
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#include <linux/config.h>
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#include <linux/config.h>
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#include <asm/machvec.h>
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#include <asm/machvec.h>
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#include <asm/ptrace.h> /* for pt_regs */
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#include <asm/ptrace.h> /* for pt_regs */
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#define INTC_IPRA 0xA414FEE2UL
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#define INTC_IPRA 0xA414FEE2UL
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#define INTC_IPRB 0xA414FEE4UL
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#define INTC_IPRB 0xA414FEE4UL
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#define INTC_IPRC 0xA4140016UL
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#define INTC_IPRC 0xA4140016UL
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#define INTC_IPRD 0xA4140018UL
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#define INTC_IPRD 0xA4140018UL
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#define INTC_IPRE 0xA414001AUL
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#define INTC_IPRE 0xA414001AUL
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#define INTC_IPRF 0xA4080000UL
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#define INTC_IPRF 0xA4080000UL
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#define INTC_IPRG 0xA4080002UL
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#define INTC_IPRG 0xA4080002UL
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#define INTC_IPRH 0xA4080004UL
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#define INTC_IPRH 0xA4080004UL
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#define INTC_IPRI 0xA4080006UL
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#define INTC_IPRI 0xA4080006UL
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#define INTC_IPRJ 0xA4080008UL
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#define INTC_IPRJ 0xA4080008UL
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#define INTC_IMR0 0xA4080040UL
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#define INTC_IMR0 0xA4080040UL
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#define INTC_IMR1 0xA4080042UL
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#define INTC_IMR1 0xA4080042UL
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#define INTC_IMR2 0xA4080044UL
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#define INTC_IMR2 0xA4080044UL
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#define INTC_IMR3 0xA4080046UL
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#define INTC_IMR3 0xA4080046UL
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#define INTC_IMR4 0xA4080048UL
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#define INTC_IMR4 0xA4080048UL
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#define INTC_IMR5 0xA408004AUL
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#define INTC_IMR5 0xA408004AUL
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#define INTC_IMR6 0xA408004CUL
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#define INTC_IMR6 0xA408004CUL
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#define INTC_IMR7 0xA408004EUL
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#define INTC_IMR7 0xA408004EUL
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#define INTC_IMR8 0xA4080050UL
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#define INTC_IMR8 0xA4080050UL
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#define INTC_IMR9 0xA4080052UL
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#define INTC_IMR9 0xA4080052UL
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#define INTC_IMR10 0xA4080054UL
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#define INTC_IMR10 0xA4080054UL
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#define INTC_IMCR0 0xA4080060UL
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#define INTC_IMCR0 0xA4080060UL
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#define INTC_IMCR1 0xA4080062UL
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#define INTC_IMCR1 0xA4080062UL
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#define INTC_IMCR2 0xA4080064UL
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#define INTC_IMCR2 0xA4080064UL
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#define INTC_IMCR3 0xA4080066UL
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#define INTC_IMCR3 0xA4080066UL
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#define INTC_IMCR4 0xA4080068UL
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#define INTC_IMCR4 0xA4080068UL
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#define INTC_IMCR5 0xA408006AUL
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#define INTC_IMCR5 0xA408006AUL
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#define INTC_IMCR6 0xA408006CUL
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#define INTC_IMCR6 0xA408006CUL
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#define INTC_IMCR7 0xA408006EUL
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#define INTC_IMCR7 0xA408006EUL
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#define INTC_IMCR8 0xA4080070UL
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#define INTC_IMCR8 0xA4080070UL
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#define INTC_IMCR9 0xA4080072UL
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#define INTC_IMCR9 0xA4080072UL
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#define INTC_IMCR10 0xA4080074UL
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#define INTC_IMCR10 0xA4080074UL
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#define INTC_ICR0 0xA414FEE0UL
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#define INTC_ICR0 0xA414FEE0UL
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#define INTC_ICR1 0xA4140010UL
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#define INTC_ICR1 0xA4140010UL
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#define INTC_IRR0 0xA4140004UL
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#define INTC_IRR0 0xA4140004UL
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/* TMU0 */
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/* TMU0 */
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#define TMU0_IRQ 16
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#define TMU0_IRQ 16
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#define TMU0_IPR_ADDR INTC_IPRA
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#define TMU0_IPR_ADDR INTC_IPRA
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#define TMU0_IPR_POS 3
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#define TMU0_IPR_POS 3
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#define TMU0_PRIORITY 2
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#define TMU0_PRIORITY 2
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#define TIMER_IRQ 16
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#define TIMER_IRQ 16
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#define TIMER_IPR_ADDR INTC_IPRA
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#define TIMER_IPR_ADDR INTC_IPRA
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#define TIMER_IPR_POS 3
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#define TIMER_IPR_POS 3
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#define TIMER_PRIORITY 2
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#define TIMER_PRIORITY 2
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/* TMU1 */
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/* TMU1 */
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#define TMU1_IRQ 17
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#define TMU1_IRQ 17
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#define TMU1_IPR_ADDR INTC_IPRA
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#define TMU1_IPR_ADDR INTC_IPRA
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#define TMU1_IPR_POS 2
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#define TMU1_IPR_POS 2
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#define TMU1_PRIORITY 2
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#define TMU1_PRIORITY 2
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/* TMU2 */
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/* TMU2 */
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#define TMU2_IRQ 18
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#define TMU2_IRQ 18
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#define TMU2_IPR_ADDR INTC_IPRA
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#define TMU2_IPR_ADDR INTC_IPRA
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#define TMU2_IPR_POS 1
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#define TMU2_IPR_POS 1
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#define TMU2_PRIORITY 2
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#define TMU2_PRIORITY 2
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/* WDT */
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/* WDT */
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#define WDT_IRQ 27
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#define WDT_IRQ 27
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#define WDT_IPR_ADDR INTC_IPRB
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#define WDT_IPR_ADDR INTC_IPRB
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#define WDT_IPR_POS 3
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#define WDT_IPR_POS 3
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#define WDT_PRIORITY 2
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#define WDT_PRIORITY 2
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/* SIM (SIM Card Module) */
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/* SIM (SIM Card Module) */
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#define SIM_ERI_IRQ 23
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#define SIM_ERI_IRQ 23
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#define SIM_RXI_IRQ 24
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#define SIM_RXI_IRQ 24
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#define SIM_TXI_IRQ 25
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#define SIM_TXI_IRQ 25
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#define SIM_TEND_IRQ 26
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#define SIM_TEND_IRQ 26
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#define SIM_IPR_ADDR INTC_IPRB
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#define SIM_IPR_ADDR INTC_IPRB
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#define SIM_IPR_POS 1
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#define SIM_IPR_POS 1
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#define SIM_PRIORITY 2
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#define SIM_PRIORITY 2
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/* VIO (Video I/O) */
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/* VIO (Video I/O) */
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#define VIO_IRQ 52
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#define VIO_IRQ 52
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#define VIO_IPR_ADDR INTC_IPRE
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#define VIO_IPR_ADDR INTC_IPRE
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#define VIO_IPR_POS 2
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#define VIO_IPR_POS 2
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#define VIO_PRIORITY 2
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#define VIO_PRIORITY 2
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/* MFI (Multi Functional Interface) */
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/* MFI (Multi Functional Interface) */
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#define MFI_IRQ 56
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#define MFI_IRQ 56
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#define MFI_IPR_ADDR INTC_IPRE
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#define MFI_IPR_ADDR INTC_IPRE
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#define MFI_IPR_POS 1
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#define MFI_IPR_POS 1
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#define MFI_PRIORITY 2
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#define MFI_PRIORITY 2
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/* VPU (Video Processing Unit) */
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/* VPU (Video Processing Unit) */
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#define VPU_IRQ 60
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#define VPU_IRQ 60
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#define VPU_IPR_ADDR INTC_IPRE
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#define VPU_IPR_ADDR INTC_IPRE
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#define VPU_IPR_POS 0
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#define VPU_IPR_POS 0
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#define VPU_PRIORITY 2
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#define VPU_PRIORITY 2
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/* KEY (Key Scan Interface) */
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/* KEY (Key Scan Interface) */
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#define KEY_IRQ 79
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#define KEY_IRQ 79
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#define KEY_IPR_ADDR INTC_IPRF
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#define KEY_IPR_ADDR INTC_IPRF
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#define KEY_IPR_POS 3
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#define KEY_IPR_POS 3
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#define KEY_PRIORITY 2
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#define KEY_PRIORITY 2
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/* CMT (Compare Match Timer) */
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/* CMT (Compare Match Timer) */
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#define CMT_IRQ 104
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#define CMT_IRQ 104
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#define CMT_IPR_ADDR INTC_IPRF
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#define CMT_IPR_ADDR INTC_IPRF
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#define CMT_IPR_POS 0
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#define CMT_IPR_POS 0
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#define CMT_PRIORITY 2
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#define CMT_PRIORITY 2
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/* DMAC(1) */
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/* DMAC(1) */
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#define DMTE0_IRQ 48
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#define DMTE0_IRQ 48
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#define DMTE1_IRQ 49
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#define DMTE1_IRQ 49
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#define DMTE2_IRQ 50
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#define DMTE2_IRQ 50
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#define DMTE3_IRQ 51
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#define DMTE3_IRQ 51
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#define DMA1_IPR_ADDR INTC_IPRE
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#define DMA1_IPR_ADDR INTC_IPRE
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#define DMA1_IPR_POS 3
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#define DMA1_IPR_POS 3
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#define DMA1_PRIORITY 7
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#define DMA1_PRIORITY 7
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/* DMAC(2) */
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/* DMAC(2) */
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#define DMTE4_IRQ 76
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#define DMTE4_IRQ 76
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#define DMTE5_IRQ 77
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#define DMTE5_IRQ 77
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#define DMA2_IPR_ADDR INTC_IPRF
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#define DMA2_IPR_ADDR INTC_IPRF
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#define DMA2_IPR_POS 2
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#define DMA2_IPR_POS 2
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#define DMA2_PRIORITY 7
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#define DMA2_PRIORITY 7
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/* SCIF0 */
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/* SCIF0 */
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#define SCIF0_IRQ 80
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#define SCIF0_IRQ 80
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#define SCIF0_IPR_ADDR INTC_IPRG
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#define SCIF0_IPR_ADDR INTC_IPRG
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#define SCIF0_IPR_POS 3
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#define SCIF0_IPR_POS 3
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#define SCIF0_PRIORITY 3
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#define SCIF0_PRIORITY 3
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/* SIOF0 */
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/* SIOF0 */
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#define SIOF0_IRQ 55
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#define SIOF0_IRQ 55
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#define SIOF0_IPR_ADDR INTC_IPRH
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#define SIOF0_IPR_ADDR INTC_IPRH
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#define SIOF0_IPR_POS 3
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#define SIOF0_IPR_POS 3
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#define SIOF0_PRIORITY 3
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#define SIOF0_PRIORITY 3
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/* FLCTL (Flash Memory Controller) */
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/* FLCTL (Flash Memory Controller) */
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#define FLSTE_IRQ 92
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#define FLSTE_IRQ 92
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#define FLTEND_IRQ 93
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#define FLTEND_IRQ 93
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#define FLTRQ0_IRQ 94
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#define FLTRQ0_IRQ 94
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#define FLTRQ1_IRQ 95
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#define FLTRQ1_IRQ 95
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#define FLCTL_IPR_ADDR INTC_IPRH
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#define FLCTL_IPR_ADDR INTC_IPRH
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#define FLCTL_IPR_POS 1
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#define FLCTL_IPR_POS 1
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#define FLCTL_PRIORITY 3
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#define FLCTL_PRIORITY 3
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/* IIC (IIC Bus Interface) */
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/* IIC (IIC Bus Interface) */
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#define IIC_ALI_IRQ 96
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#define IIC_ALI_IRQ 96
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#define IIC_TACKI_IRQ 97
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#define IIC_TACKI_IRQ 97
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#define IIC_WAITI_IRQ 98
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#define IIC_WAITI_IRQ 98
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#define IIC_DTEI_IRQ 99
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#define IIC_DTEI_IRQ 99
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#define IIC_IPR_ADDR INTC_IPRH
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#define IIC_IPR_ADDR INTC_IPRH
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#define IIC_IPR_POS 0
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#define IIC_IPR_POS 0
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#define IIC_PRIORITY 3
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#define IIC_PRIORITY 3
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/* SIO0 */
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/* SIO0 */
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#define SIO0_IRQ 88
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#define SIO0_IRQ 88
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#define SIO0_IPR_ADDR INTC_IPRI
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#define SIO0_IPR_ADDR INTC_IPRI
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#define SIO0_IPR_POS 3
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#define SIO0_IPR_POS 3
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#define SIO0_PRIORITY 3
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#define SIO0_PRIORITY 3
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/* SIU (Sound Interface Unit) */
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/* SIU (Sound Interface Unit) */
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#define SIU_IRQ 108
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#define SIU_IRQ 108
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#define SIU_IPR_ADDR INTC_IPRJ
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#define SIU_IPR_ADDR INTC_IPRJ
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#define SIU_IPR_POS 1
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#define SIU_IPR_POS 1
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#define SIU_PRIORITY 3
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#define SIU_PRIORITY 3
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/* ONCHIP_NR_IRQS */
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/* ONCHIP_NR_IRQS */
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#define NR_IRQS 109
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#define NR_IRQS 109
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/* In a generic kernel, NR_IRQS is an upper bound, and we should use
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/* In a generic kernel, NR_IRQS is an upper bound, and we should use
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* ACTUAL_NR_IRQS (which uses the machine vector) to get the correct value.
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* ACTUAL_NR_IRQS (which uses the machine vector) to get the correct value.
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*/
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*/
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#define ACTUAL_NR_IRQS NR_IRQS
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#define ACTUAL_NR_IRQS NR_IRQS
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extern void disable_irq(unsigned int);
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extern void disable_irq(unsigned int);
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extern void disable_irq_nosync(unsigned int);
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extern void disable_irq_nosync(unsigned int);
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extern void enable_irq(unsigned int);
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extern void enable_irq(unsigned int);
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/*
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/*
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* Simple Mask Register Support
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* Simple Mask Register Support
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*/
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*/
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extern void make_maskreg_irq(unsigned int irq);
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extern void make_maskreg_irq(unsigned int irq);
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extern unsigned short *irq_mask_register;
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extern unsigned short *irq_mask_register;
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/*
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/*
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* Function for "on chip support modules".
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* Function for "on chip support modules".
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*/
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*/
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extern void make_ipr_irq(unsigned int irq, unsigned int addr,
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extern void make_ipr_irq(unsigned int irq, unsigned int addr,
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int pos, int priority);
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int pos, int priority);
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extern void make_imask_irq(unsigned int irq);
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extern void make_imask_irq(unsigned int irq);
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#define PORT_PACR 0xA4050100UL
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#define PORT_PACR 0xA4050100UL
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#define PORT_PBCR 0xA4050102UL
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#define PORT_PBCR 0xA4050102UL
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#define PORT_PCCR 0xA4050104UL
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#define PORT_PCCR 0xA4050104UL
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#define PORT_PDCR 0xA4050106UL
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#define PORT_PDCR 0xA4050106UL
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#define PORT_PECR 0xA4050108UL
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#define PORT_PECR 0xA4050108UL
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#define PORT_PFCR 0xA405010AUL
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#define PORT_PFCR 0xA405010AUL
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#define PORT_PGCR 0xA405010CUL
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#define PORT_PGCR 0xA405010CUL
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#define PORT_PHCR 0xA405010EUL
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#define PORT_PHCR 0xA405010EUL
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#define PORT_PJCR 0xA4050110UL
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#define PORT_PJCR 0xA4050110UL
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#define PORT_PKCR 0xA4050112UL
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#define PORT_PKCR 0xA4050112UL
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#define PORT_PLCR 0xA4050114UL
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#define PORT_PLCR 0xA4050114UL
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#define PORT_SCPCR 0xA4050116UL
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#define PORT_SCPCR 0xA4050116UL
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#define PORT_PMCR 0xA4050118UL
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#define PORT_PMCR 0xA4050118UL
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#define PORT_PNCR 0xA405011AUL
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#define PORT_PNCR 0xA405011AUL
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#define PORT_PQCR 0xA405011CUL
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#define PORT_PQCR 0xA405011CUL
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#define PORT_PSELA 0xA4050140UL
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#define PORT_PSELA 0xA4050140UL
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#define PORT_PSELB 0xA4050142UL
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#define PORT_PSELB 0xA4050142UL
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#define PORT_PSELC 0xA4050144UL
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#define PORT_PSELC 0xA4050144UL
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#define PORT_HIZCRA 0xA4050146UL
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#define PORT_HIZCRA 0xA4050146UL
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#define PORT_HIZCRB 0xA4050148UL
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#define PORT_HIZCRB 0xA4050148UL
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#define PORT_DRVCR 0xA4050150UL
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#define PORT_DRVCR 0xA4050150UL
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#define PORT_PADR 0xA4050120UL
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#define PORT_PADR 0xA4050120UL
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#define PORT_PBDR 0xA4050122UL
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#define PORT_PBDR 0xA4050122UL
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#define PORT_PCDR 0xA4050124UL
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#define PORT_PCDR 0xA4050124UL
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#define PORT_PDDR 0xA4050126UL
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#define PORT_PDDR 0xA4050126UL
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#define PORT_PEDR 0xA4050128UL
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#define PORT_PEDR 0xA4050128UL
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#define PORT_PFDR 0xA405012AUL
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#define PORT_PFDR 0xA405012AUL
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#define PORT_PGDR 0xA405012CUL
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#define PORT_PGDR 0xA405012CUL
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#define PORT_PHDR 0xA405012EUL
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#define PORT_PHDR 0xA405012EUL
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#define PORT_PJDR 0xA4050130UL
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#define PORT_PJDR 0xA4050130UL
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#define PORT_PKDR 0xA4050132UL
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#define PORT_PKDR 0xA4050132UL
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#define PORT_PLDR 0xA4050134UL
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#define PORT_PLDR 0xA4050134UL
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#define PORT_SCPDR 0xA4050136UL
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#define PORT_SCPDR 0xA4050136UL
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#define PORT_PMDR 0xA4050138UL
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#define PORT_PMDR 0xA4050138UL
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#define PORT_PNDR 0xA405013AUL
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#define PORT_PNDR 0xA405013AUL
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#define PORT_PQDR 0xA405013CUL
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#define PORT_PQDR 0xA405013CUL
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#define IRQ0_IRQ 32
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#define IRQ0_IRQ 32
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#define IRQ1_IRQ 33
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#define IRQ1_IRQ 33
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#define IRQ2_IRQ 34
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#define IRQ2_IRQ 34
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#define IRQ3_IRQ 35
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#define IRQ3_IRQ 35
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#define IRQ4_IRQ 36
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#define IRQ4_IRQ 36
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#define IRQ5_IRQ 37
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#define IRQ5_IRQ 37
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#define IRQ0_IPR_ADDR INTC_IPRC
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#define IRQ0_IPR_ADDR INTC_IPRC
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#define IRQ1_IPR_ADDR INTC_IPRC
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#define IRQ1_IPR_ADDR INTC_IPRC
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#define IRQ2_IPR_ADDR INTC_IPRC
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#define IRQ2_IPR_ADDR INTC_IPRC
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#define IRQ3_IPR_ADDR INTC_IPRC
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#define IRQ3_IPR_ADDR INTC_IPRC
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#define IRQ4_IPR_ADDR INTC_IPRD
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#define IRQ4_IPR_ADDR INTC_IPRD
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#define IRQ5_IPR_ADDR INTC_IPRD
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#define IRQ5_IPR_ADDR INTC_IPRD
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#define IRQ0_IPR_POS 0
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#define IRQ0_IPR_POS 0
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#define IRQ1_IPR_POS 1
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#define IRQ1_IPR_POS 1
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#define IRQ2_IPR_POS 2
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#define IRQ2_IPR_POS 2
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#define IRQ3_IPR_POS 3
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#define IRQ3_IPR_POS 3
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#define IRQ4_IPR_POS 0
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#define IRQ4_IPR_POS 0
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#define IRQ5_IPR_POS 1
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#define IRQ5_IPR_POS 1
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#define IRQ0_PRIORITY 1
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#define IRQ0_PRIORITY 1
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#define IRQ1_PRIORITY 1
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#define IRQ1_PRIORITY 1
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#define IRQ2_PRIORITY 1
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#define IRQ2_PRIORITY 1
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#define IRQ3_PRIORITY 1
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#define IRQ3_PRIORITY 1
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#define IRQ4_PRIORITY 1
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#define IRQ4_PRIORITY 1
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#define IRQ5_PRIORITY 1
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#define IRQ5_PRIORITY 1
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extern int ipr_irq_demux(int irq);
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extern int ipr_irq_demux(int irq);
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#define __irq_demux(irq) ipr_irq_demux(irq)
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#define __irq_demux(irq) ipr_irq_demux(irq)
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#define irq_demux(irq) __irq_demux(irq)
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#define irq_demux(irq) __irq_demux(irq)
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#endif /* __ASM_SH_IRQ_SH7300_H */
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#endif /* __ASM_SH_IRQ_SH7300_H */
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