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Rev 1765 |
// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/FDRE_1.v,v 1.1.1.1 2001-11-04 18:59:47 lampret Exp $
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// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/FDRE_1.v,v 1.1.1.1 2001-11-04 18:59:47 lampret Exp $
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/*
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/*
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FUNCTION : D-FLIP-FLOP with sync reset and clock enable
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FUNCTION : D-FLIP-FLOP with sync reset and clock enable
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*/
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*/
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`timescale 100 ps / 10 ps
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`timescale 100 ps / 10 ps
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`celldefine
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`celldefine
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module FDRE_1 (Q, C, CE, D, R);
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module FDRE_1 (Q, C, CE, D, R);
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parameter cds_action = "ignore";
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parameter cds_action = "ignore";
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parameter INIT = 1'b0;
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parameter INIT = 1'b0;
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output Q;
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output Q;
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reg q_out;
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reg q_out;
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input C, CE, D, R;
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input C, CE, D, R;
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tri0 GSR = glbl.GSR;
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tri0 GSR = glbl.GSR;
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buf B1 (Q, q_out);
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buf B1 (Q, q_out);
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always @(GSR)
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always @(GSR)
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if (GSR)
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if (GSR)
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assign q_out = INIT;
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assign q_out = INIT;
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else
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else
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deassign q_out;
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deassign q_out;
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always @(negedge C)
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always @(negedge C)
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if (R)
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if (R)
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q_out <= 0;
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q_out <= 0;
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else if (CE)
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else if (CE)
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q_out <= D;
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q_out <= D;
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specify
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specify
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if (R)
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if (R)
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(negedge C => (Q +: 1'b0)) = (1, 1);
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(negedge C => (Q +: 1'b0)) = (1, 1);
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if (!R && CE)
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if (!R && CE)
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(negedge C => (Q +: D)) = (1, 1);
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(negedge C => (Q +: D)) = (1, 1);
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endspecify
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endspecify
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endmodule
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endmodule
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`endcelldefine
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`endcelldefine
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