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[/] [or1k/] [trunk/] [mp3/] [lib/] [xilinx/] [unisims/] [IBUFGDS_LDT_25.v] - Diff between revs 266 and 1765

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Rev 266 Rev 1765
// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/IBUFGDS_LDT_25.v,v 1.1.1.1 2001-11-04 18:59:48 lampret Exp $
// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/IBUFGDS_LDT_25.v,v 1.1.1.1 2001-11-04 18:59:48 lampret Exp $
 
 
/*
/*
 
 
FUNCTION        : INPUT BUFFER
FUNCTION        : INPUT BUFFER
 
 
*/
*/
 
 
`timescale  100 ps / 10 ps
`timescale  100 ps / 10 ps
 
 
`celldefine
`celldefine
 
 
module IBUFGDS_LDT_25 (O, I, IB);
module IBUFGDS_LDT_25 (O, I, IB);
 
 
    parameter cds_action = "ignore";
    parameter cds_action = "ignore";
 
 
    output O;
    output O;
 
 
    reg o_out;
    reg o_out;
 
 
    input  I, IB;
    input  I, IB;
 
 
    buf b_0 (O, o_out);
    buf b_0 (O, o_out);
 
 
    always @(I or IB) begin
    always @(I or IB) begin
        if (I == 1'b1 && IB == 1'b0)
        if (I == 1'b1 && IB == 1'b0)
            o_out <= I;
            o_out <= I;
        else if (I == 1'b0 && IB == 1'b1)
        else if (I == 1'b0 && IB == 1'b1)
            o_out <= I;
            o_out <= I;
    end
    end
 
 
    specify
    specify
        (I *> O) = (1, 1);
        (I *> O) = (1, 1);
    endspecify
    endspecify
 
 
endmodule
endmodule
 
 
`endcelldefine
`endcelldefine
 
 
 
 

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