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[/] [or1k/] [trunk/] [mp3/] [lib/] [xilinx/] [unisims/] [IBUFGDS_LVPECL_33.v] - Diff between revs 266 and 1765
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Rev 1765 |
// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/IBUFGDS_LVPECL_33.v,v 1.1.1.1 2001-11-04 18:59:48 lampret Exp $
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// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/IBUFGDS_LVPECL_33.v,v 1.1.1.1 2001-11-04 18:59:48 lampret Exp $
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/*
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/*
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FUNCTION : INPUT BUFFER
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FUNCTION : INPUT BUFFER
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*/
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*/
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`timescale 100 ps / 10 ps
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`timescale 100 ps / 10 ps
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`celldefine
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`celldefine
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module IBUFGDS_LVPECL_33 (O, I, IB);
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module IBUFGDS_LVPECL_33 (O, I, IB);
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parameter cds_action = "ignore";
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parameter cds_action = "ignore";
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output O;
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output O;
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input I, IB;
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input I, IB;
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reg o_out;
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reg o_out;
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buf b_0 (O, o_out);
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buf b_0 (O, o_out);
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always @(I or IB) begin
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always @(I or IB) begin
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if (I == 1'b1 && IB == 1'b0)
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if (I == 1'b1 && IB == 1'b0)
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o_out <= I;
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o_out <= I;
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else if (I == 1'b0 && IB == 1'b1)
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else if (I == 1'b0 && IB == 1'b1)
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o_out <= I;
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o_out <= I;
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end
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end
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specify
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specify
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(I *> O) = (1, 1);
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(I *> O) = (1, 1);
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endspecify
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endspecify
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endmodule
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endmodule
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`endcelldefine
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`endcelldefine
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