URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [mp3/] [lib/] [xilinx/] [unisims/] [LDP.v] - Diff between revs 266 and 1765

Rev 266	Rev 1765
`// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/LDP.v,v 1.1.1.1 2001-11-04 18:59:48 lampret Exp $`	`// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/LDP.v,v 1.1.1.1 2001-11-04 18:59:48 lampret Exp $`

`/*`	`/*`

`FUNCTION : D-LATCH with async preset`	`FUNCTION : D-LATCH with async preset`

`*/`	`*/`

`timescale 100 ps / 10 ps	`timescale 100 ps / 10 ps

`celldefine	`celldefine

`module LDP (Q, D, G, PRE);`	`module LDP (Q, D, G, PRE);`

`parameter cds_action = "ignore";`	`parameter cds_action = "ignore";`
`parameter INIT = 1'b1;`	`parameter INIT = 1'b1;`

`output Q;`	`output Q;`
`reg q_out;`	`reg q_out;`

`input D, G, PRE;`	`input D, G, PRE;`

`tri0 GSR = glbl.GSR;`	`tri0 GSR = glbl.GSR;`

`buf B1 (Q, q_out);`	`buf B1 (Q, q_out);`

`always @(GSR or PRE or D or G)`	`always @(GSR or PRE or D or G)`
`if (GSR)`	`if (GSR)`
`q_out <= INIT;`	`q_out <= INIT;`
`else if (PRE)`	`else if (PRE)`
`q_out <= 1;`	`q_out <= 1;`
`else if (G)`	`else if (G)`
`q_out <= D;`	`q_out <= D;`

`specify`	`specify`
`if (!PRE && G)`	`if (!PRE && G)`
`(D +=> Q) = (1, 1);`	`(D +=> Q) = (1, 1);`
`if (!PRE)`	`if (!PRE)`
`(posedge G => (Q +: D)) = (1, 1);`	`(posedge G => (Q +: D)) = (1, 1);`
`(posedge PRE => (Q +: 1'b1)) = (1, 1);`	`(posedge PRE => (Q +: 1'b1)) = (1, 1);`
`endspecify`	`endspecify`

`endmodule`	`endmodule`

`endcelldefine	`endcelldefine