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Rev 1765 |
// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/NOR5B3.v,v 1.1.1.1 2001-11-04 18:59:49 lampret Exp $
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// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/NOR5B3.v,v 1.1.1.1 2001-11-04 18:59:49 lampret Exp $
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/*
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/*
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FUNCTION : 5-INPUT NOR GATE
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FUNCTION : 5-INPUT NOR GATE
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*/
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*/
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`timescale 100 ps / 10 ps
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`timescale 100 ps / 10 ps
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`celldefine
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`celldefine
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module NOR5B3 (O, I0, I1, I2, I3, I4);
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module NOR5B3 (O, I0, I1, I2, I3, I4);
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parameter cds_action = "ignore";
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parameter cds_action = "ignore";
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output O;
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output O;
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input I0, I1, I2, I3, I4;
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input I0, I1, I2, I3, I4;
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not N2 (i2_inv, I2);
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not N2 (i2_inv, I2);
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not N1 (i1_inv, I1);
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not N1 (i1_inv, I1);
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not N0 (i0_inv, I0);
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not N0 (i0_inv, I0);
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nor O1 (O, i0_inv, i1_inv, i2_inv, I3, I4);
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nor O1 (O, i0_inv, i1_inv, i2_inv, I3, I4);
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specify
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specify
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(I0 *> O) = (1, 1);
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(I0 *> O) = (1, 1);
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(I1 *> O) = (1, 1);
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(I1 *> O) = (1, 1);
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(I2 *> O) = (1, 1);
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(I2 *> O) = (1, 1);
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(I3 *> O) = (1, 1);
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(I3 *> O) = (1, 1);
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(I4 *> O) = (1, 1);
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(I4 *> O) = (1, 1);
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endspecify
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endspecify
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endmodule
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endmodule
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`endcelldefine
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`endcelldefine
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